Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.r061-tall-162038392800180.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
..................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is DLCflexbar-PT-3a, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r061-tall-162038392800180
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.4M
-rw-r--r-- 1 mcc users 14K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 129K May 5 16:58 CTLCardinality.xml
-rw-r--r-- 1 mcc users 9.7K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 82K May 5 16:58 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.2K Mar 28 15:56 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Mar 28 15:56 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Mar 28 15:57 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Mar 28 15:57 LTLFireability.xml
-rw-r--r-- 1 mcc users 2.9K Mar 23 03:46 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 14K Mar 23 03:46 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Mar 22 13:46 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 16K Mar 22 13:46 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 22 09:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Mar 22 09:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 3 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 996K May 5 16:51 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-3a-00
FORMULA_NAME DLCflexbar-PT-3a-01
FORMULA_NAME DLCflexbar-PT-3a-02
FORMULA_NAME DLCflexbar-PT-3a-03
FORMULA_NAME DLCflexbar-PT-3a-04
FORMULA_NAME DLCflexbar-PT-3a-05
FORMULA_NAME DLCflexbar-PT-3a-06
FORMULA_NAME DLCflexbar-PT-3a-07
FORMULA_NAME DLCflexbar-PT-3a-08
FORMULA_NAME DLCflexbar-PT-3a-09
FORMULA_NAME DLCflexbar-PT-3a-10
FORMULA_NAME DLCflexbar-PT-3a-11
FORMULA_NAME DLCflexbar-PT-3a-12
FORMULA_NAME DLCflexbar-PT-3a-13
FORMULA_NAME DLCflexbar-PT-3a-14
FORMULA_NAME DLCflexbar-PT-3a-15

=== Now, execution of the tool begins

BK_START 1620435562154

starting LoLA
BK_INPUT DLCflexbar-PT-3a
BK_EXAMINATION: LTLCardinality
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
LTLCardinality

FORMULA DLCflexbar-PT-3a-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-3a-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-3a-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-3a-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-3a-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1620435679070

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:144
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:144
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:424
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:524
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:409
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:524
lola: rewrite Frontend/Parser/formula_rewrite.k:114
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:424
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:409
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:184
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:527
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:144
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:518
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 52 (type SKEL/SRCH) for 0 DLCflexbar-PT-3a-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 52 (type SKEL/SRCH) for DLCflexbar-PT-3a-00
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 55 (type SKEL/FNDP) for 12 DLCflexbar-PT-3a-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type SKEL/EQUN) for 12 DLCflexbar-PT-3a-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 57 (type SKEL/SRCH) for 12 DLCflexbar-PT-3a-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 58 (type SKEL/SRCH) for 12 DLCflexbar-PT-3a-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
sara: try reading problem file /home/mcc/execution/LTLCardinality-56.sara.
lola: FINISHED task # 57 (type SKEL/SRCH) for DLCflexbar-PT-3a-04
lola: result : false
lola: markings : 8
lola: fired transitions : 24
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 55 (type FNDP) for DLCflexbar-PT-3a-04 (obsolete)
lola: CANCELED task # 56 (type EQUN) for DLCflexbar-PT-3a-04 (obsolete)
lola: CANCELED task # 58 (type SRCH) for DLCflexbar-PT-3a-04 (obsolete)
lola: FINISHED task # 56 (type SKEL/EQUN) for DLCflexbar-PT-3a-04
lola: result : unknown
lola: NOTDEADLOCKFREE
lola: Rule S: 0 transitions removed,0 places removed
lola: FINISHED task # 58 (type SKEL/SRCH) for DLCflexbar-PT-3a-04
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 59 (type SKEL/SRCH) for 22 DLCflexbar-PT-3a-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 59 (type SKEL/SRCH) for DLCflexbar-PT-3a-06
lola: result : false
lola: markings : 13
lola: fired transitions : 13
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 10 (type CNST) for 9 DLCflexbar-PT-3a-03
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 29 (type CNST) for 28 DLCflexbar-PT-3a-08
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 10 (type CNST) for DLCflexbar-PT-3a-03
lola: result : true
lola: LAUNCH INITIAL
lola: LAUNCH task # 32 (type CNST) for 31 DLCflexbar-PT-3a-09
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 32 (type CNST) for DLCflexbar-PT-3a-09
lola: result : true
lola: FINISHED task # 29 (type CNST) for DLCflexbar-PT-3a-08
lola: result : false
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: planning for (null) stopped (result already fixed).
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 60 (type SKEL/SRCH) for 43 DLCflexbar-PT-3a-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 60 (type SKEL/SRCH) for DLCflexbar-PT-3a-13
lola: result : false
lola: markings : 36
lola: fired transitions : 36
lola: time used : 0.000000
lola: memory pages used : 1
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 61 (type EXCL) for 37 DLCflexbar-PT-3a-11
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 61 (type EXCL) for DLCflexbar-PT-3a-11
lola: result : true
lola: markings : 2
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 DLCflexbar-PT-3a-00
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for DLCflexbar-PT-3a-00
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 20 (type EXCL) for 19 DLCflexbar-PT-3a-05
lola: time limit : 327 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-00: LTL/CTL true LTL model checker
DLCflexbar-PT-3a-03: INITIAL true preprocessing
DLCflexbar-PT-3a-08: INITIAL false preprocessing
DLCflexbar-PT-3a-09: INITIAL true preprocessing
DLCflexbar-PT-3a-11: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-04: CONJ 0 1 0 0 5 0 0 1
DLCflexbar-PT-3a-05: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 4/327 1/32 DLCflexbar-PT-3a-05 88856 m, 17771 m/sec, 3391993 t fired, .

Time elapsed: 6 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-00: LTL/CTL true LTL model checker
DLCflexbar-PT-3a-03: INITIAL true preprocessing
DLCflexbar-PT-3a-08: INITIAL false preprocessing
DLCflexbar-PT-3a-09: INITIAL true preprocessing
DLCflexbar-PT-3a-11: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-04: CONJ 0 1 0 0 5 0 0 1
DLCflexbar-PT-3a-05: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 9/327 2/32 DLCflexbar-PT-3a-05 208399 m, 23908 m/sec, 7922169 t fired, .

Time elapsed: 11 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-00: LTL/CTL true LTL model checker
DLCflexbar-PT-3a-03: INITIAL true preprocessing
DLCflexbar-PT-3a-08: INITIAL false preprocessing
DLCflexbar-PT-3a-09: INITIAL true preprocessing
DLCflexbar-PT-3a-11: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-04: CONJ 0 1 0 0 5 0 0 1
DLCflexbar-PT-3a-05: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 14/327 3/32 DLCflexbar-PT-3a-05 329094 m, 24139 m/sec, 12526760 t fired, .

Time elapsed: 16 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-00: LTL/CTL true LTL model checker
DLCflexbar-PT-3a-03: INITIAL true preprocessing
DLCflexbar-PT-3a-08: INITIAL false preprocessing
DLCflexbar-PT-3a-09: INITIAL true preprocessing
DLCflexbar-PT-3a-11: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-04: CONJ 0 1 0 0 5 0 0 1
DLCflexbar-PT-3a-05: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 19/327 3/32 DLCflexbar-PT-3a-05 448860 m, 23953 m/sec, 17065461 t fired, .

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DLCflexbar-PT-3a-00: LTL/CTL true LTL model checker
DLCflexbar-PT-3a-03: INITIAL true preprocessing
DLCflexbar-PT-3a-08: INITIAL false preprocessing
DLCflexbar-PT-3a-09: INITIAL true preprocessing
DLCflexbar-PT-3a-11: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-04: CONJ 0 1 0 0 5 0 0 1
DLCflexbar-PT-3a-05: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 24/327 4/32 DLCflexbar-PT-3a-05 568836 m, 23995 m/sec, 21637846 t fired, .

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DLCflexbar-PT-3a-00: LTL/CTL true LTL model checker
DLCflexbar-PT-3a-03: INITIAL true preprocessing
DLCflexbar-PT-3a-08: INITIAL false preprocessing
DLCflexbar-PT-3a-09: INITIAL true preprocessing
DLCflexbar-PT-3a-11: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-04: CONJ 0 1 0 0 5 0 0 1
DLCflexbar-PT-3a-05: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 29/327 5/32 DLCflexbar-PT-3a-05 688408 m, 23914 m/sec, 26170418 t fired, .

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DLCflexbar-PT-3a-03: INITIAL true preprocessing
DLCflexbar-PT-3a-08: INITIAL false preprocessing
DLCflexbar-PT-3a-09: INITIAL true preprocessing
DLCflexbar-PT-3a-11: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-04: CONJ 0 1 0 0 5 0 0 1
DLCflexbar-PT-3a-05: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 34/327 6/32 DLCflexbar-PT-3a-05 807146 m, 23747 m/sec, 30688320 t fired, .

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DLCflexbar-PT-3a-00: LTL/CTL true LTL model checker
DLCflexbar-PT-3a-03: INITIAL true preprocessing
DLCflexbar-PT-3a-08: INITIAL false preprocessing
DLCflexbar-PT-3a-09: INITIAL true preprocessing
DLCflexbar-PT-3a-11: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-04: CONJ 0 1 0 0 5 0 0 1
DLCflexbar-PT-3a-05: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 39/327 6/32 DLCflexbar-PT-3a-05 924914 m, 23553 m/sec, 35163509 t fired, .

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DLCflexbar-PT-3a-00: LTL/CTL true LTL model checker
DLCflexbar-PT-3a-03: INITIAL true preprocessing
DLCflexbar-PT-3a-08: INITIAL false preprocessing
DLCflexbar-PT-3a-09: INITIAL true preprocessing
DLCflexbar-PT-3a-11: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-04: CONJ 0 1 0 0 5 0 0 1
DLCflexbar-PT-3a-05: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 44/327 7/32 DLCflexbar-PT-3a-05 1042578 m, 23532 m/sec, 39633550 t fired, .

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DLCflexbar-PT-3a-00: LTL/CTL true LTL model checker
DLCflexbar-PT-3a-03: INITIAL true preprocessing
DLCflexbar-PT-3a-08: INITIAL false preprocessing
DLCflexbar-PT-3a-09: INITIAL true preprocessing
DLCflexbar-PT-3a-11: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-04: CONJ 0 1 0 0 5 0 0 1
DLCflexbar-PT-3a-05: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 49/327 8/32 DLCflexbar-PT-3a-05 1161977 m, 23879 m/sec, 44181047 t fired, .

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DLCflexbar-PT-3a-00: LTL/CTL true LTL model checker
DLCflexbar-PT-3a-03: INITIAL true preprocessing
DLCflexbar-PT-3a-08: INITIAL false preprocessing
DLCflexbar-PT-3a-09: INITIAL true preprocessing
DLCflexbar-PT-3a-11: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-04: CONJ 0 1 0 0 5 0 0 1
DLCflexbar-PT-3a-05: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 54/327 9/32 DLCflexbar-PT-3a-05 1281335 m, 23871 m/sec, 48702563 t fired, .

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DLCflexbar-PT-3a-00: LTL/CTL true LTL model checker
DLCflexbar-PT-3a-03: INITIAL true preprocessing
DLCflexbar-PT-3a-08: INITIAL false preprocessing
DLCflexbar-PT-3a-09: INITIAL true preprocessing
DLCflexbar-PT-3a-11: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-04: CONJ 0 1 0 0 5 0 0 1
DLCflexbar-PT-3a-05: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 59/327 10/32 DLCflexbar-PT-3a-05 1399784 m, 23689 m/sec, 53207915 t fired, .

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DLCflexbar-PT-3a-00: LTL/CTL true LTL model checker
DLCflexbar-PT-3a-03: INITIAL true preprocessing
DLCflexbar-PT-3a-08: INITIAL false preprocessing
DLCflexbar-PT-3a-09: INITIAL true preprocessing
DLCflexbar-PT-3a-11: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-04: CONJ 0 1 0 0 5 0 0 1
DLCflexbar-PT-3a-05: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 64/327 10/32 DLCflexbar-PT-3a-05 1518720 m, 23787 m/sec, 57642996 t fired, .

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DLCflexbar-PT-3a-00: LTL/CTL true LTL model checker
DLCflexbar-PT-3a-03: INITIAL true preprocessing
DLCflexbar-PT-3a-08: INITIAL false preprocessing
DLCflexbar-PT-3a-09: INITIAL true preprocessing
DLCflexbar-PT-3a-11: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-04: CONJ 0 1 0 0 5 0 0 1
DLCflexbar-PT-3a-05: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 69/327 11/32 DLCflexbar-PT-3a-05 1670601 m, 30376 m/sec, 61962534 t fired, .

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DLCflexbar-PT-3a-00: LTL/CTL true LTL model checker
DLCflexbar-PT-3a-03: INITIAL true preprocessing
DLCflexbar-PT-3a-08: INITIAL false preprocessing
DLCflexbar-PT-3a-09: INITIAL true preprocessing
DLCflexbar-PT-3a-11: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-04: CONJ 0 1 0 0 5 0 0 1
DLCflexbar-PT-3a-05: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 74/327 12/32 DLCflexbar-PT-3a-05 1819872 m, 29854 m/sec, 66218124 t fired, .

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DLCflexbar-PT-3a-00: LTL/CTL true LTL model checker
DLCflexbar-PT-3a-03: INITIAL true preprocessing
DLCflexbar-PT-3a-08: INITIAL false preprocessing
DLCflexbar-PT-3a-09: INITIAL true preprocessing
DLCflexbar-PT-3a-11: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-04: CONJ 0 1 0 0 5 0 0 1
DLCflexbar-PT-3a-05: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 79/327 13/32 DLCflexbar-PT-3a-05 1966336 m, 29292 m/sec, 70396200 t fired, .

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DLCflexbar-PT-3a-00: LTL/CTL true LTL model checker
DLCflexbar-PT-3a-03: INITIAL true preprocessing
DLCflexbar-PT-3a-08: INITIAL false preprocessing
DLCflexbar-PT-3a-09: INITIAL true preprocessing
DLCflexbar-PT-3a-11: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-04: CONJ 0 1 0 0 5 0 0 1
DLCflexbar-PT-3a-05: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 84/327 14/32 DLCflexbar-PT-3a-05 2113829 m, 29498 m/sec, 74595869 t fired, .

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DLCflexbar-PT-3a-00: LTL/CTL true LTL model checker
DLCflexbar-PT-3a-03: INITIAL true preprocessing
DLCflexbar-PT-3a-08: INITIAL false preprocessing
DLCflexbar-PT-3a-09: INITIAL true preprocessing
DLCflexbar-PT-3a-11: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-04: CONJ 0 1 0 0 5 0 0 1
DLCflexbar-PT-3a-05: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 89/327 15/32 DLCflexbar-PT-3a-05 2260137 m, 29261 m/sec, 78764047 t fired, .

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DLCflexbar-PT-3a-00: LTL/CTL true LTL model checker
DLCflexbar-PT-3a-03: INITIAL true preprocessing
DLCflexbar-PT-3a-08: INITIAL false preprocessing
DLCflexbar-PT-3a-09: INITIAL true preprocessing
DLCflexbar-PT-3a-11: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-04: CONJ 0 1 0 0 5 0 0 1
DLCflexbar-PT-3a-05: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 94/327 16/32 DLCflexbar-PT-3a-05 2408009 m, 29574 m/sec, 82983270 t fired, .

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20 LTL EXCL 99/327 17/32 DLCflexbar-PT-3a-05 2556292 m, 29656 m/sec, 87199827 t fired, .

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/home/mcc/BenchKit/BenchKit_head.sh: line 62: 414 Killed lola --conf=$BIN_DIR/configfiles/ltlcardinalityconf --formula=$DIR/LTLCardinality.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-3a"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-3a, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r061-tall-162038392800180"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-3a.tgz
mv DLCflexbar-PT-3a execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;