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Model Checking Contest 2021
11th edition, Paris, France, June 23, 2021
Execution of r023-tajo-162038139400246
Last Updated
Jun 28, 2021

About the Execution of LoLA for BridgeAndVehicles-PT-V50P20N50

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
2855.691 56241.00 177815.00 22.70 TTFTFTFFTFTFTFTT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/mnt/tpsp/fkordon/mcc2021-input.r023-tajo-162038139400246.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
...................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is BridgeAndVehicles-PT-V50P20N50, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r023-tajo-162038139400246
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 28M
-rw-r--r-- 1 mcc users 125K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 578K May 10 09:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 3.8M May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 15M May 10 09:42 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 8.1K Mar 28 15:47 LTLCardinality.txt
-rw-r--r-- 1 mcc users 37K Mar 28 15:47 LTLCardinality.xml
-rw-r--r-- 1 mcc users 409K Mar 28 15:47 LTLFireability.txt
-rw-r--r-- 1 mcc users 1.3M Mar 28 15:47 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Mar 23 02:52 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 35K Mar 23 02:52 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 364K Mar 22 11:23 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 1.1M Mar 22 11:23 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Mar 22 09:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Mar 22 09:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 10 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 6.0M May 5 16:51 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00
FORMULA_NAME BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-01
FORMULA_NAME BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-02
FORMULA_NAME BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03
FORMULA_NAME BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-04
FORMULA_NAME BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-05
FORMULA_NAME BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-06
FORMULA_NAME BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07
FORMULA_NAME BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-08
FORMULA_NAME BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09
FORMULA_NAME BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-10
FORMULA_NAME BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11
FORMULA_NAME BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-12
FORMULA_NAME BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13
FORMULA_NAME BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14
FORMULA_NAME BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1620860859228

starting LoLA
BK_INPUT BridgeAndVehicles-PT-V50P20N50
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
ReachabilityCardinality

FORMULA BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1620860915469

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-02: INITIAL 0 0 0 0 0 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03: AG 0 0 0 0 0 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-04: INITIAL 0 0 0 0 0 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-05: INITIAL 0 0 0 0 0 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-06: INITIAL 0 0 0 0 0 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-08: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-10: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-12: EF 0 0 0 0 0 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13: AG 0 0 0 0 0 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15: AG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 5 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 13 (type CNST) for 12 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-04
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 19 (type CNST) for 18 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-06
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 16 (type CNST) for 15 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-05
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 19 (type CNST) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-06
lola: result : false
lola: FINISHED task # 13 (type CNST) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-04
lola: result : false
lola: FINISHED task # 16 (type CNST) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-05
lola: result : true
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 7 (type CNST) for 6 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-02
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 7 (type CNST) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-02
lola: result : false
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-02: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-04: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-05: INITIAL true preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-06: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-08: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-10: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-12: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15: AG 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 10 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 52 (type EXCL) for 0 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00
lola: time limit : 298 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 48 (type FNDP) for 0 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 49 (type EQUN) for 0 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 51 (type SRCH) for 0 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-49.sara.
lola: FINISHED task # 52 (type EXCL) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00
lola: result : true
lola: markings : 101
lola: fired transitions : 100
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 48 (type FNDP) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 49 (type EQUN) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 51 (type SRCH) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00 (obsolete)
lola: FINISHED task # 49 (type EQUN) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00
lola: result : unknown
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-02: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-04: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-05: INITIAL true preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-06: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-08: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-10: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-12: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15: AG 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 15 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: FINISHED task # 48 (type FNDP) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00
lola: result : true
lola: fired transitions : 60
lola: tried executions : 1
lola: time used : 3.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 63 (type EXCL) for 39 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13
lola: time limit : 325 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 59 (type FNDP) for 39 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 60 (type EQUN) for 39 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: memory limit: 5 pages
lola: LAUNCH task # 62 (type SRCH) for 39 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 59 (type FNDP) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13
lola: result : true
lola: fired transitions : 28
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 60 (type EQUN) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13 (obsolete)
lola: CANCELED task # 62 (type SRCH) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13 (obsolete)
lola: CANCELED task # 63 (type EXCL) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13 (obsolete)
lola: LAUNCH task # 72 (type EXCL) for 24 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-08
lola: time limit : 358 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 55 (type FNDP) for 9 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 57 (type EQUN) for 9 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 64 (type SRCH) for 9 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 60 (type EQUN) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 72 (type EXCL) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-08
lola: result : true
lola: markings : 55
lola: fired transitions : 54
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 65 (type EXCL) for 9 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03
lola: time limit : 397 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-57.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-02: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-04: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-05: INITIAL true preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-06: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-08: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03: AG 0 1 4 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-10: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-12: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15: AG 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 EF FNDP 1/1789 0/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03 --
57 EF STEQ 1/3580 0/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03 sara is running.
64 EF SRCH 1/3580 1/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03 --
65 EF EXCL 0/397 1/32 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03 --

Time elapsed: 20 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-02: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-04: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-05: INITIAL true preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-06: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-08: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03: AG 0 1 4 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 EF FNDP 6/295 0/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03 12206 t fired, 37 attempts, .
57 EF STEQ 6/295 0/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03 sara is running.
64 EF SRCH 6/295 1/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03 6094 m, 1218 m/sec, 11582 t fired, .
65 EF EXCL 5/397 1/32 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03 181 m, 36 m/sec, 180 t fired, .

Time elapsed: 25 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 57 (type EQUN) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03
lola: result : false
lola: CANCELED task # 55 (type FNDP) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 64 (type SRCH) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 65 (type EXCL) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03 (obsolete)
lola: LAUNCH task # 122 (type EXCL) for 36 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-12
lola: time limit : 446 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 93 (type FNDP) for 33 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 94 (type EQUN) for 33 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 96 (type SRCH) for 33 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 55 (type FNDP) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03
lola: result : unknown
lola: fired transitions : 21356
lola: tried executions : 65
lola: time used : 10.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 122 (type EXCL) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-12
lola: result : true
lola: markings : 198
lola: fired transitions : 197
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 116 (type EXCL) for 30 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-10
lola: time limit : 510 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-94.sara.
lola: FINISHED task # 116 (type EXCL) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-10
lola: result : true
lola: markings : 148
lola: fired transitions : 147
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 110 (type EXCL) for 3 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-01
lola: time limit : 595 sec
lola: memory limit: 32 pages
lola: FINISHED task # 110 (type EXCL) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-01
lola: result : true
lola: markings : 26
lola: fired transitions : 25
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 91 (type EXCL) for 27 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09
lola: time limit : 714 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-01: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-02: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03: AG true state equation
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-04: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-05: INITIAL true preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-06: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-08: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-10: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-12: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09: EF 0 4 1 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11: EF 0 2 3 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
91 EF EXCL 1/714 1/32 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09 2576 m, 515 m/sec, 3729 t fired, .
93 EF FNDP 1/510 0/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11 5474 t fired, 39 attempts, .
94 EF STEQ 1/510 0/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11 sara is running.
96 EF SRCH 1/595 1/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11 4370 m, 874 m/sec, 9134 t fired, .

Time elapsed: 30 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic

FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-01: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-02: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03: AG true state equation
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-04: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-05: INITIAL true preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-06: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-08: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-10: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-12: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09: EF 0 4 1 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11: EF 0 2 3 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
91 EF EXCL 6/714 1/32 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09 12164 m, 1917 m/sec, 17633 t fired, .
93 EF FNDP 6/509 0/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11 41873 t fired, 273 attempts, .
94 EF STEQ 6/509 0/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11 sara is running.
96 EF SRCH 6/594 1/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11 17964 m, 2718 m/sec, 39674 t fired, .

Time elapsed: 35 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 94 (type EQUN) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11
lola: result : false
lola: CANCELED task # 93 (type FNDP) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 96 (type SRCH) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11 (obsolete)
lola: LAUNCH task # 74 (type FNDP) for 21 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 75 (type EQUN) for 21 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 77 (type SRCH) for 21 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 93 (type FNDP) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11
lola: result : unknown
lola: fired transitions : 43961
lola: tried executions : 287
lola: time used : 7.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-75.sara.
sara: place or transition ordering is non-deterministic

FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-01: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-02: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03: AG true state equation
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-04: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-05: INITIAL true preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-06: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-08: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-10: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11: EF false state equation
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-12: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07: EF 0 2 3 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09: EF 0 4 1 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
74 EF FNDP 4/594 0/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07 20693 t fired, 54 attempts, .
75 EF STEQ 4/712 0/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07 sara is running.
77 EF SRCH 4/712 1/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07 23218 m, 4643 m/sec, 64023 t fired, .
91 EF EXCL 11/892 1/32 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09 21199 m, 1807 m/sec, 30862 t fired, .

Time elapsed: 40 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 75 (type EQUN) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07
lola: result : false
lola: CANCELED task # 74 (type FNDP) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 77 (type SRCH) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07 (obsolete)
lola: LAUNCH task # 81 (type FNDP) for 42 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 82 (type EQUN) for 42 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 84 (type SRCH) for 42 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 74 (type FNDP) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07
lola: result : unknown
lola: fired transitions : 21002
lola: tried executions : 55
lola: time used : 5.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-82.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-01: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-02: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03: AG true state equation
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-04: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-05: INITIAL true preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-06: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07: EF false state equation
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-08: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-10: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11: EF false state equation
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-12: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09: EF 0 4 1 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14: AG 0 2 3 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
81 EF FNDP 4/889 0/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14 21661 t fired, 71 attempts, .
82 EF STEQ 4/889 0/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14 sara is running.
84 EF SRCH 4/889 1/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14 11680 m, 2336 m/sec, 22446 t fired, .
91 EF EXCL 16/1190 1/32 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09 30051 m, 1770 m/sec, 43948 t fired, .

Time elapsed: 45 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 82 (type EQUN) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14
lola: result : false
lola: CANCELED task # 81 (type FNDP) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14 (obsolete)
lola: CANCELED task # 84 (type SRCH) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14 (obsolete)
lola: LAUNCH task # 100 (type FNDP) for 45 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 101 (type EQUN) for 45 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 103 (type SRCH) for 45 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 81 (type FNDP) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14
lola: result : unknown
lola: fired transitions : 29650
lola: tried executions : 98
lola: time used : 6.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-101.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-01: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-02: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03: AG true state equation
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-04: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-05: INITIAL true preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-06: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07: EF false state equation
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-08: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-10: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11: EF false state equation
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-12: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13: AG false findpath
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14: AG true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09: EF 0 4 1 0 1 0 0 0
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15: AG 0 2 3 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
91 EF EXCL 21/1785 1/32 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09 38144 m, 1618 m/sec, 58384 t fired, .
100 EF FNDP 3/1184 0/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15 13625 t fired, 42 attempts, .
101 EF STEQ 3/1184 0/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15 sara is running.
103 EF SRCH 3/1776 1/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15 14567 m, 2913 m/sec, 28003 t fired, .

Time elapsed: 50 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 101 (type EQUN) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15
lola: result : false
lola: CANCELED task # 100 (type FNDP) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15 (obsolete)
lola: CANCELED task # 103 (type SRCH) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15 (obsolete)
lola: LAUNCH task # 87 (type FNDP) for 27 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 88 (type EQUN) for 27 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 90 (type SRCH) for 27 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 100 (type FNDP) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15
lola: result : unknown
lola: fired transitions : 18663
lola: tried executions : 58
lola: time used : 5.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-88.sara.
sara: place or transition ordering is non-deterministic

FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-01: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-02: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03: AG true state equation
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-04: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-05: INITIAL true preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-06: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07: EF false state equation
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-08: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-10: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11: EF false state equation
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-12: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13: AG false findpath
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14: AG true state equation
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15: AG true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09: EF 0 1 4 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 EF FNDP 3/1774 0/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09 24103 t fired, 276 attempts, .
88 EF STEQ 3/3548 0/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09 sara is running.
90 EF SRCH 3/3548 1/5 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09 27079 m, 5415 m/sec, 40359 t fired, .
91 EF EXCL 26/3571 1/32 BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09 46836 m, 1738 m/sec, 71267 t fired, .

Time elapsed: 55 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 88 (type EQUN) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09
lola: result : false
lola: CANCELED task # 87 (type FNDP) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 90 (type SRCH) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 91 (type EXCL) for BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09 (obsolete)
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-00: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-01: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-02: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-03: AG true state equation
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-04: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-05: INITIAL true preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-06: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-07: EF false state equation
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-08: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-09: EF false state equation
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-10: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-11: EF false state equation
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-12: EF true tandem / relaxed
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-13: AG false findpath
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-14: AG true state equation
BridgeAndVehicles-PT-V50P20N50-ReachabilityCardinality-15: AG true state equation


Time elapsed: 56 secs. Pages in use: 3

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-PT-V50P20N50"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is BridgeAndVehicles-PT-V50P20N50, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r023-tajo-162038139400246"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-PT-V50P20N50.tgz
mv BridgeAndVehicles-PT-V50P20N50 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;