Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/mnt/tpsp/fkordon/mcc2021-input.r023-tajo-162038139300174.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
.................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is BridgeAndVehicles-PT-V10P10N10, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r023-tajo-162038139300174
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.5M
-rw-r--r-- 1 mcc users 40K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 221K May 10 09:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 133K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 539K May 10 09:42 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.4K Mar 28 15:46 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Mar 28 15:46 LTLCardinality.xml
-rw-r--r-- 1 mcc users 16K Mar 28 15:46 LTLFireability.txt
-rw-r--r-- 1 mcc users 56K Mar 28 15:46 LTLFireability.xml
-rw-r--r-- 1 mcc users 6.7K Mar 23 02:48 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 26K Mar 23 02:48 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 19K Mar 22 11:00 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 61K Mar 22 11:00 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K Mar 22 09:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.3K Mar 22 09:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 10 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 311K May 5 16:51 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-00
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-01
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-02
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-03
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-04
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-05
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-06
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-07
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-08
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-09
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-10
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-11
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-12
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-13
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-14
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1620856809288

starting LoLA
BK_INPUT BridgeAndVehicles-PT-V10P10N10
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
ReachabilityCardinality

FORMULA BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1620856814524

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 22 (type CNST) for 21 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-07
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 22 (type CNST) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-07
lola: result : false
lola: LAUNCH INITIAL
lola: LAUNCH task # 19 (type CNST) for 18 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-06
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 19 (type CNST) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-06
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 53 (type EXCL) for 33 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-11
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 49 (type FNDP) for 33 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 50 (type EQUN) for 33 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 52 (type SRCH) for 33 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 49 (type FNDP) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-11
lola: result : true
lola: fired transitions : 18
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 50 (type EQUN) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 52 (type SRCH) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 53 (type EXCL) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-11 (obsolete)
lola: LAUNCH task # 79 (type EXCL) for 24 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-08
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 132 (type FNDP) for 42 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 133 (type EQUN) for 42 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 135 (type SRCH) for 42 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 50 (type EQUN) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-11
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-133.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 133 (type EQUN) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-14
lola: result : false
lola: CANCELED task # 132 (type FNDP) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-14 (obsolete)
lola: CANCELED task # 135 (type SRCH) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-14 (obsolete)
lola: LAUNCH task # 81 (type FNDP) for 3 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 82 (type EQUN) for 3 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 84 (type SRCH) for 3 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 132 (type FNDP) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-14
lola: result : unknown
lola: fired transitions : 14351
lola: tried executions : 173
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 81 (type FNDP) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-01
lola: result : true
lola: fired transitions : 26
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 84 (type SRCH) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-01
lola: result : true
lola: markings : 28
lola: fired transitions : 27
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 82 (type EQUN) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-01 (obsolete)
lola: LAUNCH task # 119 (type FNDP) for 39 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 120 (type EQUN) for 39 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 122 (type SRCH) for 39 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 122 (type SRCH) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-13
lola: result : true
lola: markings : 17
lola: fired transitions : 16
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 119 (type FNDP) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-13 (obsolete)
lola: CANCELED task # 120 (type EQUN) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-13 (obsolete)
lola: LAUNCH task # 113 (type FNDP) for 12 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 114 (type EQUN) for 12 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 116 (type SRCH) for 12 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-82.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 119 (type FNDP) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-13
lola: result : true
lola: fired transitions : 15
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-120.sara.
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-114.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic


lola: FINISHED task # 120 (type EQUN) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-13
lola: result : true
lola: FINISHED task # 114 (type EQUN) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-04
lola: result : false
lola: CANCELED task # 113 (type FNDP) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 116 (type SRCH) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-04 (obsolete)
lola: LAUNCH task # 99 (type FNDP) for 6 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 100 (type EQUN) for 6 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 102 (type SRCH) for 6 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 113 (type FNDP) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-04
lola: result : unknown
lola: fired transitions : 5008
lola: tried executions : 251
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-100.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 100 (type EQUN) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-02
lola: result : false
lola: CANCELED task # 99 (type FNDP) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-02 (obsolete)
lola: CANCELED task # 102 (type SRCH) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-02 (obsolete)
lola: LAUNCH task # 93 (type FNDP) for 15 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 94 (type EQUN) for 15 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 96 (type SRCH) for 15 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 99 (type FNDP) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-02
lola: result : unknown
lola: fired transitions : 11198
lola: tried executions : 168
lola: time used : 1.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-94.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 94 (type EQUN) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-05
lola: result : false
lola: CANCELED task # 93 (type FNDP) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 96 (type SRCH) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-05 (obsolete)
lola: LAUNCH task # 126 (type FNDP) for 45 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 127 (type EQUN) for 45 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 129 (type SRCH) for 45 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 93 (type FNDP) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-05
lola: result : unknown
lola: fired transitions : 8443
lola: tried executions : 99
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-127.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 127 (type EQUN) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-15
lola: result : false
lola: CANCELED task # 126 (type FNDP) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-15 (obsolete)
lola: CANCELED task # 129 (type SRCH) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-15 (obsolete)
lola: LAUNCH task # 106 (type FNDP) for 0 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 107 (type EQUN) for 0 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 109 (type SRCH) for 0 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 126 (type FNDP) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-15
lola: result : unknown
lola: fired transitions : 10654
lola: tried executions : 152
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 106 (type FNDP) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-00
lola: result : true
lola: fired transitions : 31
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 107 (type EQUN) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 109 (type SRCH) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-00 (obsolete)
lola: LAUNCH task # 87 (type FNDP) for 9 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 88 (type EQUN) for 9 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 90 (type SRCH) for 9 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-107.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-88.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
sara: warning, failure of lp_solve (at job 110)

lola: FINISHED task # 88 (type EQUN) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-03
lola: result : false
lola: CANCELED task # 87 (type FNDP) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 90 (type SRCH) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-03 (obsolete)
lola: LAUNCH task # 56 (type FNDP) for 36 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 57 (type EQUN) for 36 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 59 (type SRCH) for 36 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 87 (type FNDP) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-03
lola: result : unknown
lola: fired transitions : 8841
lola: tried executions : 389
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-57.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 57 (type EQUN) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-12
lola: result : false
lola: CANCELED task # 56 (type FNDP) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 59 (type SRCH) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-12 (obsolete)
lola: LAUNCH task # 63 (type FNDP) for 27 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 64 (type EQUN) for 27 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 66 (type FNDP) for 30 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 56 (type FNDP) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-12
lola: result : unknown
lola: fired transitions : 6905
lola: tried executions : 98
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-64.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 79 (type EXCL) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-08
lola: result : false
lola: markings : 54854
lola: fired transitions : 111745
lola: time used : 3.000000
lola: memory pages used : 1
lola: LAUNCH task # 72 (type EXCL) for 30 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-10
lola: time limit : 1798 sec
lola: memory limit: 32 pages
lola: FINISHED task # 72 (type EXCL) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-10
lola: result : false
lola: markings : 55154
lola: fired transitions : 112307
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 66 (type FNDP) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-10 (obsolete)
lola: LAUNCH task # 68 (type EXCL) for 27 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-09
lola: time limit : 3596 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 67 (type SRCH) for 27 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 66 (type FNDP) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-10
lola: result : unknown
lola: fired transitions : 249273
lola: tried executions : 7884
lola: time used : 3.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-00: AG false findpath
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-01: EF true findpath
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-02: EF false state equation
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-03: EF false state equation
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-04: AG true state equation
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-05: EF false state equation
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-06: INITIAL true preprocessing
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-07: INITIAL false preprocessing
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-08: EF false tandem / relaxed
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-10: EF false tandem / relaxed
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-11: AG false findpath
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-12: AG true state equation
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-13: EF true tandem / insertion
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-14: EF false state equation
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-15: AG true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-09: AG 0 1 4 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 EF FNDP 4/3596 0/5 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-09 279412 t fired, 5987 attempts, .
64 EF STEQ 4/3596 0/5 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-09 sara is running.
67 EF SRCH 1/1798 1/5 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-09 44132 m, 8826 m/sec, 106913 t fired, .
68 EF EXCL 1/3596 1/32 BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-09 19369 m, 3873 m/sec, 38170 t fired, .

Time elapsed: 5 secs. Pages in use: 4
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 67 (type SRCH) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-09
lola: result : false
lola: markings : 55535
lola: fired transitions : 135788
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 63 (type FNDP) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 64 (type EQUN) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 68 (type EXCL) for BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-09 (obsolete)
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-00: AG false findpath
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-01: EF true findpath
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-02: EF false state equation
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-03: EF false state equation
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-04: AG true state equation
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-05: EF false state equation
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-06: INITIAL true preprocessing
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-07: INITIAL false preprocessing
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-08: EF false tandem / relaxed
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-09: AG true tandem / insertion
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-10: EF false tandem / relaxed
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-11: AG false findpath
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-12: AG true state equation
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-13: EF true tandem / insertion
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-14: EF false state equation
BridgeAndVehicles-PT-V10P10N10-ReachabilityCardinality-15: AG true state equation


Time elapsed: 5 secs. Pages in use: 4

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-PT-V10P10N10"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is BridgeAndVehicles-PT-V10P10N10, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r023-tajo-162038139300174"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-PT-V10P10N10.tgz
mv BridgeAndVehicles-PT-V10P10N10 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;