About the Execution of LoLA for BridgeAndVehicles-COL-V80P20N50
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 6724.743 | 78798.00 | 269698.00 | 19.30 | TFTTFTFFTFTTFFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2021-input.r023-tajo-162038139200134.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is BridgeAndVehicles-COL-V80P20N50, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r023-tajo-162038139200134
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 436K
-rw-r--r-- 1 mcc users 20K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 147K May 10 09:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 9.6K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K May 10 09:42 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.3K Mar 28 15:47 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Mar 28 15:47 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Mar 28 15:47 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 28 15:47 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 23 02:57 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K Mar 23 02:56 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.7K Mar 22 11:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 19K Mar 22 11:53 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Mar 22 09:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Mar 22 09:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_pt
-rw-r--r-- 1 mcc users 10 May 5 16:51 instance
-rw-r--r-- 1 mcc users 5 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 47K May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00
FORMULA_NAME BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01
FORMULA_NAME BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02
FORMULA_NAME BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03
FORMULA_NAME BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04
FORMULA_NAME BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-05
FORMULA_NAME BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06
FORMULA_NAME BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07
FORMULA_NAME BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08
FORMULA_NAME BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-09
FORMULA_NAME BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10
FORMULA_NAME BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11
FORMULA_NAME BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12
FORMULA_NAME BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-13
FORMULA_NAME BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14
FORMULA_NAME BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1620854674826
starting LoLA
BK_INPUT BridgeAndVehicles-COL-V80P20N50
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620854753624
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading HL formula in XML format (--xmlformula)
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 57 (type SKEL/FNDP) for 6 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: TR BINDINGS
lola: LAUNCH task # 58 (type SKEL/EQUN) for 6 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 60 (type SKEL/SRCH) for 6 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 61 (type SKEL/SRCH) for 6 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH INITIAL
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 41 (type SKEL/CNST) for 39 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-13
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: TR BINDINGS DONE
lola: Places: 228, Transitions: 8588
lola: FINISHED task # 41 (type SKEL/CNST) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-13
lola: result : false
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH INITIAL
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 17 (type SKEL/CNST) for 15 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-05
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 60 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 61 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02
lola: result : false
lola: markings : 19843
lola: fired transitions : 32803
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: CANCELED task # 57 (type FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02 (obsolete)
lola: CANCELED task # 58 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-58.sara.
lola: @ trans enregistrement_A
lola: @ trans decision
lola: @ trans altern_cpt
lola: LAUNCH task # 74 (type SKEL/FNDP) for 24 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 89 (type SKEL/EQUN) for 24 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 91 (type SKEL/SRCH) for 24 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: @ trans autorisation_A
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: @ trans liberation_A
lola: @ trans enregistrement_B
lola: FINISHED task # 17 (type SKEL/CNST) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-05
lola: result : true
lola: @ trans timeout_A
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 57 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02
lola: result : unknown
lola: fired transitions : 86014
lola: tried executions : 86015
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 74 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08
lola: result : true
lola: fired transitions : 82
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: CANCELED task # 89 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 91 (type SRCH) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08 (obsolete)
lola: LAUNCH task # 72 (type SKEL/FNDP) for 30 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 87 (type SKEL/EQUN) for 30 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 122 (type SKEL/SRCH) for 30 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 123 (type SKEL/SRCH) for 30 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 29 (type SKEL/CNST) for 27 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-09
lola: time limit : 0 sec
lola: memory limit: 0 pages
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 91 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08
lola: result : true
lola: markings : 84
lola: fired transitions : 83
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 122 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10
lola: result : true
lola: markings : 79
lola: fired transitions : 78
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 72 (type FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 87 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 123 (type SRCH) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10 (obsolete)
lola: LAUNCH task # 76 (type SKEL/FNDP) for 42 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-89.sara.
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-87.sara.
lola: LAUNCH task # 108 (type SKEL/FNDP) for 3 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: @ trans timeout_B
lola: LAUNCH task # 109 (type SKEL/EQUN) for 3 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-109.sara.
lola: FINISHED task # 29 (type SKEL/CNST) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-09
lola: result : false
lola: LAUNCH task # 77 (type SKEL/FNDP) for 18 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 108 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01
lola: result : true
lola: fired transitions : 79
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 109 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01 (obsolete)
lola: LAUNCH task # 88 (type SKEL/FNDP) for 33 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 125 (type SKEL/EQUN) for 33 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 72 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10
lola: result : true
lola: fired transitions : 77
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 109 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01
lola: result : unknown
lola: FINISHED task # 87 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10
lola: result : true
lola: FINISHED task # 77 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06
lola: result : true
lola: fired transitions : 79
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 89 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08
lola: result : true
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-125.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 58 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02
lola: result : false
lola: FINISHED task # 76 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14
lola: result : true
lola: fired transitions : 80
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 139 (type SKEL/FNDP) for 12 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 140 (type SKEL/EQUN) for 12 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 88 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11
lola: result : true
lola: fired transitions : 81
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 125 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11 (obsolete)
lola: LAUNCH task # 81 (type SKEL/FNDP) for 21 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 82 (type SKEL/EQUN) for 21 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-140.sara.
lola: FINISHED task # 125 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 81 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07
lola: result : true
lola: fired transitions : 78
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 82 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-82.sara.
sara: place or transition ordering is non-deterministic
lola: LAUNCH task # 49 (type SKEL/FNDP) for 0 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 50 (type SKEL/EQUN) for 0 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 140 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04
lola: result : true
lola: CANCELED task # 139 (type FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04 (obsolete)
lola: LAUNCH task # 75 (type SKEL/FNDP) for 45 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 94 (type SKEL/EQUN) for 45 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 139 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04
lola: result : unknown
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-94.sara.
sara: place or transition ordering is non-deterministic
rewrite Frontend/Parser/formula_rewrite.k:711
lola: @ trans liberation_B
lola: @ trans basculement
lola: @ trans autorisation_B
lola: FINISHED task # 75 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15
lola: result : true
lola: fired transitions : 56
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 94 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15 (obsolete)
lola: LAUNCH task # 115 (type SKEL/FNDP) for 9 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 116 (type SKEL/EQUN) for 9 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 49 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00
lola: result : true
lola: fired transitions : 79
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-50.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 82 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: result : true
lola: CANCELED task # 50 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00 (obsolete)
lola: LAUNCH task # 102 (type SKEL/FNDP) for 36 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 103 (type SKEL/EQUN) for 36 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 94 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15
lola: result : true
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-116.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-103.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 50 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00
lola: result : true
lola: FINISHED task # 115 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03
lola: result : true
lola: fired transitions : 18
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 116 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03 (obsolete)
lola: LAUNCH task # 105 (type SKEL/SRCH) for 36 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 106 (type SKEL/SRCH) for 36 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 116 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03
lola: result : true
lola: FINISHED task # 106 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12
lola: result : false
lola: markings : 19843
lola: fired transitions : 32804
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 102 (type FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 103 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 105 (type SRCH) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12 (obsolete)
lola: FINISHED task # 102 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12
lola: result : unknown
lola: fired transitions : 6796
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 103 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12
lola: result : false
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: Rule S: 0 transitions removed,0 places removed
lola: planning for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12 stopped (result already fixed).
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-05: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-09: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 4
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-05: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-09: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15: EF 0 0 0 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-05: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-09: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 4
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-05: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-09: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15: EF 0 0 0 0 2 0 0 3
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-05: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-09: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15: EF 0 0 0 0 2 0 0 3
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BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-05: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-09: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15: EF 0 0 0 0 2 0 0 3
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lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 149 (type EXCL) for 30 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10
lola: time limit : 324 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 145 (type FNDP) for 30 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 146 (type EQUN) for 30 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 148 (type SRCH) for 30 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-146.sara.
lola: FINISHED task # 148 (type SRCH) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10
lola: result : true
lola: markings : 79
lola: fired transitions : 78
lola: time used : 3.000000
lola: memory pages used : 1
lola: CANCELED task # 145 (type FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 146 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 149 (type EXCL) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10 (obsolete)
lola: FINISHED task # 146 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10
lola: result : unknown
lola: FINISHED task # 145 (type FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10
lola: result : unknown
lola: fired transitions : 52
lola: tried executions : 2
lola: time used : 3.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-05: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-09: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10: EF true tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15: EF 0 0 0 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 155 (type EXCL) for 24 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08
lola: time limit : 356 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 151 (type FNDP) for 24 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 152 (type EQUN) for 24 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 154 (type SRCH) for 24 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-152.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-05: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-09: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10: EF true tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08: EF 0 1 4 0 3 0 0 2
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15: EF 0 0 0 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
151 EF FNDP 2/1780 0/5 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08 --
152 EF STEQ 2/3561 0/5 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08 sara is running.
154 EF SRCH 2/3561 1/5 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08 --
155 EF EXCL 2/356 1/32 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08 7 m, 1 m/sec, 6 t fired, .
Time elapsed: 41 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 151 (type FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08
lola: result : true
lola: fired transitions : 85
lola: tried executions : 1
lola: time used : 3.000000
lola: memory pages used : 0
lola: CANCELED task # 152 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 154 (type SRCH) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 155 (type EXCL) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08 (obsolete)
lola: FINISHED task # 152 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 162 (type EXCL) for 12 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04
lola: time limit : 395 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 158 (type FNDP) for 12 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 159 (type EQUN) for 12 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 161 (type SRCH) for 12 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 161 (type SRCH) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04
lola: result : true
lola: markings : 61
lola: fired transitions : 60
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 158 (type FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 159 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 162 (type EXCL) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04 (obsolete)
lola: FINISHED task # 158 (type FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04
lola: result : unknown
lola: fired transitions : 48
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 169 (type EXCL) for 18 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06
lola: time limit : 444 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 165 (type FNDP) for 18 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 166 (type EQUN) for 18 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 168 (type SRCH) for 18 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-159.sara.
lola: FINISHED task # 165 (type FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06
lola: result : true
lola: fired transitions : 79
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: CANCELED task # 166 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06 (obsolete)
lola: CANCELED task # 168 (type SRCH) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06 (obsolete)
lola: CANCELED task # 169 (type EXCL) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-166.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 175 (type EXCL) for 0 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00
lola: time limit : 507 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 171 (type FNDP) for 0 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 172 (type EQUN) for 0 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 174 (type SRCH) for 0 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04: AG false tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-05: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06: AG false findpath
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08: EF true findpath
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-09: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10: EF true tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00: EF 0 1 4 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15: EF 0 0 0 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
171 EF FNDP 0/1777 0/5 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00 --
172 EF STEQ 0/3554 0/5 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00 sara not yet started (preprocessing).
174 EF SRCH 0/3554 1/5 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00 --
175 EF EXCL 0/507 1/32 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00 --
Time elapsed: 46 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 174 (type SRCH) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00
lola: result : true
lola: markings : 81
lola: fired transitions : 80
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 171 (type FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 172 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 175 (type EXCL) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00 (obsolete)
lola: FINISHED task # 171 (type FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00
lola: result : unknown
lola: fired transitions : 75
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 181 (type EXCL) for 45 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15
lola: time limit : 592 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 177 (type FNDP) for 45 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 178 (type EQUN) for 45 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 180 (type SRCH) for 45 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-172.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-178.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00: EF true tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04: AG false tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-05: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06: AG false findpath
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08: EF true findpath
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-09: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10: EF true tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15: EF 0 1 4 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
177 EF FNDP 6/1777 0/5 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15 --
178 EF STEQ 6/3554 0/5 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15 sara is running.
180 EF SRCH 6/3554 1/5 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15 --
181 EF EXCL 6/592 1/32 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15 --
Time elapsed: 52 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00: EF true tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04: AG false tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-05: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06: AG false findpath
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08: EF true findpath
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-09: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10: EF true tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15: EF 0 1 4 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
177 EF FNDP 11/1771 0/5 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15 --
178 EF STEQ 11/3548 0/5 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15 sara is running.
180 EF SRCH 11/3548 1/5 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15 --
181 EF EXCL 11/592 1/32 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15 --
Time elapsed: 57 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 180 (type SRCH) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15
lola: result : true
lola: markings : 58
lola: fired transitions : 57
lola: time used : 13.000000
lola: memory pages used : 1
lola: CANCELED task # 177 (type FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15 (obsolete)
lola: CANCELED task # 178 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15 (obsolete)
lola: CANCELED task # 181 (type EXCL) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15 (obsolete)
lola: FINISHED task # 178 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15
lola: result : unknown
lola: FINISHED task # 177 (type FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15
lola: result : true
lola: fired transitions : 56
lola: tried executions : 1
lola: time used : 13.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 188 (type EXCL) for 3 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01
lola: time limit : 708 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 184 (type FNDP) for 3 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 185 (type EQUN) for 3 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 187 (type SRCH) for 3 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 187 (type SRCH) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01
lola: result : true
lola: markings : 81
lola: fired transitions : 80
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 184 (type FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 185 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 188 (type EXCL) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01 (obsolete)
lola: FINISHED task # 184 (type FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01
lola: result : unknown
lola: fired transitions : 26
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-185.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 195 (type EXCL) for 42 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14
lola: time limit : 884 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 191 (type FNDP) for 42 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 192 (type EQUN) for 42 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 194 (type SRCH) for 42 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 194 (type SRCH) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14
lola: result : true
lola: markings : 236
lola: fired transitions : 235
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 191 (type FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14 (obsolete)
lola: CANCELED task # 192 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14 (obsolete)
lola: CANCELED task # 195 (type EXCL) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14 (obsolete)
lola: FINISHED task # 191 (type FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14
lola: result : unknown
lola: fired transitions : 120
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00: EF true tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01: AG false tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04: AG false tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-05: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06: AG false findpath
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08: EF true findpath
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-09: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10: EF true tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-13: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14: AG false tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15: EF true tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03: EF 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07: AG 0 0 0 0 2 0 0 3
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11: EF 0 0 0 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 62 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 201 (type EXCL) for 9 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03
lola: time limit : 1179 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 197 (type FNDP) for 9 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 198 (type EQUN) for 9 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 200 (type SRCH) for 9 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-192.sara.
lola: FINISHED task # 201 (type EXCL) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03
lola: result : true
lola: markings : 61
lola: fired transitions : 60
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 197 (type FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 198 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 200 (type SRCH) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03 (obsolete)
lola: FINISHED task # 197 (type FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03
lola: result : true
lola: fired transitions : 56
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-198.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 208 (type EXCL) for 21 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07
lola: time limit : 1768 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 204 (type FNDP) for 21 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 205 (type EQUN) for 21 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 207 (type SRCH) for 21 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 204 (type FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07
lola: result : true
lola: fired transitions : 78
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 205 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 207 (type SRCH) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 208 (type EXCL) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07 (obsolete)
lola: LAUNCH task # 214 (type EXCL) for 33 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11
lola: time limit : 3536 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 210 (type FNDP) for 33 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 211 (type EQUN) for 33 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 213 (type SRCH) for 33 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00: EF true tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01: AG false tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03: EF true tandem / relaxed
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04: AG false tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-05: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06: AG false findpath
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07: AG false findpath
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08: EF true findpath
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-09: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10: EF true tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-13: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14: AG false tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15: EF true tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11: EF 0 1 4 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
210 EF FNDP 3/1768 0/5 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11 --
211 EF STEQ 3/3536 0/5 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11 sara not yet started (preprocessing).
213 EF SRCH 3/3536 1/5 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11 --
214 EF EXCL 3/3536 1/32 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11 --
Time elapsed: 67 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00: EF true tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01: AG false tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03: EF true tandem / relaxed
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04: AG false tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-05: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06: AG false findpath
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07: AG false findpath
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08: EF true findpath
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-09: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10: EF true tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-13: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14: AG false tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15: EF true tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11: EF 0 1 4 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
210 EF FNDP 8/1765 0/5 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11 --
211 EF STEQ 8/3533 0/5 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11 sara not yet started (preprocessing).
213 EF SRCH 8/3533 1/5 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11 --
214 EF EXCL 8/3536 1/32 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11 --
Time elapsed: 72 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00: EF true tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01: AG false tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03: EF true tandem / relaxed
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04: AG false tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-05: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06: AG false findpath
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07: AG false findpath
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08: EF true findpath
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-09: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10: EF true tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-13: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14: AG false tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15: EF true tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11: EF 0 1 4 0 2 0 0 3
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
210 EF FNDP 13/1760 0/5 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11 --
211 EF STEQ 13/3528 0/5 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11 sara not yet started (preprocessing).
213 EF SRCH 13/3528 1/5 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11 --
214 EF EXCL 13/3536 1/32 BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11 --
Time elapsed: 77 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 166 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06
lola: result : true
lola: FINISHED task # 172 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00
lola: result : true
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-205.sara.
lola: FINISHED task # 210 (type FNDP) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11
lola: result : true
lola: fired transitions : 81
lola: tried executions : 1
lola: time used : 15.000000
lola: memory pages used : 0
lola: CANCELED task # 211 (type EQUN) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 213 (type SRCH) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 214 (type EXCL) for BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11 (obsolete)
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-00: EF true tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-01: AG false tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-02: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-03: EF true tandem / relaxed
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-04: AG false tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-05: INITIAL true skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-06: AG false findpath
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-07: AG false findpath
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-08: EF true findpath
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-09: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-10: EF true tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-11: EF true findpath
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-12: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-13: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-14: AG false tandem / insertion
BridgeAndVehicles-COL-V80P20N50-ReachabilityCardinality-15: EF true tandem / insertion
Time elapsed: 79 secs. Pages in use: 2
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-COL-V80P20N50"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is BridgeAndVehicles-COL-V80P20N50, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r023-tajo-162038139200134"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-COL-V80P20N50.tgz
mv BridgeAndVehicles-COL-V80P20N50 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;