About the Execution of LoLA for BridgeAndVehicles-COL-V10P10N10
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
701.147 | 6946.00 | 25006.00 | 5.20 | FTFFTFTFFFTFFTFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2021-input.r023-tajo-162038139000014.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
.......................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is BridgeAndVehicles-COL-V10P10N10, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r023-tajo-162038139000014
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 444K
-rw-r--r-- 1 mcc users 20K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 144K May 10 09:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 15K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 85K May 10 09:42 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Mar 28 15:46 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Mar 28 15:46 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Mar 28 15:46 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Mar 28 15:46 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K Mar 23 02:48 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K Mar 23 02:48 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.7K Mar 22 11:00 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 19K Mar 22 11:00 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Mar 22 09:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Mar 22 09:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_pt
-rw-r--r-- 1 mcc users 10 May 5 16:51 instance
-rw-r--r-- 1 mcc users 5 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 38K May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-00
FORMULA_NAME BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-01
FORMULA_NAME BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-02
FORMULA_NAME BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-03
FORMULA_NAME BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-04
FORMULA_NAME BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-05
FORMULA_NAME BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-06
FORMULA_NAME BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-07
FORMULA_NAME BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-08
FORMULA_NAME BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-09
FORMULA_NAME BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-10
FORMULA_NAME BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-11
FORMULA_NAME BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-12
FORMULA_NAME BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-13
FORMULA_NAME BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-14
FORMULA_NAME BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1620853013222
starting LoLA
BK_INPUT BridgeAndVehicles-COL-V10P10N10
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620853020168
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading HL formula in XML format (--xmlformula)
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 50 (type SKEL/FNDP) for 30 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: TR BINDINGS
lola: LAUNCH task # 51 (type SKEL/EQUN) for 30 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 53 (type SKEL/SRCH) for 30 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type SKEL/SRCH) for 30 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: TR BINDINGS DONE
lola: Places: 48, Transitions: 288
lola: FINISHED task # 53 (type SKEL/SRCH) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-10
lola: result : false
lola: markings : 1323
lola: fired transitions : 2803
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 50 (type FNDP) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 51 (type EQUN) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 54 (type SRCH) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-10 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 64 (type SKEL/FNDP) for 0 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 65 (type SKEL/EQUN) for 0 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 67 (type SKEL/SRCH) for 0 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 68 (type SKEL/SRCH) for 0 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 50 (type SKEL/FNDP) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-10
lola: result : unknown
lola: fired transitions : 23644
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 64 (type SKEL/FNDP) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-00
lola: result : true
lola: fired transitions : 30
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: CANCELED task # 65 (type EQUN) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 67 (type SRCH) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 68 (type SRCH) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-00 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 70 (type SKEL/FNDP) for 3 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 71 (type SKEL/FNDP) for 6 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 84 (type SKEL/EQUN) for 3 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 86 (type SKEL/SRCH) for 3 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-51.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 70 (type SKEL/FNDP) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-01
lola: result : true
lola: fired transitions : 63
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 84 (type EQUN) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 86 (type SRCH) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-01 (obsolete)
lola: LAUNCH task # 121 (type SKEL/FNDP) for 42 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 128 (type SKEL/EQUN) for 42 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 130 (type SKEL/SRCH) for 42 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 86 (type SKEL/SRCH) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-01
lola: result : true
lola: markings : 51
lola: fired transitions : 58
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-65.sara.
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-84.sara.
lola: FINISHED task # 130 (type SKEL/SRCH) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-14
lola: result : true
lola: markings : 13
lola: fired transitions : 12
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 121 (type SKEL/FNDP) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-14
lola: result : true
lola: fired transitions : 11
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 128 (type EQUN) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-14 (obsolete)
lola: LAUNCH task # 90 (type SKEL/FNDP) for 27 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 91 (type SKEL/EQUN) for 27 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 93 (type SKEL/SRCH) for 27 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 128 (type SKEL/EQUN) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-14
lola: result : unknown
lola: FINISHED task # 65 (type SKEL/EQUN) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-00
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 51 (type SKEL/EQUN) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-10
lola: result : false
lola: FINISHED task # 84 (type SKEL/EQUN) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-01
lola: result : true
lola: @ trans enregistrement_A
lola: @ trans decision
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-91.sara.
lola: @ trans altern_cpt
lola: @ trans autorisation_A
lola: @ trans liberation_A
lola: FINISHED task # 93 (type SKEL/SRCH) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-09
lola: result : false
lola: markings : 13773
lola: fired transitions : 32008
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 90 (type FNDP) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 91 (type EQUN) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-09 (obsolete)
lola: LAUNCH task # 108 (type SKEL/FNDP) for 9 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 114 (type SKEL/FNDP) for 33 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 117 (type SKEL/EQUN) for 9 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 90 (type SKEL/FNDP) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-09
lola: result : unknown
lola: fired transitions : 5950
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: @ trans enregistrement_B
lola: @ trans timeout_A
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: @ trans timeout_B
lola: @ trans liberation_B
lola: @ trans basculement
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-117.sara.
sara: place or transition ordering is non-deterministic
lola: @ trans autorisation_B
lola: FINISHED task # 91 (type SKEL/EQUN) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-09
lola: result : false
lola: FINISHED task # 117 (type SKEL/EQUN) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-03
lola: result : false
lola: CANCELED task # 108 (type FNDP) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-03 (obsolete)
lola: LAUNCH task # 72 (type SKEL/FNDP) for 12 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 101 (type SKEL/EQUN) for 12 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 108 (type SKEL/FNDP) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-03
lola: result : unknown
lola: fired transitions : 7174
lola: tried executions : 110
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-101.sara.
sara: place or transition ordering is non-deterministic
lola: Rule S: 0 transitions removed,0 places removed
lola: planning for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-09 stopped (result already fixed).
lola: FINISHED task # 101 (type SKEL/EQUN) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-04
lola: result : false
lola: planning for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-03 stopped (result already fixed).
lola: LAUNCH INITIAL
lola: LAUNCH task # 19 (type CNST) for 18 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-06
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 22 (type CNST) for 21 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-07
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: planning for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-10 stopped (result already fixed).
lola: CANCELED task # 72 (type FNDP) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-04 (obsolete)
lola: FINISHED task # 19 (type CNST) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-06
lola: result : true
lola: LAUNCH task # 110 (type SKEL/FNDP) for 39 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 22 (type CNST) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-07
lola: result : false
lola: LAUNCH task # 112 (type SKEL/FNDP) for 36 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 72 (type SKEL/FNDP) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-04
lola: result : unknown
lola: fired transitions : 10214
lola: tried executions : 807
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: planning for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-04 stopped (result already fixed).
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 110 (type SKEL/FNDP) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-13
lola: result : true
lola: fired transitions : 61
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 229 (type EXCL) for 24 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-08
lola: time limit : 360 sec
lola: memory limit: 32 pages
lola: FINISHED task # 229 (type EXCL) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-08
lola: result : true
lola: markings : 29
lola: fired transitions : 28
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 184 (type EXCL) for 45 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-15
lola: time limit : 400 sec
lola: memory limit: 32 pages
lola: FINISHED task # 184 (type EXCL) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-15
lola: result : false
lola: markings : 69516
lola: fired transitions : 93624
lola: time used : 3.000000
lola: memory pages used : 1
lola: LAUNCH task # 177 (type EXCL) for 36 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-12
lola: time limit : 449 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-03: EF false skeleton: state equation
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-04: AG true skeleton: state equation
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-06: AG true preprocessing
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-07: EF false preprocessing
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-08: AG false tandem / relaxed
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-09: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-10: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-15: AG true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-00: AG 0 5 0 0 2 0 0 3
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-01: EF 0 5 0 0 3 0 0 2
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-02: EF 0 9 1 0 0 0 0 0
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-05: EF 0 10 0 0 0 0 0 0
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-11: EF 0 9 1 0 0 0 0 0
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-12: EF 0 8 2 0 0 0 0 0
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 4
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-14: AG 0 5 0 0 3 0 0 2
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 EF FNDP 5/197 0/5 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-02 1777654 t fired, 2 attempts, .
112 EF FNDP 5/208 0/5 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-12 3670650 t fired, 4 attempts, .
114 EF FNDP 5/208 0/5 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-11 1774112 t fired, 43276 attempts, .
177 EF EXCL 2/449 1/32 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-12 54258 m, 10851 m/sec, 72998 t fired, .
Time elapsed: 5 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 177 (type EXCL) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-12
lola: result : false
lola: markings : 69516
lola: fired transitions : 93624
lola: time used : 3.000000
lola: memory pages used : 1
lola: CANCELED task # 112 (type FNDP) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-12 (obsolete)
lola: LAUNCH task # 209 (type EXCL) for 0 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-00
lola: time limit : 513 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 105 (type SKEL/FNDP) for 15 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 112 (type SKEL/FNDP) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-12
lola: result : unknown
lola: fired transitions : 4117702
lola: tried executions : 6
lola: time used : 6.000000
lola: memory pages used : 0
lola: FINISHED task # 209 (type EXCL) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-00
lola: result : true
lola: markings : 32
lola: fired transitions : 31
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 196 (type EXCL) for 33 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-11
lola: time limit : 599 sec
lola: memory limit: 32 pages
lola: FINISHED task # 196 (type EXCL) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-11
lola: result : false
lola: markings : 71074
lola: fired transitions : 101963
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 114 (type FNDP) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-11 (obsolete)
lola: LAUNCH task # 216 (type EXCL) for 42 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-14
lola: time limit : 718 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 218 (type FNDP) for 3 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 114 (type SKEL/FNDP) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-11
lola: result : unknown
lola: fired transitions : 2494148
lola: tried executions : 60875
lola: time used : 7.000000
lola: memory pages used : 0
lola: FINISHED task # 216 (type EXCL) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-14
lola: result : true
lola: markings : 238
lola: fired transitions : 290
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 202 (type EXCL) for 15 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-05
lola: time limit : 898 sec
lola: memory limit: 32 pages
lola: FINISHED task # 218 (type FNDP) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-01
lola: result : true
lola: fired transitions : 26
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 167 (type FNDP) for 39 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 167 (type FNDP) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-13
lola: result : true
lola: fired transitions : 30
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 96 (type SKEL/EQUN) for 6 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-96.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 96 (type SKEL/EQUN) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-02
lola: result : false
lola: CANCELED task # 71 (type FNDP) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-02 (obsolete)
lola: LAUNCH task # 118 (type SKEL/EQUN) for 15 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 146 (type SKEL/SRCH) for 15 BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 71 (type SKEL/FNDP) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-02
lola: result : unknown
lola: fired transitions : 2391279
lola: tried executions : 4
lola: time used : 7.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-118.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 118 (type SKEL/EQUN) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-05
lola: result : false
lola: CANCELED task # 105 (type FNDP) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 146 (type SRCH) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 202 (type EXCL) for BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-05 (obsolete)
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-00: AG false tandem / relaxed
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-01: EF true findpath
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-02: EF false skeleton: state equation
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-03: EF false skeleton: state equation
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-04: AG true skeleton: state equation
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-05: EF false skeleton: state equation
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-06: AG true preprocessing
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-07: EF false preprocessing
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-08: AG false tandem / relaxed
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-09: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-10: AG true skeleton: tandem / insertion
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-11: EF false tandem / relaxed
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-12: EF false tandem / relaxed
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-13: EF true findpath
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-14: AG false tandem / relaxed
BridgeAndVehicles-COL-V10P10N10-ReachabilityCardinality-15: AG true tandem / relaxed
Time elapsed: 7 secs. Pages in use: 2
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-COL-V10P10N10"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is BridgeAndVehicles-COL-V10P10N10, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r023-tajo-162038139000014"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-COL-V10P10N10.tgz
mv BridgeAndVehicles-COL-V10P10N10 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;