fond
Model Checking Contest 2021
11th edition, Paris, France, June 23, 2021
Execution of r004-tall-162037986200572
Last Updated
Jun 28, 2021

About the Execution of LoLA for BART-COL-040

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16246.884 1716331.00 1722320.00 4964.00 F?FTT?F?TF???FF? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.r004-tall-162037986200572.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is BART-COL-040, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r004-tall-162037986200572
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 532K
-rw-r--r-- 1 mcc users 12K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 98K May 10 09:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 9.0K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 67K May 10 09:42 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Mar 28 15:45 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Mar 28 15:45 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Mar 28 15:46 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Mar 28 15:46 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.1K Mar 23 02:28 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 20K Mar 23 02:28 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Mar 22 10:46 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 14K Mar 22 10:46 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 22 09:09 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Mar 22 09:09 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_pt
-rw-r--r-- 1 mcc users 4 May 5 16:51 instance
-rw-r--r-- 1 mcc users 5 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 207K May 5 16:51 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BART-COL-040-CTLFireability-00
FORMULA_NAME BART-COL-040-CTLFireability-01
FORMULA_NAME BART-COL-040-CTLFireability-02
FORMULA_NAME BART-COL-040-CTLFireability-03
FORMULA_NAME BART-COL-040-CTLFireability-04
FORMULA_NAME BART-COL-040-CTLFireability-05
FORMULA_NAME BART-COL-040-CTLFireability-06
FORMULA_NAME BART-COL-040-CTLFireability-07
FORMULA_NAME BART-COL-040-CTLFireability-08
FORMULA_NAME BART-COL-040-CTLFireability-09
FORMULA_NAME BART-COL-040-CTLFireability-10
FORMULA_NAME BART-COL-040-CTLFireability-11
FORMULA_NAME BART-COL-040-CTLFireability-12
FORMULA_NAME BART-COL-040-CTLFireability-13
FORMULA_NAME BART-COL-040-CTLFireability-14
FORMULA_NAME BART-COL-040-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1620732618137

starting LoLA
BK_INPUT BART-COL-040
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability

FORMULA BART-COL-040-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BART-COL-040-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BART-COL-040-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BART-COL-040-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BART-COL-040-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BART-COL-040-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BART-COL-040-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BART-COL-040-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BART-COL-040-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1620734334468

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading HL formula in XML format (--xmlformula)
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:199
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:202
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:199
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:135
lola: rewrite Frontend/Parser/formula_rewrite.k:122
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:182
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:135
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:122
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:227
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
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lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
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lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
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lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 54 (type SKEL/FNDP) for 36 BART-COL-040-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 55 (type SKEL/EQUN) for 36 BART-COL-040-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 56 (type SKEL/SRCH) for 36 BART-COL-040-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: TR BINDINGS
lola: LAUNCH task # 57 (type SKEL/SRCH) for 36 BART-COL-040-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 56 (type SKEL/SRCH) for BART-COL-040-CTLFireability-12
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH INITIAL
lola: LAUNCH task # 2 (type SKEL/CNST) for 0 BART-COL-040-CTLFireability-00
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 8 (type SKEL/CNST) for 6 BART-COL-040-CTLFireability-02
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 11 (type SKEL/CNST) for 9 BART-COL-040-CTLFireability-03
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 14 (type SKEL/CNST) for 12 BART-COL-040-CTLFireability-04
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 20 (type SKEL/CNST) for 18 BART-COL-040-CTLFireability-06
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
sara: try reading problem file /home/mcc/execution/CTLFireability-55.sara.
lola: LAUNCH task # 26 (type SKEL/CNST) for 24 BART-COL-040-CTLFireability-08
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 29 (type SKEL/CNST) for 27 BART-COL-040-CTLFireability-09
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
sara: place or transition ordering is non-deterministic
lola: LAUNCH task # 45 (type SKEL/CNST) for 43 BART-COL-040-CTLFireability-13
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 48 (type SKEL/CNST) for 46 BART-COL-040-CTLFireability-14
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: CANCELED task # 54 (type FNDP) for BART-COL-040-CTLFireability-12 (obsolete)
lola: CANCELED task # 55 (type EQUN) for BART-COL-040-CTLFireability-12 (obsolete)
lola: CANCELED task # 57 (type SRCH) for BART-COL-040-CTLFireability-12 (obsolete)
lola: FINISHED task # 54 (type SKEL/FNDP) for BART-COL-040-CTLFireability-12
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 57 (type SKEL/SRCH) for BART-COL-040-CTLFireability-12
lola: result : unknown
lola: markings : 1

lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 2 (type SKEL/CNST) for BART-COL-040-CTLFireability-00
lola: result : false
lola: FINISHED task # 26 (type SKEL/CNST) for BART-COL-040-CTLFireability-08
lola: result : true
lola: FINISHED task # 14 (type SKEL/CNST) for BART-COL-040-CTLFireability-04
lola: result : true
lola: FINISHED task # 8 (type SKEL/CNST) for BART-COL-040-CTLFireability-02
lola: result : false
lola: FINISHED task # 29 (type SKEL/CNST) for BART-COL-040-CTLFireability-09
lola: result : false
lola: FINISHED task # 45 (type SKEL/CNST) for BART-COL-040-CTLFireability-13
lola: result : false
lola: FINISHED task # 48 (type SKEL/CNST) for BART-COL-040-CTLFireability-14
lola: result : false
lola: FINISHED task # 11 (type SKEL/CNST) for BART-COL-040-CTLFireability-03
lola: result : true
lola: FINISHED task # 20 (type SKEL/CNST) for BART-COL-040-CTLFireability-06
lola: result : false
lola: FINISHED task # 55 (type SKEL/EQUN) for BART-COL-040-CTLFireability-12
lola: result : true
lola: TR BINDINGS DONE
lola: Places: 20213, Transitions: 12920
lola: @ trans TooEarly
lola: @ trans MissStation
lola: @ trans TrainStop
lola: @ trans TrainStable
lola: @ trans TrainDecc
lola: @ trans TrainAcc
lola: @ trans AtStation
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
BART-COL-040-CTLFireability-02: INITIAL false skeleton: preprocessing
BART-COL-040-CTLFireability-03: INITIAL true skeleton: preprocessing
BART-COL-040-CTLFireability-04: INITIAL true skeleton: preprocessing
BART-COL-040-CTLFireability-06: INITIAL false skeleton: preprocessing
BART-COL-040-CTLFireability-08: INITIAL true skeleton: preprocessing
BART-COL-040-CTLFireability-09: INITIAL false skeleton: preprocessing
BART-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
BART-COL-040-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-COL-040-CTLFireability-01: AG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-07: LTL/CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
BART-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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# running tasks: 0 of 4 Visible: 16
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BART-COL-040-CTLFireability-02: INITIAL false skeleton: preprocessing
BART-COL-040-CTLFireability-03: INITIAL true skeleton: preprocessing
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BART-COL-040-CTLFireability-06: INITIAL false skeleton: preprocessing
BART-COL-040-CTLFireability-08: INITIAL true skeleton: preprocessing
BART-COL-040-CTLFireability-09: INITIAL false skeleton: preprocessing
BART-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
BART-COL-040-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-COL-040-CTLFireability-01: AG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-07: LTL/CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
BART-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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BART-COL-040-CTLFireability-08: INITIAL true skeleton: preprocessing
BART-COL-040-CTLFireability-09: INITIAL false skeleton: preprocessing
BART-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
BART-COL-040-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-COL-040-CTLFireability-01: AG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-07: LTL/CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
BART-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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BART-COL-040-CTLFireability-03: INITIAL true skeleton: preprocessing
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BART-COL-040-CTLFireability-06: INITIAL false skeleton: preprocessing
BART-COL-040-CTLFireability-08: INITIAL true skeleton: preprocessing
BART-COL-040-CTLFireability-09: INITIAL false skeleton: preprocessing
BART-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
BART-COL-040-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-COL-040-CTLFireability-01: AG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-07: LTL/CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
BART-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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BART-COL-040-CTLFireability-03: INITIAL true skeleton: preprocessing
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BART-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
BART-COL-040-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-COL-040-CTLFireability-01: AG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-07: LTL/CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
BART-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

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BART-COL-040-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-COL-040-CTLFireability-01: AG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-07: LTL/CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
BART-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

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BART-COL-040-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-COL-040-CTLFireability-01: AG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-07: LTL/CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
BART-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

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BART-COL-040-CTLFireability-14: INITIAL false skeleton: preprocessing

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BART-COL-040-CTLFireability-01: AG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-07: LTL/CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
BART-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

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BART-COL-040-CTLFireability-02: INITIAL false skeleton: preprocessing
BART-COL-040-CTLFireability-03: INITIAL true skeleton: preprocessing
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BART-COL-040-CTLFireability-06: INITIAL false skeleton: preprocessing
BART-COL-040-CTLFireability-08: INITIAL true skeleton: preprocessing
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BART-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
BART-COL-040-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-COL-040-CTLFireability-01: AG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-07: LTL/CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
BART-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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BART-COL-040-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-COL-040-CTLFireability-01: AG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-07: LTL/CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
BART-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

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BART-COL-040-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-COL-040-CTLFireability-01: AG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-07: LTL/CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
BART-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

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BART-COL-040-CTLFireability-01: AG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-07: LTL/CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
BART-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

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BART-COL-040-CTLFireability-07: LTL/CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
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BART-COL-040-CTLFireability-07: LTL/CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
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BART-COL-040-CTLFireability-07: LTL/CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-07: LTL/CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
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BART-COL-040-CTLFireability-07: LTL/CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-07: LTL/CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-07: LTL/CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
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BART-COL-040-CTLFireability-07: LTL/CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-07: LTL/CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-07: LTL/CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-12: CONJ 0 0 0 0 5 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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BART-COL-040-CTLFireability-11: EG 0 0 0 0 1 0 0 0
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/home/mcc/BenchKit/BenchKit_head.sh: line 62: 413 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BART-COL-040"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is BART-COL-040, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r004-tall-162037986200572"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/BART-COL-040.tgz
mv BART-COL-040 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;