About the Execution of LoLA for AirplaneLD-PT-2000
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
4340.411 | 299648.00 | 506116.00 | 645.30 | TFFFFFFFTTFFFTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r004-tall-162037985800302.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is AirplaneLD-PT-2000, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r004-tall-162037985800302
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 83M
-rw-r--r-- 1 mcc users 8.2M May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 27M May 5 16:58 CTLCardinality.xml
-rw-r--r-- 1 mcc users 3.5M May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 20M May 5 16:58 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 295K Mar 28 15:43 LTLCardinality.txt
-rw-r--r-- 1 mcc users 695K Mar 28 15:43 LTLCardinality.xml
-rw-r--r-- 1 mcc users 617K Mar 28 15:43 LTLFireability.txt
-rw-r--r-- 1 mcc users 2.5M Mar 28 15:43 LTLFireability.xml
-rw-r--r-- 1 mcc users 743K Mar 23 01:29 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 1.7M Mar 23 01:29 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 370K Mar 22 09:56 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 1.4M Mar 22 09:56 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 285K Mar 22 09:09 UpperBounds.txt
-rw-r--r-- 1 mcc users 521K Mar 22 09:09 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 5 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 16M May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-PT-2000-ReachabilityCardinality-00
FORMULA_NAME AirplaneLD-PT-2000-ReachabilityCardinality-01
FORMULA_NAME AirplaneLD-PT-2000-ReachabilityCardinality-02
FORMULA_NAME AirplaneLD-PT-2000-ReachabilityCardinality-03
FORMULA_NAME AirplaneLD-PT-2000-ReachabilityCardinality-04
FORMULA_NAME AirplaneLD-PT-2000-ReachabilityCardinality-05
FORMULA_NAME AirplaneLD-PT-2000-ReachabilityCardinality-06
FORMULA_NAME AirplaneLD-PT-2000-ReachabilityCardinality-07
FORMULA_NAME AirplaneLD-PT-2000-ReachabilityCardinality-08
FORMULA_NAME AirplaneLD-PT-2000-ReachabilityCardinality-09
FORMULA_NAME AirplaneLD-PT-2000-ReachabilityCardinality-10
FORMULA_NAME AirplaneLD-PT-2000-ReachabilityCardinality-11
FORMULA_NAME AirplaneLD-PT-2000-ReachabilityCardinality-12
FORMULA_NAME AirplaneLD-PT-2000-ReachabilityCardinality-13
FORMULA_NAME AirplaneLD-PT-2000-ReachabilityCardinality-14
FORMULA_NAME AirplaneLD-PT-2000-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1620439512479
starting LoLA
BK_INPUT AirplaneLD-PT-2000
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA AirplaneLD-PT-2000-ReachabilityCardinality-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-2000-ReachabilityCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-2000-ReachabilityCardinality-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-2000-ReachabilityCardinality-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-2000-ReachabilityCardinality-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-2000-ReachabilityCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-2000-ReachabilityCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-2000-ReachabilityCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-2000-ReachabilityCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-2000-ReachabilityCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-2000-ReachabilityCardinality-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-2000-ReachabilityCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-2000-ReachabilityCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-2000-ReachabilityCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-2000-ReachabilityCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-2000-ReachabilityCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620439812127
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 50 (type SKEL/FNDP) for 3 AirplaneLD-PT-2000-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type SKEL/EQUN) for 3 AirplaneLD-PT-2000-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 53 (type SKEL/SRCH) for 3 AirplaneLD-PT-2000-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 54 (type SKEL/SRCH) for 3 AirplaneLD-PT-2000-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 53 (type SKEL/SRCH) for AirplaneLD-PT-2000-ReachabilityCardinality-01
lola: result : true
lola: markings : 9
lola: fired transitions : 8
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 50 (type FNDP) for AirplaneLD-PT-2000-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 51 (type EQUN) for AirplaneLD-PT-2000-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 54 (type SRCH) for AirplaneLD-PT-2000-ReachabilityCardinality-01 (obsolete)
lola: FINISHED task # 50 (type SKEL/FNDP) for AirplaneLD-PT-2000-ReachabilityCardinality-01
lola: result : true
lola: fired transitions : 7
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-51.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 51 (type SKEL/EQUN) for AirplaneLD-PT-2000-ReachabilityCardinality-01
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 58 (type SKEL/FNDP) for 6 AirplaneLD-PT-2000-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 59 (type SKEL/EQUN) for 6 AirplaneLD-PT-2000-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 61 (type SKEL/SRCH) for 6 AirplaneLD-PT-2000-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 62 (type SKEL/SRCH) for 6 AirplaneLD-PT-2000-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 58 (type SKEL/FNDP) for AirplaneLD-PT-2000-ReachabilityCardinality-02
lola: result : true
lola: fired transitions : 7
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 59 (type EQUN) for AirplaneLD-PT-2000-ReachabilityCardinality-02 (obsolete)
lola: CANCELED task # 61 (type SRCH) for AirplaneLD-PT-2000-ReachabilityCardinality-02 (obsolete)
lola: CANCELED task # 62 (type SRCH) for AirplaneLD-PT-2000-ReachabilityCardinality-02 (obsolete)
lola: FINISHED task # 59 (type SKEL/EQUN) for AirplaneLD-PT-2000-ReachabilityCardinality-02
lola: result : unknown
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 66 (type SKEL/FNDP) for 24 AirplaneLD-PT-2000-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 67 (type SKEL/EQUN) for 24 AirplaneLD-PT-2000-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 69 (type SKEL/SRCH) for 24 AirplaneLD-PT-2000-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 70 (type SKEL/SRCH) for 24 AirplaneLD-PT-2000-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 69 (type SKEL/SRCH) for AirplaneLD-PT-2000-ReachabilityCardinality-08
lola: result : false
lola: markings : 200
lola: fired transitions : 375
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 66 (type FNDP) for AirplaneLD-PT-2000-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 67 (type EQUN) for AirplaneLD-PT-2000-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 70 (type SRCH) for AirplaneLD-PT-2000-ReachabilityCardinality-08 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-67.sara.
sara: place or transition ordering is non-deterministic
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 67 (type SKEL/EQUN) for AirplaneLD-PT-2000-ReachabilityCardinality-08
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 73 (type SKEL/FNDP) for 30 AirplaneLD-PT-2000-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 74 (type SKEL/EQUN) for 30 AirplaneLD-PT-2000-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 76 (type SKEL/SRCH) for 30 AirplaneLD-PT-2000-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type SKEL/SRCH) for 30 AirplaneLD-PT-2000-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 76 (type SKEL/SRCH) for AirplaneLD-PT-2000-ReachabilityCardinality-10
lola: result : false
lola: markings : 13
lola: fired transitions : 12
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 73 (type FNDP) for AirplaneLD-PT-2000-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 74 (type EQUN) for AirplaneLD-PT-2000-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 77 (type SRCH) for AirplaneLD-PT-2000-ReachabilityCardinality-10 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-74.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 74 (type SKEL/EQUN) for AirplaneLD-PT-2000-ReachabilityCardinality-10
lola: result : false
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 81 (type SKEL/FNDP) for 9 AirplaneLD-PT-2000-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 82 (type SKEL/EQUN) for 9 AirplaneLD-PT-2000-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 84 (type SKEL/SRCH) for 9 AirplaneLD-PT-2000-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 85 (type SKEL/SRCH) for 9 AirplaneLD-PT-2000-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 84 (type SKEL/SRCH) for AirplaneLD-PT-2000-ReachabilityCardinality-03
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 81 (type FNDP) for AirplaneLD-PT-2000-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 82 (type EQUN) for AirplaneLD-PT-2000-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 85 (type SRCH) for AirplaneLD-PT-2000-ReachabilityCardinality-03 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-82.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 81 (type SKEL/FNDP) for AirplaneLD-PT-2000-ReachabilityCardinality-03
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 82 (type SKEL/EQUN) for AirplaneLD-PT-2000-ReachabilityCardinality-03
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 89 (type SKEL/FNDP) for 18 AirplaneLD-PT-2000-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 90 (type SKEL/EQUN) for 18 AirplaneLD-PT-2000-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 92 (type SKEL/SRCH) for 18 AirplaneLD-PT-2000-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 93 (type SKEL/SRCH) for 18 AirplaneLD-PT-2000-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 92 (type SKEL/SRCH) for AirplaneLD-PT-2000-ReachabilityCardinality-06
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 93 (type SKEL/SRCH) for AirplaneLD-PT-2000-ReachabilityCardinality-06
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 89 (type FNDP) for AirplaneLD-PT-2000-ReachabilityCardinality-06 (obsolete)
lola: CANCELED task # 90 (type EQUN) for AirplaneLD-PT-2000-ReachabilityCardinality-06 (obsolete)
lola: FINISHED task # 89 (type SKEL/FNDP) for AirplaneLD-PT-2000-ReachabilityCardinality-06
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 90 (type SKEL/EQUN) for AirplaneLD-PT-2000-ReachabilityCardinality-06
lola: result : unknown
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 96 (type SKEL/FNDP) for 39 AirplaneLD-PT-2000-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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AirplaneLD-PT-2000-ReachabilityCardinality-00: INITIAL 0 0 0 0 0 0 0 0
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AirplaneLD-PT-2000-ReachabilityCardinality-02: AG 0 0 0 0 2 0 0 3
AirplaneLD-PT-2000-ReachabilityCardinality-03: AG 0 0 0 0 3 0 0 2
AirplaneLD-PT-2000-ReachabilityCardinality-04: INITIAL 0 0 0 0 0 0 0 0
AirplaneLD-PT-2000-ReachabilityCardinality-05: INITIAL 0 0 0 0 0 0 0 0
AirplaneLD-PT-2000-ReachabilityCardinality-06: AG 0 0 0 0 4 0 0 1
AirplaneLD-PT-2000-ReachabilityCardinality-07: INITIAL 0 0 0 0 0 0 0 0
AirplaneLD-PT-2000-ReachabilityCardinality-09: INITIAL 0 0 0 0 0 0 0 0
AirplaneLD-PT-2000-ReachabilityCardinality-11: EF 0 0 0 0 0 0 0 0
AirplaneLD-PT-2000-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
AirplaneLD-PT-2000-ReachabilityCardinality-13: EF 0 0 0 0 3 0 0 2
AirplaneLD-PT-2000-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
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AirplaneLD-PT-2000-ReachabilityCardinality-00: INITIAL 0 0 0 0 0 0 0 0
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AirplaneLD-PT-2000-ReachabilityCardinality-02: AG 0 0 0 0 2 0 0 3
AirplaneLD-PT-2000-ReachabilityCardinality-03: AG 0 0 0 0 3 0 0 2
AirplaneLD-PT-2000-ReachabilityCardinality-04: INITIAL 0 0 0 0 0 0 0 0
AirplaneLD-PT-2000-ReachabilityCardinality-05: INITIAL 0 0 0 0 0 0 0 0
AirplaneLD-PT-2000-ReachabilityCardinality-06: AG 0 0 0 0 4 0 0 1
AirplaneLD-PT-2000-ReachabilityCardinality-07: INITIAL 0 0 0 0 0 0 0 0
AirplaneLD-PT-2000-ReachabilityCardinality-09: INITIAL 0 0 0 0 0 0 0 0
AirplaneLD-PT-2000-ReachabilityCardinality-11: EF 0 0 0 0 0 0 0 0
AirplaneLD-PT-2000-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
AirplaneLD-PT-2000-ReachabilityCardinality-13: EF 0 0 0 0 3 0 0 2
AirplaneLD-PT-2000-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
AirplaneLD-PT-2000-ReachabilityCardinality-15: INITIAL 0 0 0 0 0 0 0 0
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lola: result : true
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lola: result : true
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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AirplaneLD-PT-2000-ReachabilityCardinality-11: EF false skeleton: tandem / insertion
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AirplaneLD-PT-2000-ReachabilityCardinality-02: AG 0 0 0 0 2 0 0 3
AirplaneLD-PT-2000-ReachabilityCardinality-03: AG 0 0 0 0 3 0 0 2
AirplaneLD-PT-2000-ReachabilityCardinality-06: AG 0 0 0 0 4 0 0 1
AirplaneLD-PT-2000-ReachabilityCardinality-12: AG 0 0 0 0 3 0 0 2
AirplaneLD-PT-2000-ReachabilityCardinality-13: EF 0 0 0 0 3 0 0 2
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AirplaneLD-PT-2000-ReachabilityCardinality-06: AG 0 0 0 0 4 0 0 1
AirplaneLD-PT-2000-ReachabilityCardinality-12: AG 0 0 0 0 3 0 0 2
AirplaneLD-PT-2000-ReachabilityCardinality-13: EF 0 0 0 0 3 0 0 2
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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AirplaneLD-PT-2000-ReachabilityCardinality-12: AG false tandem / relaxed
AirplaneLD-PT-2000-ReachabilityCardinality-13: EF true tandem / insertion
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lola: rewrite Frontend/Parser/formula_rewrite.k:721
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sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-147.sara.
lola: FINISHED task # 147 (type EQUN) for AirplaneLD-PT-2000-ReachabilityCardinality-06
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:721
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lola: rewrite Frontend/Parser/formula_rewrite.k:787
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lola: rewrite Frontend/Parser/formula_rewrite.k:721
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lola: FINISHED task # 156 (type SRCH) for AirplaneLD-PT-2000-ReachabilityCardinality-02
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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AirplaneLD-PT-2000-ReachabilityCardinality-12: AG false tandem / relaxed
AirplaneLD-PT-2000-ReachabilityCardinality-13: EF true tandem / insertion
AirplaneLD-PT-2000-ReachabilityCardinality-14: AG false tandem / relaxed
AirplaneLD-PT-2000-ReachabilityCardinality-15: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
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lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-161.sara.
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lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-168.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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AirplaneLD-PT-2000-ReachabilityCardinality-09: INITIAL true preprocessing
AirplaneLD-PT-2000-ReachabilityCardinality-10: EF false skeleton: tandem / insertion
AirplaneLD-PT-2000-ReachabilityCardinality-11: EF false skeleton: tandem / insertion
AirplaneLD-PT-2000-ReachabilityCardinality-12: AG false tandem / relaxed
AirplaneLD-PT-2000-ReachabilityCardinality-13: EF true tandem / insertion
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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167 EF FNDP 2/1670 0/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 213 t fired, 30 attempts, .
168 EF STEQ 2/3341 0/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 sara is running.
170 EF SRCH 2/3341 1/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 452 m, 90 m/sec, 539 t fired, .
171 EF EXCL 2/3341 1/32 AirplaneLD-PT-2000-ReachabilityCardinality-01 1225 m, 245 m/sec, 1224 t fired, .
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AirplaneLD-PT-2000-ReachabilityCardinality-09: INITIAL true preprocessing
AirplaneLD-PT-2000-ReachabilityCardinality-10: EF false skeleton: tandem / insertion
AirplaneLD-PT-2000-ReachabilityCardinality-11: EF false skeleton: tandem / insertion
AirplaneLD-PT-2000-ReachabilityCardinality-12: AG false tandem / relaxed
AirplaneLD-PT-2000-ReachabilityCardinality-13: EF true tandem / insertion
AirplaneLD-PT-2000-ReachabilityCardinality-14: AG false tandem / relaxed
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167 EF FNDP 7/1668 0/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 593 t fired, 89 attempts, .
168 EF STEQ 7/3339 0/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 sara is running.
170 EF SRCH 7/3339 1/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 1667 m, 243 m/sec, 1997 t fired, .
171 EF EXCL 7/3341 1/32 AirplaneLD-PT-2000-ReachabilityCardinality-01 4024 m, 559 m/sec, 4023 t fired, .
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AirplaneLD-PT-2000-ReachabilityCardinality-12: AG false tandem / relaxed
AirplaneLD-PT-2000-ReachabilityCardinality-13: EF true tandem / insertion
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167 EF FNDP 12/1663 0/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 1008 t fired, 151 attempts, .
168 EF STEQ 12/3334 0/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 sara is running.
170 EF SRCH 12/3334 1/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 2879 m, 242 m/sec, 3352 t fired, .
171 EF EXCL 12/3341 1/32 AirplaneLD-PT-2000-ReachabilityCardinality-01 6699 m, 535 m/sec, 6698 t fired, .
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AirplaneLD-PT-2000-ReachabilityCardinality-13: EF true tandem / insertion
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167 EF FNDP 17/1658 0/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 1373 t fired, 209 attempts, .
168 EF STEQ 17/3329 0/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 sara is running.
170 EF SRCH 17/3329 1/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 4033 m, 230 m/sec, 4621 t fired, .
171 EF EXCL 17/3341 1/32 AirplaneLD-PT-2000-ReachabilityCardinality-01 9388 m, 537 m/sec, 9388 t fired, .
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AirplaneLD-PT-2000-ReachabilityCardinality-12: AG false tandem / relaxed
AirplaneLD-PT-2000-ReachabilityCardinality-13: EF true tandem / insertion
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167 EF FNDP 22/1653 0/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 1793 t fired, 276 attempts, .
168 EF STEQ 22/3324 0/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 sara is running.
170 EF SRCH 22/3324 1/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 5178 m, 229 m/sec, 5866 t fired, .
171 EF EXCL 22/3341 1/32 AirplaneLD-PT-2000-ReachabilityCardinality-01 12007 m, 523 m/sec, 12006 t fired, .
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167 EF FNDP 27/1648 0/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 2228 t fired, 341 attempts, .
168 EF STEQ 27/3319 0/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 sara is running.
170 EF SRCH 27/3319 1/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 6339 m, 232 m/sec, 7204 t fired, .
171 EF EXCL 27/3341 1/32 AirplaneLD-PT-2000-ReachabilityCardinality-01 14774 m, 553 m/sec, 14773 t fired, .
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167 EF FNDP 32/1643 0/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 2668 t fired, 406 attempts, .
168 EF STEQ 32/3314 0/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 sara is running.
170 EF SRCH 32/3314 1/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 7495 m, 231 m/sec, 8490 t fired, .
171 EF EXCL 32/3341 1/32 AirplaneLD-PT-2000-ReachabilityCardinality-01 17590 m, 563 m/sec, 17589 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-2000-ReachabilityCardinality-00: INITIAL true preprocessing
AirplaneLD-PT-2000-ReachabilityCardinality-02: AG false tandem / insertion
AirplaneLD-PT-2000-ReachabilityCardinality-03: AG false tandem / insertion
AirplaneLD-PT-2000-ReachabilityCardinality-04: INITIAL false preprocessing
AirplaneLD-PT-2000-ReachabilityCardinality-05: INITIAL false preprocessing
AirplaneLD-PT-2000-ReachabilityCardinality-06: AG false tandem / relaxed
AirplaneLD-PT-2000-ReachabilityCardinality-07: INITIAL false preprocessing
AirplaneLD-PT-2000-ReachabilityCardinality-08: AG true skeleton: tandem / insertion
AirplaneLD-PT-2000-ReachabilityCardinality-09: INITIAL true preprocessing
AirplaneLD-PT-2000-ReachabilityCardinality-10: EF false skeleton: tandem / insertion
AirplaneLD-PT-2000-ReachabilityCardinality-11: EF false skeleton: tandem / insertion
AirplaneLD-PT-2000-ReachabilityCardinality-12: AG false tandem / relaxed
AirplaneLD-PT-2000-ReachabilityCardinality-13: EF true tandem / insertion
AirplaneLD-PT-2000-ReachabilityCardinality-14: AG false tandem / relaxed
AirplaneLD-PT-2000-ReachabilityCardinality-15: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-2000-ReachabilityCardinality-01: AG 0 1 4 0 3 0 0 2
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
167 EF FNDP 37/1638 0/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 3057 t fired, 466 attempts, .
168 EF STEQ 37/3309 0/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 sara is running.
170 EF SRCH 37/3309 1/5 AirplaneLD-PT-2000-ReachabilityCardinality-01 8764 m, 253 m/sec, 9914 t fired, .
171 EF EXCL 37/3341 1/32 AirplaneLD-PT-2000-ReachabilityCardinality-01 20099 m, 501 m/sec, 20098 t fired, .
Time elapsed: 296 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 168 (type EQUN) for AirplaneLD-PT-2000-ReachabilityCardinality-01
lola: result : true
lola: CANCELED task # 167 (type FNDP) for AirplaneLD-PT-2000-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 170 (type SRCH) for AirplaneLD-PT-2000-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 171 (type EXCL) for AirplaneLD-PT-2000-ReachabilityCardinality-01 (obsolete)
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-2000-ReachabilityCardinality-00: INITIAL true preprocessing
AirplaneLD-PT-2000-ReachabilityCardinality-01: AG false state equation
AirplaneLD-PT-2000-ReachabilityCardinality-02: AG false tandem / insertion
AirplaneLD-PT-2000-ReachabilityCardinality-03: AG false tandem / insertion
AirplaneLD-PT-2000-ReachabilityCardinality-04: INITIAL false preprocessing
AirplaneLD-PT-2000-ReachabilityCardinality-05: INITIAL false preprocessing
AirplaneLD-PT-2000-ReachabilityCardinality-06: AG false tandem / relaxed
AirplaneLD-PT-2000-ReachabilityCardinality-07: INITIAL false preprocessing
AirplaneLD-PT-2000-ReachabilityCardinality-08: AG true skeleton: tandem / insertion
AirplaneLD-PT-2000-ReachabilityCardinality-09: INITIAL true preprocessing
AirplaneLD-PT-2000-ReachabilityCardinality-10: EF false skeleton: tandem / insertion
AirplaneLD-PT-2000-ReachabilityCardinality-11: EF false skeleton: tandem / insertion
AirplaneLD-PT-2000-ReachabilityCardinality-12: AG false tandem / relaxed
AirplaneLD-PT-2000-ReachabilityCardinality-13: EF true tandem / insertion
AirplaneLD-PT-2000-ReachabilityCardinality-14: AG false tandem / relaxed
AirplaneLD-PT-2000-ReachabilityCardinality-15: INITIAL false preprocessing
Time elapsed: 299 secs. Pages in use: 2
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-PT-2000"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is AirplaneLD-PT-2000, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r004-tall-162037985800302"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-PT-2000.tgz
mv AirplaneLD-PT-2000 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;