fond
Model Checking Contest 2021
11th edition, Paris, France, June 23, 2021
Execution of r004-tall-162037985400004
Last Updated
Jun 28, 2021

About the Execution of LoLA for ARMCacheCoherence-PT-none

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
10498.147 1157320.00 1239862.00 2853.70 TT?FFF??FFTFTFFT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.r004-tall-162037985400004.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
...................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is ARMCacheCoherence-PT-none, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r004-tall-162037985400004
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 14M
-rw-r--r-- 1 mcc users 14K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 133K May 10 09:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.4K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 65K May 10 09:42 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Mar 28 15:41 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Mar 28 15:41 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Mar 28 15:41 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Mar 28 15:41 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K Mar 23 01:15 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K Mar 23 01:15 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.0K Mar 22 09:35 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 22 09:35 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Mar 22 09:09 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Mar 22 09:09 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 5 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 14M May 5 16:51 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-00
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-01
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-02
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-03
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-04
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-05
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-06
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-07
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-08
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-09
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-10
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-11
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-12
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-13
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-14
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1620716671736

starting LoLA
BK_INPUT ARMCacheCoherence-PT-none
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability

FORMULA ARMCacheCoherence-PT-none-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1620717829056

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 52 (type EXCL) for 30 ARMCacheCoherence-PT-none-CTLFireability-10
lola: time limit : 162 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 52 (type EXCL) for ARMCacheCoherence-PT-none-CTLFireability-10
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 ARMCacheCoherence-PT-none-CTLFireability-04
lola: time limit : 170 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for ARMCacheCoherence-PT-none-CTLFireability-04
lola: result : false
lola: markings : 14
lola: fired transitions : 32
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 ARMCacheCoherence-PT-none-CTLFireability-03
lola: time limit : 178 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for ARMCacheCoherence-PT-none-CTLFireability-03
lola: result : false
lola: markings : 35
lola: fired transitions : 127
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 ARMCacheCoherence-PT-none-CTLFireability-01
lola: time limit : 187 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 4 (type EXCL) for ARMCacheCoherence-PT-none-CTLFireability-01
lola: result : true
lola: markings : 295925
lola: fired transitions : 894036
lola: time used : 3.000000
lola: memory pages used : 2
lola: LAUNCH task # 50 (type EXCL) for 49 ARMCacheCoherence-PT-none-CTLFireability-15
lola: time limit : 274 sec
lola: memory limit: 32 pages
lola: FINISHED task # 50 (type EXCL) for ARMCacheCoherence-PT-none-CTLFireability-15
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 47 (type EXCL) for 46 ARMCacheCoherence-PT-none-CTLFireability-14
lola: time limit : 297 sec
lola: memory limit: 32 pages
lola: FINISHED task # 47 (type EXCL) for ARMCacheCoherence-PT-none-CTLFireability-14
lola: result : false
lola: markings : 2959
lola: fired transitions : 9614
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 39 ARMCacheCoherence-PT-none-CTLFireability-13
lola: time limit : 324 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for ARMCacheCoherence-PT-none-CTLFireability-13
lola: result : false
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 39 ARMCacheCoherence-PT-none-CTLFireability-13
lola: time limit : 356 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for ARMCacheCoherence-PT-none-CTLFireability-13
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
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lola: result : true
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lola: fired transitions : 1630
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 0/713 1/32 ARMCacheCoherence-PT-none-CTLFireability-02 6060 m, 1212 m/sec, 21370 t fired, .

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7 CTL EXCL 5/713 1/32 ARMCacheCoherence-PT-none-CTLFireability-02 54846 m, 9757 m/sec, 355416 t fired, .

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7 CTL EXCL 10/713 1/32 ARMCacheCoherence-PT-none-CTLFireability-02 93562 m, 7743 m/sec, 659345 t fired, .

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7 CTL EXCL 15/713 1/32 ARMCacheCoherence-PT-none-CTLFireability-02 123341 m, 5955 m/sec, 875899 t fired, .

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7 CTL EXCL 20/713 1/32 ARMCacheCoherence-PT-none-CTLFireability-02 180836 m, 11499 m/sec, 1219111 t fired, .

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7 CTL EXCL 25/713 1/32 ARMCacheCoherence-PT-none-CTLFireability-02 223615 m, 8555 m/sec, 1527265 t fired, .

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7 CTL EXCL 30/713 2/32 ARMCacheCoherence-PT-none-CTLFireability-02 266525 m, 8582 m/sec, 1790127 t fired, .

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7 CTL EXCL 35/713 2/32 ARMCacheCoherence-PT-none-CTLFireability-02 312729 m, 9240 m/sec, 2080129 t fired, .

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7 CTL EXCL 40/713 2/32 ARMCacheCoherence-PT-none-CTLFireability-02 353906 m, 8235 m/sec, 2337074 t fired, .

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7 CTL EXCL 45/713 2/32 ARMCacheCoherence-PT-none-CTLFireability-02 383125 m, 5843 m/sec, 2551149 t fired, .

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7 CTL EXCL 50/713 2/32 ARMCacheCoherence-PT-none-CTLFireability-02 403673 m, 4109 m/sec, 2743709 t fired, .

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7 CTL EXCL 55/713 2/32 ARMCacheCoherence-PT-none-CTLFireability-02 442217 m, 7708 m/sec, 3008405 t fired, .

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7 CTL EXCL 60/713 2/32 ARMCacheCoherence-PT-none-CTLFireability-02 479018 m, 7360 m/sec, 3282273 t fired, .

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7 CTL EXCL 65/713 3/32 ARMCacheCoherence-PT-none-CTLFireability-02 522645 m, 8725 m/sec, 3580693 t fired, .

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7 CTL EXCL 70/713 3/32 ARMCacheCoherence-PT-none-CTLFireability-02 561139 m, 7698 m/sec, 3804806 t fired, .

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7 CTL EXCL 75/713 3/32 ARMCacheCoherence-PT-none-CTLFireability-02 601605 m, 8093 m/sec, 4049955 t fired, .

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7 CTL EXCL 80/713 3/32 ARMCacheCoherence-PT-none-CTLFireability-02 640615 m, 7802 m/sec, 4292270 t fired, .

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7 CTL EXCL 85/713 3/32 ARMCacheCoherence-PT-none-CTLFireability-02 676944 m, 7265 m/sec, 4636717 t fired, .

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7 CTL EXCL 90/713 3/32 ARMCacheCoherence-PT-none-CTLFireability-02 714111 m, 7433 m/sec, 4944321 t fired, .

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7 CTL EXCL 95/713 4/32 ARMCacheCoherence-PT-none-CTLFireability-02 754646 m, 8107 m/sec, 5192850 t fired, .

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7 CTL EXCL 100/713 4/32 ARMCacheCoherence-PT-none-CTLFireability-02 798444 m, 8759 m/sec, 5466324 t fired, .

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7 CTL EXCL 105/713 4/32 ARMCacheCoherence-PT-none-CTLFireability-02 843440 m, 8999 m/sec, 5734035 t fired, .

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7 CTL EXCL 110/713 4/32 ARMCacheCoherence-PT-none-CTLFireability-02 880640 m, 7440 m/sec, 5978004 t fired, .

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7 CTL EXCL 115/713 4/32 ARMCacheCoherence-PT-none-CTLFireability-02 921019 m, 8075 m/sec, 6262995 t fired, .

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7 CTL EXCL 120/713 4/32 ARMCacheCoherence-PT-none-CTLFireability-02 957415 m, 7279 m/sec, 6504192 t fired, .

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7 CTL EXCL 135/713 5/32 ARMCacheCoherence-PT-none-CTLFireability-02 1065613 m, 7267 m/sec, 7242191 t fired, .

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7 CTL EXCL 140/713 5/32 ARMCacheCoherence-PT-none-CTLFireability-02 1101074 m, 7092 m/sec, 7507255 t fired, .

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7 CTL EXCL 145/713 5/32 ARMCacheCoherence-PT-none-CTLFireability-02 1137963 m, 7377 m/sec, 7754975 t fired, .

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7 CTL EXCL 150/713 5/32 ARMCacheCoherence-PT-none-CTLFireability-02 1165266 m, 5460 m/sec, 7975985 t fired, .

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7 CTL EXCL 155/713 5/32 ARMCacheCoherence-PT-none-CTLFireability-02 1200707 m, 7088 m/sec, 8222202 t fired, .

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7 CTL EXCL 160/713 6/32 ARMCacheCoherence-PT-none-CTLFireability-02 1233549 m, 6568 m/sec, 8511224 t fired, .

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7 CTL EXCL 165/713 6/32 ARMCacheCoherence-PT-none-CTLFireability-02 1266931 m, 6676 m/sec, 8791312 t fired, .

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7 CTL EXCL 170/713 6/32 ARMCacheCoherence-PT-none-CTLFireability-02 1304285 m, 7470 m/sec, 9043750 t fired, .

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7 CTL EXCL 175/713 6/32 ARMCacheCoherence-PT-none-CTLFireability-02 1336973 m, 6537 m/sec, 9279231 t fired, .

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7 CTL EXCL 180/713 6/32 ARMCacheCoherence-PT-none-CTLFireability-02 1371070 m, 6819 m/sec, 9532643 t fired, .

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7 CTL EXCL 185/713 6/32 ARMCacheCoherence-PT-none-CTLFireability-02 1403428 m, 6471 m/sec, 9781526 t fired, .

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7 CTL EXCL 190/713 6/32 ARMCacheCoherence-PT-none-CTLFireability-02 1434701 m, 6254 m/sec, 10020554 t fired, .

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7 CTL EXCL 195/713 7/32 ARMCacheCoherence-PT-none-CTLFireability-02 1469234 m, 6906 m/sec, 10272618 t fired, .

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7 CTL EXCL 210/713 7/32 ARMCacheCoherence-PT-none-CTLFireability-02 1569409 m, 6580 m/sec, 11026028 t fired, .

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7 CTL EXCL 215/713 7/32 ARMCacheCoherence-PT-none-CTLFireability-02 1601053 m, 6328 m/sec, 11278970 t fired, .

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7 CTL EXCL 220/713 7/32 ARMCacheCoherence-PT-none-CTLFireability-02 1636370 m, 7063 m/sec, 11571004 t fired, .

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7 CTL EXCL 225/713 7/32 ARMCacheCoherence-PT-none-CTLFireability-02 1684868 m, 9699 m/sec, 11962242 t fired, .

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7 CTL EXCL 230/713 8/32 ARMCacheCoherence-PT-none-CTLFireability-02 1719756 m, 6977 m/sec, 12237888 t fired, .

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7 CTL EXCL 235/713 8/32 ARMCacheCoherence-PT-none-CTLFireability-02 1749932 m, 6035 m/sec, 12469804 t fired, .

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7 CTL EXCL 240/713 8/32 ARMCacheCoherence-PT-none-CTLFireability-02 1782281 m, 6469 m/sec, 12720933 t fired, .

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7 CTL EXCL 245/713 8/32 ARMCacheCoherence-PT-none-CTLFireability-02 1813666 m, 6277 m/sec, 13046896 t fired, .

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7 CTL EXCL 250/713 8/32 ARMCacheCoherence-PT-none-CTLFireability-02 1844399 m, 6146 m/sec, 13291634 t fired, .

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7 CTL EXCL 255/713 8/32 ARMCacheCoherence-PT-none-CTLFireability-02 1872991 m, 5718 m/sec, 13522925 t fired, .

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7 CTL EXCL 260/713 8/32 ARMCacheCoherence-PT-none-CTLFireability-02 1903707 m, 6143 m/sec, 13762996 t fired, .

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7 CTL EXCL 280/713 9/32 ARMCacheCoherence-PT-none-CTLFireability-02 2020936 m, 5811 m/sec, 14710634 t fired, .

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7 CTL EXCL 285/713 9/32 ARMCacheCoherence-PT-none-CTLFireability-02 2050687 m, 5950 m/sec, 14939459 t fired, .

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7 CTL EXCL 290/713 9/32 ARMCacheCoherence-PT-none-CTLFireability-02 2080154 m, 5893 m/sec, 15169526 t fired, .

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7 CTL EXCL 295/713 9/32 ARMCacheCoherence-PT-none-CTLFireability-02 2112685 m, 6506 m/sec, 15452328 t fired, .

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7 CTL EXCL 300/713 9/32 ARMCacheCoherence-PT-none-CTLFireability-02 2142248 m, 5912 m/sec, 15684845 t fired, .

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7 CTL EXCL 305/713 9/32 ARMCacheCoherence-PT-none-CTLFireability-02 2172860 m, 6122 m/sec, 15918563 t fired, .

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7 CTL EXCL 310/713 10/32 ARMCacheCoherence-PT-none-CTLFireability-02 2202406 m, 5909 m/sec, 16161478 t fired, .

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7 CTL EXCL 315/713 10/32 ARMCacheCoherence-PT-none-CTLFireability-02 2231723 m, 5863 m/sec, 16399685 t fired, .

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7 CTL EXCL 320/713 10/32 ARMCacheCoherence-PT-none-CTLFireability-02 2259723 m, 5600 m/sec, 16625503 t fired, .

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7 CTL EXCL 325/713 10/32 ARMCacheCoherence-PT-none-CTLFireability-02 2286879 m, 5431 m/sec, 16847566 t fired, .

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7 CTL EXCL 330/713 10/32 ARMCacheCoherence-PT-none-CTLFireability-02 2316381 m, 5900 m/sec, 17082972 t fired, .

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7 CTL EXCL 355/713 11/32 ARMCacheCoherence-PT-none-CTLFireability-02 2462364 m, 5245 m/sec, 18336774 t fired, .

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7 CTL EXCL 360/713 11/32 ARMCacheCoherence-PT-none-CTLFireability-02 2489567 m, 5440 m/sec, 18569810 t fired, .

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7 CTL EXCL 365/713 11/32 ARMCacheCoherence-PT-none-CTLFireability-02 2519689 m, 6024 m/sec, 18804102 t fired, .

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7 CTL EXCL 370/713 11/32 ARMCacheCoherence-PT-none-CTLFireability-02 2543198 m, 4701 m/sec, 19026799 t fired, .

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7 CTL EXCL 375/713 11/32 ARMCacheCoherence-PT-none-CTLFireability-02 2567109 m, 4782 m/sec, 19243662 t fired, .

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7 CTL EXCL 380/713 11/32 ARMCacheCoherence-PT-none-CTLFireability-02 2593899 m, 5358 m/sec, 19475164 t fired, .

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7 CTL EXCL 385/713 11/32 ARMCacheCoherence-PT-none-CTLFireability-02 2619450 m, 5110 m/sec, 19695667 t fired, .

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7 CTL EXCL 390/713 11/32 ARMCacheCoherence-PT-none-CTLFireability-02 2645590 m, 5228 m/sec, 19924706 t fired, .

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7 CTL EXCL 395/713 12/32 ARMCacheCoherence-PT-none-CTLFireability-02 2669478 m, 4777 m/sec, 20143998 t fired, .

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7 CTL EXCL 405/713 12/32 ARMCacheCoherence-PT-none-CTLFireability-02 2719467 m, 4911 m/sec, 20577925 t fired, .

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7 CTL EXCL 425/713 12/32 ARMCacheCoherence-PT-none-CTLFireability-02 2817087 m, 4843 m/sec, 21461478 t fired, .

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7 CTL EXCL 430/713 12/32 ARMCacheCoherence-PT-none-CTLFireability-02 2839786 m, 4539 m/sec, 21685311 t fired, .

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7 CTL EXCL 435/713 12/32 ARMCacheCoherence-PT-none-CTLFireability-02 2868583 m, 5759 m/sec, 21952252 t fired, .

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7 CTL EXCL 440/713 12/32 ARMCacheCoherence-PT-none-CTLFireability-02 2894696 m, 5222 m/sec, 22183201 t fired, .

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7 CTL EXCL 445/713 13/32 ARMCacheCoherence-PT-none-CTLFireability-02 2922641 m, 5589 m/sec, 22421118 t fired, .

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7 CTL EXCL 450/713 13/32 ARMCacheCoherence-PT-none-CTLFireability-02 2946695 m, 4810 m/sec, 22635252 t fired, .

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7 CTL EXCL 455/713 13/32 ARMCacheCoherence-PT-none-CTLFireability-02 2971743 m, 5009 m/sec, 22856196 t fired, .

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7 CTL EXCL 460/713 13/32 ARMCacheCoherence-PT-none-CTLFireability-02 2996573 m, 4966 m/sec, 23079326 t fired, .

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7 CTL EXCL 465/713 13/32 ARMCacheCoherence-PT-none-CTLFireability-02 3021040 m, 4893 m/sec, 23303270 t fired, .

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7 CTL EXCL 470/713 13/32 ARMCacheCoherence-PT-none-CTLFireability-02 3043922 m, 4576 m/sec, 23527321 t fired, .

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7 CTL EXCL 475/713 13/32 ARMCacheCoherence-PT-none-CTLFireability-02 3066546 m, 4524 m/sec, 23737420 t fired, .

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7 CTL EXCL 480/713 13/32 ARMCacheCoherence-PT-none-CTLFireability-02 3090456 m, 4782 m/sec, 23959000 t fired, .

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7 CTL EXCL 485/713 13/32 ARMCacheCoherence-PT-none-CTLFireability-02 3114475 m, 4803 m/sec, 24198275 t fired, .

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7 CTL EXCL 490/713 13/32 ARMCacheCoherence-PT-none-CTLFireability-02 3139902 m, 5085 m/sec, 24439584 t fired, .

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7 CTL EXCL 500/713 14/32 ARMCacheCoherence-PT-none-CTLFireability-02 3189471 m, 4903 m/sec, 24884692 t fired, .

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7 CTL EXCL 505/713 14/32 ARMCacheCoherence-PT-none-CTLFireability-02 3211733 m, 4452 m/sec, 25094327 t fired, .

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7 CTL EXCL 510/713 14/32 ARMCacheCoherence-PT-none-CTLFireability-02 3234440 m, 4541 m/sec, 25305370 t fired, .

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7 CTL EXCL 515/713 14/32 ARMCacheCoherence-PT-none-CTLFireability-02 3260291 m, 5170 m/sec, 25560759 t fired, .

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7 CTL EXCL 520/713 14/32 ARMCacheCoherence-PT-none-CTLFireability-02 3283782 m, 4698 m/sec, 25777781 t fired, .

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7 CTL EXCL 525/713 14/32 ARMCacheCoherence-PT-none-CTLFireability-02 3305846 m, 4412 m/sec, 25985777 t fired, .

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7 CTL EXCL 570/713 15/32 ARMCacheCoherence-PT-none-CTLFireability-02 3506981 m, 4057 m/sec, 27993493 t fired, .

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7 CTL EXCL 575/713 15/32 ARMCacheCoherence-PT-none-CTLFireability-02 3529335 m, 4470 m/sec, 28214144 t fired, .

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7 CTL EXCL 580/713 15/32 ARMCacheCoherence-PT-none-CTLFireability-02 3553042 m, 4741 m/sec, 28460326 t fired, .

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7 CTL EXCL 585/713 15/32 ARMCacheCoherence-PT-none-CTLFireability-02 3576785 m, 4748 m/sec, 28705389 t fired, .

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7 CTL EXCL 590/713 15/32 ARMCacheCoherence-PT-none-CTLFireability-02 3598782 m, 4399 m/sec, 28914418 t fired, .

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7 CTL EXCL 640/713 16/32 ARMCacheCoherence-PT-none-CTLFireability-02 3823234 m, 4247 m/sec, 31291514 t fired, .

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7 CTL EXCL 645/713 16/32 ARMCacheCoherence-PT-none-CTLFireability-02 3844429 m, 4239 m/sec, 31513895 t fired, .

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7 CTL EXCL 650/713 17/32 ARMCacheCoherence-PT-none-CTLFireability-02 3869659 m, 5046 m/sec, 31746823 t fired, .

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7 CTL EXCL 655/713 17/32 ARMCacheCoherence-PT-none-CTLFireability-02 3889495 m, 3967 m/sec, 31961933 t fired, .

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7 CTL EXCL 660/713 17/32 ARMCacheCoherence-PT-none-CTLFireability-02 3910288 m, 4158 m/sec, 32177044 t fired, .

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7 CTL EXCL 665/713 17/32 ARMCacheCoherence-PT-none-CTLFireability-02 3932343 m, 4411 m/sec, 32401382 t fired, .

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7 CTL EXCL 5/2853 1/5 ARMCacheCoherence-PT-none-CTLFireability-02 54027 m, -814260 m/sec, 346100 t fired, .

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1 CTL EXCL 15/713 2/32 ARMCacheCoherence-PT-none-CTLFireability-00 440976 m, 27384 m/sec, 1833595 t fired, .
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1 CTL EXCL 20/713 3/32 ARMCacheCoherence-PT-none-CTLFireability-00 573338 m, 26472 m/sec, 2450191 t fired, .
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1 CTL EXCL 25/713 3/32 ARMCacheCoherence-PT-none-CTLFireability-00 700719 m, 25476 m/sec, 3069891 t fired, .
7 CTL EXCL 25/570 1/5 ARMCacheCoherence-PT-none-CTLFireability-02 221045 m, 8230 m/sec, 1516812 t fired, .

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1 CTL EXCL 30/713 4/32 ARMCacheCoherence-PT-none-CTLFireability-00 826936 m, 25243 m/sec, 3693910 t fired, .
7 CTL EXCL 30/570 2/5 ARMCacheCoherence-PT-none-CTLFireability-02 264348 m, 8660 m/sec, 1780194 t fired, .

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7 CTL EXCL 35/570 2/5 ARMCacheCoherence-PT-none-CTLFireability-02 311859 m, 9502 m/sec, 2073849 t fired, .

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7 CTL EXCL 40/570 2/5 ARMCacheCoherence-PT-none-CTLFireability-02 352271 m, 8082 m/sec, 2328437 t fired, .

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7 CTL EXCL 45/570 2/5 ARMCacheCoherence-PT-none-CTLFireability-02 382932 m, 6132 m/sec, 2546990 t fired, .

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7 CTL EXCL 50/570 2/5 ARMCacheCoherence-PT-none-CTLFireability-02 403543 m, 4122 m/sec, 2738988 t fired, .

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7 CTL EXCL 55/570 2/5 ARMCacheCoherence-PT-none-CTLFireability-02 440337 m, 7358 m/sec, 2996543 t fired, .

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7 CTL EXCL 60/570 2/5 ARMCacheCoherence-PT-none-CTLFireability-02 477502 m, 7433 m/sec, 3268430 t fired, .

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1 CTL EXCL 65/713 7/32 ARMCacheCoherence-PT-none-CTLFireability-00 1678822 m, 23841 m/sec, 8068752 t fired, .
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1 CTL EXCL 70/713 8/32 ARMCacheCoherence-PT-none-CTLFireability-00 1798723 m, 23980 m/sec, 8698098 t fired, .
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1 CTL EXCL 75/713 8/32 ARMCacheCoherence-PT-none-CTLFireability-00 1882603 m, 16776 m/sec, 9141324 t fired, .
7 CTL EXCL 75/570 3/5 ARMCacheCoherence-PT-none-CTLFireability-02 599345 m, 7878 m/sec, 4038258 t fired, .

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7 CTL EXCL 80/713 3/5 ARMCacheCoherence-PT-none-CTLFireability-02 639601 m, 8051 m/sec, 4282817 t fired, .

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7 CTL EXCL 85/713 3/5 ARMCacheCoherence-PT-none-CTLFireability-02 675693 m, 7218 m/sec, 4621887 t fired, .

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7 CTL EXCL 90/713 3/5 ARMCacheCoherence-PT-none-CTLFireability-02 712555 m, 7372 m/sec, 4934027 t fired, .

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7 CTL EXCL 95/713 4/5 ARMCacheCoherence-PT-none-CTLFireability-02 753452 m, 8179 m/sec, 5182549 t fired, .

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7 CTL EXCL 100/713 4/5 ARMCacheCoherence-PT-none-CTLFireability-02 796232 m, 8556 m/sec, 5454633 t fired, .

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7 CTL EXCL 105/713 4/5 ARMCacheCoherence-PT-none-CTLFireability-02 841498 m, 9053 m/sec, 5723001 t fired, .

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7 CTL EXCL 110/713 4/5 ARMCacheCoherence-PT-none-CTLFireability-02 879275 m, 7555 m/sec, 5968916 t fired, .

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7 CTL EXCL 115/713 4/5 ARMCacheCoherence-PT-none-CTLFireability-02 920004 m, 8145 m/sec, 6252464 t fired, .

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7 CTL EXCL 135/713 5/5 ARMCacheCoherence-PT-none-CTLFireability-02 1064483 m, 7278 m/sec, 7233647 t fired, .

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7 CTL EXCL 140/713 5/5 ARMCacheCoherence-PT-none-CTLFireability-02 1100079 m, 7119 m/sec, 7498164 t fired, .

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7 CTL EXCL 145/713 5/5 ARMCacheCoherence-PT-none-CTLFireability-02 1136864 m, 7357 m/sec, 7745833 t fired, .

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7 CTL EXCL 150/713 5/5 ARMCacheCoherence-PT-none-CTLFireability-02 1163716 m, 5370 m/sec, 7966079 t fired, .

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7 CTL EXCL 155/713 5/5 ARMCacheCoherence-PT-none-CTLFireability-02 1199341 m, 7125 m/sec, 8211732 t fired, .

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22 CTL EXCL 5/1346 3/32 ARMCacheCoherence-PT-none-CTLFireability-07 669915 m, 133983 m/sec, 4966343 t fired, .

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22 CTL EXCL 55/1346 22/32 ARMCacheCoherence-PT-none-CTLFireability-07 5238121 m, 76744 m/sec, 57152141 t fired, .

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22 CTL EXCL 70/1346 24/32 ARMCacheCoherence-PT-none-CTLFireability-07 5543595 m, 4152 m/sec, 72493043 t fired, .

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19 CTL EXCL 5/2573 2/32 ARMCacheCoherence-PT-none-CTLFireability-06 438000 m, 87600 m/sec, 3243418 t fired, .

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19 CTL EXCL 10/2573 4/32 ARMCacheCoherence-PT-none-CTLFireability-06 808676 m, 74135 m/sec, 6466674 t fired, .

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19 CTL EXCL 15/2573 5/32 ARMCacheCoherence-PT-none-CTLFireability-06 1157675 m, 69799 m/sec, 9681369 t fired, .

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19 CTL EXCL 20/2573 7/32 ARMCacheCoherence-PT-none-CTLFireability-06 1494759 m, 67416 m/sec, 12902969 t fired, .

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19 CTL EXCL 25/2573 8/32 ARMCacheCoherence-PT-none-CTLFireability-06 1824593 m, 65966 m/sec, 16114589 t fired, .

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19 CTL EXCL 30/2573 9/32 ARMCacheCoherence-PT-none-CTLFireability-06 2144861 m, 64053 m/sec, 19336392 t fired, .

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19 CTL EXCL 35/2573 11/32 ARMCacheCoherence-PT-none-CTLFireability-06 2459397 m, 62907 m/sec, 22597530 t fired, .

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19 CTL EXCL 45/2573 13/32 ARMCacheCoherence-PT-none-CTLFireability-06 3073980 m, 60788 m/sec, 29108555 t fired, .

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19 CTL EXCL 80/2573 22/32 ARMCacheCoherence-PT-none-CTLFireability-06 5132583 m, 57340 m/sec, 53109201 t fired, .

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19 CTL EXCL 85/2573 23/32 ARMCacheCoherence-PT-none-CTLFireability-06 5421473 m, 57778 m/sec, 56719092 t fired, .

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19 CTL EXCL 90/2573 24/32 ARMCacheCoherence-PT-none-CTLFireability-06 5709704 m, 57646 m/sec, 60338625 t fired, .

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19 CTL EXCL 95/2573 25/32 ARMCacheCoherence-PT-none-CTLFireability-06 5994196 m, 56898 m/sec, 64111195 t fired, .

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19 CTL EXCL 105/2573 27/32 ARMCacheCoherence-PT-none-CTLFireability-06 6556634 m, 55729 m/sec, 71787263 t fired, .

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FINAL RESULTS
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ARMCacheCoherence-PT-none-CTLFireability-00: CTL true CTL model checker
ARMCacheCoherence-PT-none-CTLFireability-01: CTL true CTL model checker
ARMCacheCoherence-PT-none-CTLFireability-02: CTL unknown AGGR
ARMCacheCoherence-PT-none-CTLFireability-03: CTL false CTL model checker
ARMCacheCoherence-PT-none-CTLFireability-04: CTL false CTL model checker
ARMCacheCoherence-PT-none-CTLFireability-05: CTL false CTL model checker
ARMCacheCoherence-PT-none-CTLFireability-06: CTL unknown AGGR
ARMCacheCoherence-PT-none-CTLFireability-07: CTL unknown AGGR
ARMCacheCoherence-PT-none-CTLFireability-08: CTL false CTL model checker
ARMCacheCoherence-PT-none-CTLFireability-09: CTL false CTL model checker
ARMCacheCoherence-PT-none-CTLFireability-10: F true state space / EG
ARMCacheCoherence-PT-none-CTLFireability-11: CTL false CTL model checker
ARMCacheCoherence-PT-none-CTLFireability-12: CTL true CTL model checker
ARMCacheCoherence-PT-none-CTLFireability-13: DISJ false DISJ
ARMCacheCoherence-PT-none-CTLFireability-14: CTL false CTL model checker
ARMCacheCoherence-PT-none-CTLFireability-15: CTL true CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ARMCacheCoherence-PT-none"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is ARMCacheCoherence-PT-none, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r004-tall-162037985400004"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ARMCacheCoherence-PT-none.tgz
mv ARMCacheCoherence-PT-none execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;