Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/local/x2003239/mcc2020-input.r193-csrt-159033388500218.qcow2', fmt=qcow2 size=4294967296 backing_file=/local/x2003239/mcc2020-input.qcow2 encryption=off cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool itstools
Input is SquareGrid-PT-080408, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r193-csrt-159033388500218
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 684K
-rw-r--r-- 1 mcc users 3.5K Apr 27 15:14 CTLCardinality.txt
-rw-r--r-- 1 mcc users 18K Apr 27 15:14 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Apr 27 15:14 CTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 27 15:14 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Apr 27 15:14 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K Apr 27 15:14 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Apr 27 15:14 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 28 14:02 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 27 15:14 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 28 14:02 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K Apr 27 15:14 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K Apr 27 15:14 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.3K Apr 27 15:14 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 27 15:14 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 27 15:14 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 27 15:14 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Apr 27 15:14 equiv_col
-rw-r--r-- 1 mcc users 7 Apr 27 15:14 instance
-rw-r--r-- 1 mcc users 6 Apr 27 15:14 iscolored
-rwxr-xr-x 1 mcc users 505K Apr 27 15:14 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SquareGrid-PT-080408-00
FORMULA_NAME SquareGrid-PT-080408-01
FORMULA_NAME SquareGrid-PT-080408-02
FORMULA_NAME SquareGrid-PT-080408-03
FORMULA_NAME SquareGrid-PT-080408-04
FORMULA_NAME SquareGrid-PT-080408-05
FORMULA_NAME SquareGrid-PT-080408-06
FORMULA_NAME SquareGrid-PT-080408-07
FORMULA_NAME SquareGrid-PT-080408-08
FORMULA_NAME SquareGrid-PT-080408-09
FORMULA_NAME SquareGrid-PT-080408-10
FORMULA_NAME SquareGrid-PT-080408-11
FORMULA_NAME SquareGrid-PT-080408-12
FORMULA_NAME SquareGrid-PT-080408-13
FORMULA_NAME SquareGrid-PT-080408-14
FORMULA_NAME SquareGrid-PT-080408-15

=== Now, execution of the tool begins

BK_START 1590494366680

[2020-05-26 11:59:28] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -greatspnpath, /home/mcc/BenchKit//greatspn/, -order, META, -manyOrder, -smt, -timeout, 3600]
[2020-05-26 11:59:28] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2020-05-26 11:59:28] [INFO ] Load time of PNML (sax parser for PT used): 121 ms
[2020-05-26 11:59:28] [INFO ] Transformed 896 places.
[2020-05-26 11:59:28] [INFO ] Transformed 1056 transitions.
[2020-05-26 11:59:28] [INFO ] Parsed PT model containing 896 places and 1056 transitions in 174 ms.
Parsed 16 properties from file /home/mcc/execution/LTLFireability.xml in 28 ms.
Working with output stream class java.io.PrintStream
Finished random walk after 26204 steps, including 0 resets, run visited all 47 properties in 1440 ms. (steps per millisecond=18 )
[2020-05-26 11:59:30] [INFO ] Initial state reduction rules for CTL removed 3 formulas.
[2020-05-26 11:59:30] [INFO ] Flatten gal took : 179 ms
FORMULA SquareGrid-PT-080408-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SquareGrid-PT-080408-08 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SquareGrid-PT-080408-01 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2020-05-26 11:59:30] [INFO ] Flatten gal took : 95 ms
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
[2020-05-26 11:59:31] [INFO ] Applying decomposition
[2020-05-26 11:59:31] [INFO ] Flatten gal took : 67 ms
[2020-05-26 11:59:31] [INFO ] Input system was already deterministic with 1056 transitions.
Converted graph to binary with : CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.louvain.binaries_1.0.0.202005100927/bin/convert-linux64, -i, /tmp/graph482785285163259480.txt, -o, /tmp/graph482785285163259480.bin, -w, /tmp/graph482785285163259480.weights], workingDir=null]
Built communities with : CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.louvain.binaries_1.0.0.202005100927/bin/louvain-linux64, /tmp/graph482785285163259480.bin, -l, -1, -v, -w, /tmp/graph482785285163259480.weights, -q, 0, -e, 0.001], workingDir=null]
[2020-05-26 11:59:31] [INFO ] Decomposing Gal with order
[2020-05-26 11:59:31] [INFO ] Rewriting arrays to variables to allow decomposition.
[2020-05-26 11:59:31] [INFO ] Removed a total of 1024 redundant transitions.
[2020-05-26 11:59:32] [INFO ] Flatten gal took : 232 ms
[2020-05-26 11:59:32] [INFO ] Fuse similar labels procedure discarded/fused a total of 0 labels/synchronizations in 13 ms.
[2020-05-26 11:59:32] [INFO ] Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 24 ms
[2020-05-26 11:59:32] [INFO ] Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 1 ms
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.202005100927/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.202005100927/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 13 LTL properties
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 1056 rows 896 cols
Checking formula 0 : !(((!(("((i24.u179.p4il_8_3>=1)&&(i25.u346.pb2_8_2>=1))")U("((i15.u184.p4i_1_6>=1)&&(i15.u308.pbl_1_6>=1))")))||(!(F("((i15.u184.p4i_1_6>=1)&&(i15.u308.pbl_1_6>=1))")))))
Formula 0 simplified : !(!("((i24.u179.p4il_8_3>=1)&&(i25.u346.pb2_8_2>=1))" U "((i15.u184.p4i_1_6>=1)&&(i15.u308.pbl_1_6>=1))") | !F"((i15.u184.p4i_1_6>=1)&&(i15.u308.pbl_1_6>=1))")
built 56 ordering constraints for composite.
built 22 ordering constraints for composite.
built 7 ordering constraints for composite.
built 12 ordering constraints for composite.
built 12 ordering constraints for composite.
built 22 ordering constraints for composite.
built 22 ordering constraints for composite.
built 40 ordering constraints for composite.
built 22 ordering constraints for composite.
built 22 ordering constraints for composite.
built 22 ordering constraints for composite.
built 22 ordering constraints for composite.
built 40 ordering constraints for composite.
built 22 ordering constraints for composite.
built 22 ordering constraints for composite.
built 22 ordering constraints for composite.
built 32 ordering constraints for composite.
built 22 ordering constraints for composite.
built 22 ordering constraints for composite.
built 22 ordering constraints for composite.
built 40 ordering constraints for composite.
built 40 ordering constraints for composite.
[2020-05-26 11:59:32] [INFO ] Computed 353 place invariants in 118 ms
inv : p4i_7_7 + p4il_7_7 = 1
inv : p4i_8_3 + p4il_8_3 = 1
inv : p4i_8_8 + p4il_8_8 = 1
inv : p4i_7_2 + p4il_7_2 = 1
inv : p4i_6_1 + p4il_6_1 = 1
inv : p4i_4_4 + p4il_4_4 = 1
inv : p4i_6_6 + p4il_6_6 = 1
inv : p4i_2_7 + p4il_2_7 = 1
inv : p4i_3_8 + p4il_3_8 = 1
inv : pb1_6_4 + pb2_6_4 + pb3_6_4 + pb4_6_4 + pbl_6_4 = 24
inv : pb1_3_2 + pb2_3_2 + pb3_3_2 + pb4_3_2 + pbl_3_2 = 24
inv : p4i_3_3 + p4il_3_3 = 1
inv : p4o_2_3 + p4ol_2_3 = 1
inv : p4o_5_1 + p4ol_5_1 = 1
inv : p4o_1_2 + p4ol_1_2 = 1
inv : p4o_3_4 + p4ol_3_4 = 1
inv : p1o_9_6 + p1ol_9_6 = 1
inv : p4o_7_3 + p4ol_7_3 = 1
inv : pb1_1_3 + pb2_1_3 + pb3_1_3 + pb4_1_3 + pbl_1_3 = 24
inv : pb1_4_5 + pb2_4_5 + pb3_4_5 + pb4_4_5 + pbl_4_5 = 24
inv : pb1_7_7 + pb2_7_7 + pb3_7_7 + pb4_7_7 + pbl_7_7 = 24
inv : p4i_1_6 + p4il_1_6 = 1
inv : p4o_6_2 + p4ol_6_2 = 1
inv : p4i_5_5 + p4il_5_5 = 1
inv : p1o_4_1 + p1ol_4_1 = 1
inv : p1o_5_3 + p1ol_5_3 = 1
inv : p1o_1_5 + p1ol_1_5 = 1
inv : p1o_8_4 + p1ol_8_4 = 1
inv : p1o_5_8 + p1ol_5_8 = 1
inv : p1o_3_4 + p1ol_3_4 = 1
inv : p1o_7_7 + p1ol_7_7 = 1
inv : p4o_8_4 + p4ol_8_4 = 1
inv : p1i_2_4 + p1il_2_4 = 1
inv : pb1_3_6 + pb2_3_6 + pb3_3_6 + pb4_3_6 + pbl_3_6 = 24
inv : pb1_6_8 + pb2_6_8 + pb3_6_8 + pb4_6_8 + pbl_6_8 = 24
inv : p4o_8_9 + p4ol_8_9 = 1
inv : p1i_1_7 + p1il_1_7 = 1
inv : p4o_4_5 + p4ol_4_5 = 1
inv : pb1_1_7 + pb2_1_7 + pb3_1_7 + pb4_1_7 + pbl_1_7 = 24
inv : p1i_4_4 - p1il_1_1 - p1il_1_2 - p1il_1_3 - p1il_1_4 - p1il_1_5 - p1il_1_6 - p1il_1_7 - p1il_1_8 - p1il_2_1 - p1il_2_2 - p1il_2_3 - p1il_2_4 - p1il_2_5 - p1il_2_6 - p1il_2_7 - p1il_2_8 - p1il_3_1 - p1il_3_2 - p1il_3_3 - p1il_3_4 - p1il_3_5 - p1il_3_6 - p1il_3_7 - p1il_3_8 - p1il_4_1 - p1il_4_2 - p1il_4_3 - p1il_4_5 - p1il_4_6 - p1il_4_7 - p1il_4_8 - p1il_5_1 - p1il_5_2 - p1il_5_3 - p1il_5_4 - p1il_5_5 - p1il_5_6 - p1il_5_7 - p1il_5_8 - p1il_6_1 - p1il_6_2 - p1il_6_3 - p1il_6_4 - p1il_6_5 - p1il_6_6 - p1il_6_7 - p1il_6_8 - p1il_7_1 - p1il_7_2 - p1il_7_3 - p1il_7_4 - p1il_7_5 - p1il_7_6 - p1il_7_7 - p1il_7_8 - p1il_8_1 - p1il_8_2 - p1il_8_3 - p1il_8_4 - p1il_8_5 - p1il_8_6 - p1il_8_7 - p1il_8_8 - p1il_9_1 - p1il_9_2 - p1il_9_3 - p1il_9_4 - p1il_9_5 - p1il_9_6 - p1il_9_7 - p1il_9_8 - p1ol_1_1 - p1ol_1_2 - p1ol_1_3 - p1ol_1_4 - p1ol_1_5 - p1ol_1_6 - p1ol_1_7 - p1ol_1_8 - p1ol_2_1 - p1ol_2_2 - p1ol_2_3 - p1ol_2_4 - p1ol_2_5 - p1ol_2_6 - p1ol_2_7 - p1ol_2_8 - p1ol_3_1 - p1ol_3_2 - p1ol_3_3 - p1ol_3_4 - p1ol_3_5 - p1ol_3_6 - p1ol_3_7 - p1ol_3_8 - p1ol_4_1 - p1ol_4_2 - p1ol_4_3 - p1ol_4_4 - p1ol_4_5 - p1ol_4_6 - p1ol_4_7 - p1ol_4_8 - p1ol_5_1 - p1ol_5_2 - p1ol_5_3 - p1ol_5_4 - p1ol_5_5 - p1ol_5_6 - p1ol_5_7 - p1ol_5_8 - p1ol_6_1 - p1ol_6_2 - p1ol_6_3 - p1ol_6_4 - p1ol_6_5 - p1ol_6_6 - p1ol_6_7 - p1ol_6_8 - p1ol_7_1 - p1ol_7_2 - p1ol_7_3 - p1ol_7_4 - p1ol_7_5 - p1ol_7_6 - p1ol_7_7 - p1ol_7_8 - p1ol_8_1 - p1ol_8_2 - p1ol_8_3 - p1ol_8_4 - p1ol_8_5 - p1ol_8_6 - p1ol_8_7 - p1ol_8_8 - p1ol_9_1 - p1ol_9_2 - p1ol_9_3 - p1ol_9_4 - p1ol_9_5 - p1ol_9_6 - p1ol_9_7 - p1ol_9_8 - p4il_1_1 - p4il_1_2 - p4il_1_3 - p4il_1_4 - p4il_1_5 - p4il_1_6 - p4il_1_7 - p4il_1_8 - p4il_1_9 - p4il_2_1 - p4il_2_2 - p4il_2_3 - p4il_2_4 - p4il_2_5 - p4il_2_6 - p4il_2_7 - p4il_2_8 - p4il_2_9 - p4il_3_1 - p4il_3_2 - p4il_3_3 - p4il_3_4 - p4il_3_5 - p4il_3_6 - p4il_3_7 - p4il_3_8 - p4il_3_9 - p4il_4_1 - p4il_4_2 - p4il_4_3 - p4il_4_4 - p4il_4_5 - p4il_4_6 - p4il_4_7 - p4il_4_8 - p4il_4_9 - p4il_5_1 - p4il_5_2 - p4il_5_3 - p4il_5_4 - p4il_5_5 - p4il_5_6 - p4il_5_7 - p4il_5_8 - p4il_5_9 - p4il_6_1 - p4il_6_2 - p4il_6_3 - p4il_6_4 - p4il_6_5 - p4il_6_6 - p4il_6_7 - p4il_6_8 - p4il_6_9 - p4il_7_1 - p4il_7_2 - p4il_7_3 - p4il_7_4 - p4il_7_5 - p4il_7_6 - p4il_7_7 - p4il_7_8 - p4il_7_9 - p4il_8_1 - p4il_8_2 - p4il_8_3 - p4il_8_4 - p4il_8_5 - p4il_8_6 - p4il_8_7 - p4il_8_8 - p4il_8_9 - p4ol_1_1 - p4ol_1_2 - p4ol_1_3 - p4ol_1_4 - p4ol_1_5 - p4ol_1_6 - p4ol_1_7 - p4ol_1_8 - p4ol_1_9 - p4ol_2_1 - p4ol_2_2 - p4ol_2_3 - p4ol_2_4 - p4ol_2_5 - p4ol_2_6 - p4ol_2_7 - p4ol_2_8 - p4ol_2_9 - p4ol_3_1 - p4ol_3_2 - p4ol_3_3 - p4ol_3_4 - p4ol_3_5 - p4ol_3_6 - p4ol_3_7 - p4ol_3_8 - p4ol_3_9 - p4ol_4_1 - p4ol_4_2 - p4ol_4_3 - p4ol_4_4 - p4ol_4_5 - p4ol_4_6 - p4ol_4_7 - p4ol_4_8 - p4ol_4_9 - p4ol_5_1 - p4ol_5_2 - p4ol_5_3 - p4ol_5_4 - p4ol_5_5 - p4ol_5_6 - p4ol_5_7 - p4ol_5_8 - p4ol_5_9 - p4ol_6_1 - p4ol_6_2 - p4ol_6_3 - p4ol_6_4 - p4ol_6_5 - p4ol_6_6 - p4ol_6_7 - p4ol_6_8 - p4ol_6_9 - p4ol_7_1 - p4ol_7_2 - p4ol_7_3 - p4ol_7_4 - p4ol_7_5 - p4ol_7_6 - p4ol_7_7 - p4ol_7_8 - p4ol_7_9 - p4ol_8_1 - p4ol_8_2 - p4ol_8_3 - p4ol_8_4 - p4ol_8_5 - p4ol_8_6 - p4ol_8_7 - p4ol_8_8 - p4ol_8_9 - pbl_1_1 - pbl_1_2 - pbl_1_3 - pbl_1_4 - pbl_1_5 - pbl_1_6 - pbl_1_7 - pbl_1_8 - pbl_2_1 - pbl_2_2 - pbl_2_3 - pbl_2_4 - pbl_2_5 - pbl_2_6 - pbl_2_7 - pbl_2_8 - pbl_3_1 - pbl_3_2 - pbl_3_3 - pbl_3_4 - pbl_3_5 - pbl_3_6 - pbl_3_7 - pbl_3_8 - pbl_4_1 - pbl_4_2 - pbl_4_3 - pbl_4_4 - pbl_4_5 - pbl_4_6 - pbl_4_7 - pbl_4_8 - pbl_5_1 - pbl_5_2 - pbl_5_3 - pbl_5_4 - pbl_5_5 - pbl_5_6 - pbl_5_7 - pbl_5_8 - pbl_6_1 - pbl_6_2 - pbl_6_3 - pbl_6_4 - pbl_6_5 - pbl_6_6 - pbl_6_7 - pbl_6_8 - pbl_7_1 - pbl_7_2 - pbl_7_3 - pbl_7_4 - pbl_7_5 - pbl_7_6 - pbl_7_7 - pbl_7_8 - pbl_8_1 - pbl_8_2 - pbl_8_3 - pbl_8_4 - pbl_8_5 - pbl_8_6 - pbl_8_7 - pbl_8_8 = -799
inv : p4o_2_8 + p4ol_2_8 = 1
inv : p1i_3_8 + p1il_3_8 = 1
inv : p4i_4_9 + p4il_4_9 = 1
inv : p1i_8_6 + p1il_8_6 = 1
inv : p1i_8_3 + p1il_8_3 = 1
inv : p1i_4_3 + p1il_4_3 = 1
inv : p4i_1_1 + p4il_1_1 = 1
inv : p4o_6_7 + p4ol_6_7 = 1
inv : pb1_5_1 + pb2_5_1 + pb3_5_1 + pb4_5_1 + pbl_5_1 = 24
inv : pb1_8_3 + pb2_8_3 + pb3_8_3 + pb4_8_3 + pbl_8_3 = 24
inv : pb1_4_1 + pb2_4_1 + pb3_4_1 + pb4_4_1 + pbl_4_1 = 24
inv : p1i_1_4 + p1il_1_4 = 1
inv : p1o_1_8 + p1ol_1_8 = 1
inv : p1i_4_5 + p1il_4_5 = 1
inv : p1o_3_7 + p1ol_3_7 = 1
inv : p1i_5_2 + p1il_5_2 = 1
inv : p1o_2_5 + p1ol_2_5 = 1
inv : pb1_7_4 + pb2_7_4 + pb3_7_4 + pb4_7_4 + pbl_7_4 = 24
inv : p1o_7_5 + p1ol_7_5 = 1
inv : p1o_8_2 + p1ol_8_2 = 1
inv : p1i_5_7 + p1il_5_7 = 1
inv : p1i_6_7 + p1il_6_7 = 1
inv : p1o_3_2 + p1ol_3_2 = 1
inv : p1i_8_8 + p1il_8_8 = 1
inv : p1i_3_6 + p1il_3_6 = 1
inv : p4o_8_6 + p4ol_8_6 = 1
inv : p1i_8_1 + p1il_8_1 = 1
inv : p1o_6_8 + p1ol_6_8 = 1
inv : p4o_4_7 + p4ol_4_7 = 1
inv : p1il_1_1 + p1il_1_2 + p1il_1_3 + p1il_1_4 + p1il_1_5 + p1il_1_6 + p1il_1_7 + p1il_1_8 + p1il_2_1 + p1il_2_2 + p1il_2_3 + p1il_2_4 + p1il_2_5 + p1il_2_6 + p1il_2_7 + p1il_2_8 + p1il_3_1 + p1il_3_2 + p1il_3_3 + p1il_3_4 + p1il_3_5 + p1il_3_6 + p1il_3_7 + p1il_3_8 + p1il_4_1 + p1il_4_2 + p1il_4_3 + p1il_4_4 + p1il_4_5 + p1il_4_6 + p1il_4_7 + p1il_4_8 + p1il_5_1 + p1il_5_2 + p1il_5_3 + p1il_5_4 + p1il_5_5 + p1il_5_6 + p1il_5_7 + p1il_5_8 + p1il_6_1 + p1il_6_2 + p1il_6_3 + p1il_6_4 + p1il_6_5 + p1il_6_6 + p1il_6_7 + p1il_6_8 + p1il_7_1 + p1il_7_2 + p1il_7_3 + p1il_7_4 + p1il_7_5 + p1il_7_6 + p1il_7_7 + p1il_7_8 + p1il_8_1 + p1il_8_2 + p1il_8_3 + p1il_8_4 + p1il_8_5 + p1il_8_6 + p1il_8_7 + p1il_8_8 + p1il_9_1 + p1il_9_2 + p1il_9_3 + p1il_9_4 + p1il_9_5 + p1il_9_6 + p1il_9_7 + p1il_9_8 + p1ol_1_1 + p1ol_1_2 + p1ol_1_3 + p1ol_1_4 + p1ol_1_5 + p1ol_1_6 + p1ol_1_7 + p1ol_1_8 + p1ol_2_1 + p1ol_2_2 + p1ol_2_3 + p1ol_2_4 + p1ol_2_5 + p1ol_2_6 + p1ol_2_7 + p1ol_2_8 + p1ol_3_1 + p1ol_3_2 + p1ol_3_3 + p1ol_3_4 + p1ol_3_5 + p1ol_3_6 + p1ol_3_7 + p1ol_3_8 + p1ol_4_1 + p1ol_4_2 + p1ol_4_3 + p1ol_4_4 + p1ol_4_5 + p1ol_4_6 + p1ol_4_7 + p1ol_4_8 + p1ol_5_1 + p1ol_5_2 + p1ol_5_3 + p1ol_5_4 + p1ol_5_5 + p1ol_5_6 + p1ol_5_7 + p1ol_5_8 + p1ol_6_1 + p1ol_6_2 + p1ol_6_3 + p1ol_6_4 + p1ol_6_5 + p1ol_6_6 + p1ol_6_7 + p1ol_6_8 + p1ol_7_1 + p1ol_7_2 + p1ol_7_3 + p1ol_7_4 + p1ol_7_5 + p1ol_7_6 + p1ol_7_7 + p1ol_7_8 + p1ol_8_1 + p1ol_8_2 + p1ol_8_3 + p1ol_8_4 + p1ol_8_5 + p1ol_8_6 + p1ol_8_7 + p1ol_8_8 + p1ol_9_1 + p1ol_9_2 + p1ol_9_3 + p1ol_9_4 + p1ol_9_5 + p1ol_9_6 + p1ol_9_7 + p1ol_9_8 + p4il_1_1 + p4il_1_2 + p4il_1_3 + p4il_1_4 + p4il_1_5 + p4il_1_6 + p4il_1_7 + p4il_1_8 + p4il_1_9 + p4il_2_1 + p4il_2_2 + p4il_2_3 + p4il_2_4 + p4il_2_5 + p4il_2_6 + p4il_2_7 + p4il_2_8 + p4il_2_9 + p4il_3_1 + p4il_3_2 + p4il_3_3 + p4il_3_4 + p4il_3_5 + p4il_3_6 + p4il_3_7 + p4il_3_8 + p4il_3_9 + p4il_4_1 + p4il_4_2 + p4il_4_3 + p4il_4_4 + p4il_4_5 + p4il_4_6 + p4il_4_7 + p4il_4_8 + p4il_4_9 + p4il_5_1 + p4il_5_2 + p4il_5_3 + p4il_5_4 + p4il_5_5 + p4il_5_6 + p4il_5_7 + p4il_5_8 + p4il_5_9 + p4il_6_1 + p4il_6_2 + p4il_6_3 + p4il_6_4 + p4il_6_5 + p4il_6_6 + p4il_6_7 + p4il_6_8 + p4il_6_9 + p4il_7_1 + p4il_7_2 + p4il_7_3 + p4il_7_4 + p4il_7_5 + p4il_7_6 + p4il_7_7 + p4il_7_8 + p4il_7_9 + p4il_8_1 + p4il_8_2 + p4il_8_3 + p4il_8_4 + p4il_8_5 + p4il_8_6 + p4il_8_7 + p4il_8_8 + p4il_8_9 + p4ol_1_1 + p4ol_1_2 + p4ol_1_3 + p4ol_1_4 + p4ol_1_5 + p4ol_1_6 + p4ol_1_7 + p4ol_1_8 + p4ol_1_9 + p4ol_2_1 + p4ol_2_2 + p4ol_2_3 + p4ol_2_4 + p4ol_2_5 + p4ol_2_6 + p4ol_2_7 + p4ol_2_8 + p4ol_2_9 + p4ol_3_1 + p4ol_3_2 + p4ol_3_3 + p4ol_3_4 + p4ol_3_5 + p4ol_3_6 + p4ol_3_7 + p4ol_3_8 + p4ol_3_9 + p4ol_4_1 + p4ol_4_2 + p4ol_4_3 + p4ol_4_4 + p4ol_4_5 + p4ol_4_6 + p4ol_4_7 + p4ol_4_8 + p4ol_4_9 + p4ol_5_1 + p4ol_5_2 + p4ol_5_3 + p4ol_5_4 + p4ol_5_5 + p4ol_5_6 + p4ol_5_7 + p4ol_5_8 + p4ol_5_9 + p4ol_6_1 + p4ol_6_2 + p4ol_6_3 + p4ol_6_4 + p4ol_6_5 + p4ol_6_6 + p4ol_6_7 + p4ol_6_8 + p4ol_6_9 + p4ol_7_1 + p4ol_7_2 + p4ol_7_3 + p4ol_7_4 + p4ol_7_5 + p4ol_7_6 + p4ol_7_7 + p4ol_7_8 + p4ol_7_9 + p4ol_8_1 + p4ol_8_2 + p4ol_8_3 + p4ol_8_4 + p4ol_8_5 + p4ol_8_6 + p4ol_8_7 + p4ol_8_8 + p4ol_8_9 + pbl_1_1 + pbl_1_2 + pbl_1_3 + pbl_1_4 + pbl_1_5 + pbl_1_6 + pbl_1_7 + pbl_1_8 + pbl_2_1 + pbl_2_2 + pbl_2_3 + pbl_2_4 + pbl_2_5 + pbl_2_6 + pbl_2_7 + pbl_2_8 + pbl_3_1 + pbl_3_2 + pbl_3_3 + pbl_3_4 + pbl_3_5 + pbl_3_6 + pbl_3_7 + pbl_3_8 + pbl_4_1 + pbl_4_2 + pbl_4_3 + pbl_4_4 + pbl_4_5 + pbl_4_6 + pbl_4_7 + pbl_4_8 + pbl_5_1 + pbl_5_2 + pbl_5_3 + pbl_5_4 + pbl_5_5 + pbl_5_6 + pbl_5_7 + pbl_5_8 + pbl_6_1 + pbl_6_2 + pbl_6_3 + pbl_6_4 + pbl_6_5 + pbl_6_6 + pbl_6_7 + pbl_6_8 + pbl_7_1 + pbl_7_2 + pbl_7_3 + pbl_7_4 + pbl_7_5 + pbl_7_6 + pbl_7_7 + pbl_7_8 + pbl_8_1 + pbl_8_2 + pbl_8_3 + pbl_8_4 + pbl_8_5 + pbl_8_6 + pbl_8_7 + pbl_8_8 = 800
inv : pb1_5_5 + pb2_5_5 + pb3_5_5 + pb4_5_5 + pbl_5_5 = 24
inv : p4o_1_9 + p4ol_1_9 = 1
inv : p4o_5_8 + p4ol_5_8 = 1
inv : p4i_1_9 + p4il_1_9 = 1
inv : pb1_2_7 + pb2_2_7 + pb3_2_7 + pb4_2_7 + pbl_2_7 = 24
inv : p4i_2_5 + p4il_2_5 = 1
inv : pb1_6_7 + pb2_6_7 + pb3_6_7 + pb4_6_7 + pbl_6_7 = 24
inv : p4o_7_8 + p4ol_7_8 = 1
inv : pb1_5_8 + pb2_5_8 + pb3_5_8 + pb4_5_8 + pbl_5_8 = 24
inv : p4i_1_8 + p4il_1_8 = 1
inv : p1i_9_5 + p1il_9_5 = 1
inv : pb1_8_6 + pb2_8_6 + pb3_8_6 + pb4_8_6 + pbl_8_6 = 24
inv : p4o_5_3 + p4ol_5_3 = 1
inv : p1i_7_4 + p1il_7_4 = 1
inv : p4o_3_9 + p4ol_3_9 = 1
inv : p1i_3_1 + p1il_3_1 = 1
inv : pb1_4_6 + pb2_4_6 + pb3_4_6 + pb4_4_6 + pbl_4_6 = 24
inv : pb1_2_2 + pb2_2_2 + pb3_2_2 + pb4_2_2 + pbl_2_2 = 24
inv : p4i_5_7 + p4il_5_7 = 1
inv : p4o_2_1 + p4ol_2_1 = 1
inv : p4o_1_4 + p4ol_1_4 = 1
inv : p1o_9_1 + p1ol_9_1 = 1
inv : p4i_6_4 + p4il_6_4 = 1
inv : p1o_4_6 + p1ol_4_6 = 1
inv : p4o_8_2 + p4ol_8_2 = 1
inv : p4o_8_7 + p4ol_8_7 = 1
inv : p4o_7_1 + p4ol_7_1 = 1
inv : pb1_3_3 + pb2_3_3 + pb3_3_3 + pb4_3_3 + pbl_3_3 = 24
inv : p1o_4_8 + p1ol_4_8 = 1
inv : p4o_6_5 + p4ol_6_5 = 1
inv : p4o_1_5 + p4ol_1_5 = 1
inv : p1o_5_5 + p1ol_5_5 = 1
inv : p1o_6_2 + p1ol_6_2 = 1
inv : p4i_2_9 + p4il_2_9 = 1
inv : p4i_4_1 + p4il_4_1 = 1
inv : p1o_2_4 + p1ol_2_4 = 1
inv : pb1_8_2 + pb2_8_2 + pb3_8_2 + pb4_8_2 + pbl_8_2 = 24
inv : p4i_5_2 + p4il_5_2 = 1
inv : p1i_9_6 + p1il_9_6 = 1
inv : p4o_7_6 + p4ol_7_6 = 1
inv : p1o_3_6 + p1ol_3_6 = 1
inv : p1i_3_5 + p1il_3_5 = 1
inv : pb1_7_6 + pb2_7_6 + pb3_7_6 + pb4_7_6 + pbl_7_6 = 24
inv : p1i_5_4 + p1il_5_4 = 1
inv : pb1_4_4 + pb2_4_4 + pb3_4_4 + pb4_4_4 + pbl_4_4 = 24
inv : p1i_2_8 + p1il_2_8 = 1
inv : p4i_1_4 + p4il_1_4 = 1
inv : p1i_6_1 + p1il_6_1 = 1
inv : p4i_6_9 + p4il_6_9 = 1
inv : p1i_9_1 + p1il_9_1 = 1
inv : p4i_7_5 + p4il_7_5 = 1
inv : pb1_1_8 + pb2_1_8 + pb3_1_8 + pb4_1_8 + pbl_1_8 = 24
inv : pb1_5_2 + pb2_5_2 + pb3_5_2 + pb4_5_2 + pbl_5_2 = 24
inv : p1i_6_5 + p1il_6_5 = 1
inv : p1i_7_2 + p1il_7_2 = 1
inv : p4i_2_4 + p4il_2_4 = 1
inv : p1o_6_6 + p1ol_6_6 = 1
inv : pb1_7_1 + pb2_7_1 + pb3_7_1 + pb4_7_1 + pbl_7_1 = 24
inv : p4o_4_2 + p4ol_4_2 = 1
inv : pb1_6_3 + pb2_6_3 + pb3_6_3 + pb4_6_3 + pbl_6_3 = 24
inv : p4o_2_5 + p4ol_2_5 = 1
inv : pb1_3_7 + pb2_3_7 + pb3_3_7 + pb4_3_7 + pbl_3_7 = 24
inv : p4o_6_1 + p4ol_6_1 = 1
inv : p1o_3_1 + p1ol_3_1 = 1
inv : p4i_4_6 + p4il_4_6 = 1
inv : pb1_5_6 + pb2_5_6 + pb3_5_6 + pb4_5_6 + pbl_5_6 = 24
inv : p1o_1_3 + p1ol_1_3 = 1
inv : p1i_2_1 + p1il_2_1 = 1
inv : pb1_5_7 + pb2_5_7 + pb3_5_7 + pb4_5_7 + pbl_5_7 = 24
inv : p1o_8_5 + p1ol_8_5 = 1
inv : p1o_7_3 + p1ol_7_3 = 1
inv : p1o_8_7 + p1ol_8_7 = 1
inv : p4i_4_8 + p4il_4_8 = 1
inv : p4i_6_2 + p4il_6_2 = 1
inv : p4o_5_5 + p4ol_5_5 = 1
inv : pb1_8_7 + pb2_8_7 + pb3_8_7 + pb4_8_7 + pbl_8_7 = 24
inv : pb1_3_8 + pb2_3_8 + pb3_3_8 + pb4_3_8 + pbl_3_8 = 24
inv : p4o_4_4 + p4ol_4_4 = 1
inv : p4i_7_3 + p4il_7_3 = 1
inv : p1i_9_3 + p1il_9_3 = 1
inv : p1i_3_3 + p1il_3_3 = 1
inv : p1i_4_2 + p1il_4_2 = 1
inv : p1o_2_7 + p1ol_2_7 = 1
inv : p4o_6_8 + p4ol_6_8 = 1
inv : p1i_7_7 + p1il_7_7 = 1
inv : p4i_8_6 + p4il_8_6 = 1
inv : p1i_8_4 + p1il_8_4 = 1
inv : p1o_5_7 + p1ol_5_7 = 1
inv : p4i_8_1 + p4il_8_1 = 1
inv : p1i_1_2 + p1il_1_2 = 1
inv : p4o_3_1 + p4ol_3_1 = 1
inv : pb1_2_6 + pb2_2_6 + pb3_2_6 + pb4_2_6 + pbl_2_6 = 24
inv : pb1_2_1 + pb2_2_1 + pb3_2_1 + pb4_2_1 + pbl_2_1 = 24
inv : p1i_4_7 + p1il_4_7 = 1
inv : p4o_6_3 + p4ol_6_3 = 1
inv : p1o_2_2 + p1ol_2_2 = 1
inv : p4o_3_6 + p4ol_3_6 = 1
inv : pb1_1_4 + pb2_1_4 + pb3_1_4 + pb4_1_4 + pbl_1_4 = 24
inv : p4i_5_4 + p4il_5_4 = 1
inv : p4o_1_7 + p4ol_1_7 = 1
inv : p1o_9_4 + p1ol_9_4 = 1
inv : p1o_7_8 + p1ol_7_8 = 1
inv : p4i_2_2 + p4il_2_2 = 1
inv : p4i_3_5 + p4il_3_5 = 1
inv : p1o_4_3 + p1ol_4_3 = 1
inv : p1i_9_8 + p1il_9_8 = 1
inv : p4i_6_7 + p4il_6_7 = 1
inv : p1i_2_6 + p1il_2_6 = 1
inv : p1i_6_3 + p1il_6_3 = 1
inv : p4o_4_9 + p4ol_4_9 = 1
inv : p1i_8_2 + p1il_8_2 = 1
inv : p1i_7_5 + p1il_7_5 = 1
inv : p1i_8_7 + p1il_8_7 = 1
inv : p1i_9_4 + p1il_9_4 = 1
inv : p1i_6_8 + p1il_6_8 = 1
inv : p1i_5_1 + p1il_5_1 = 1
inv : p1i_2_5 + p1il_2_5 = 1
inv : p1i_3_2 + p1il_3_2 = 1
inv : pb1_1_5 + pb2_1_5 + pb3_1_5 + pb4_1_5 + pbl_1_5 = 24
inv : pb1_4_7 + pb2_4_7 + pb3_4_7 + pb4_4_7 + pbl_4_7 = 24
inv : p1i_3_7 + p1il_3_7 = 1
inv : pb1_8_1 + pb2_8_1 + pb3_8_1 + pb4_8_1 + pbl_8_1 = 24
inv : p1o_2_1 + p1ol_2_1 = 1
inv : p1o_3_3 + p1ol_3_3 = 1
inv : p1o_6_4 + p1ol_6_4 = 1
inv : p1o_7_6 + p1ol_7_6 = 1
inv : pb1_2_8 + pb2_2_8 + pb3_2_8 + pb4_2_8 + pbl_2_8 = 24
inv : p4o_7_9 + p4ol_7_9 = 1
inv : pb1_6_2 + pb2_6_2 + pb3_6_2 + pb4_6_2 + pbl_6_2 = 24
inv : p1i_5_6 + p1il_5_6 = 1
inv : p1i_1_3 + p1il_1_3 = 1
inv : p4o_5_7 + p4ol_5_7 = 1
inv : p4o_3_5 + p4ol_3_5 = 1
inv : p4o_7_4 + p4ol_7_4 = 1
inv : p1o_8_8 + p1ol_8_8 = 1
inv : p4o_5_2 + p4ol_5_2 = 1
inv : p4i_2_1 + p4il_2_1 = 1
inv : p4o_1_3 + p4ol_1_3 = 1
inv : pb1_1_1 + pb2_1_1 + pb3_1_1 + pb4_1_1 + pbl_1_1 = 24
inv : pb1_4_3 + pb2_4_3 + pb3_4_3 + pb4_4_3 + pbl_4_3 = 24
inv : pb1_7_5 + pb2_7_5 + pb3_7_5 + pb4_7_5 + pbl_7_5 = 24
inv : p1o_4_5 + p1ol_4_5 = 1
inv : p4o_1_8 + p4ol_1_8 = 1
inv : p1o_9_5 + p1ol_9_5 = 1
inv : p1o_5_2 + p1ol_5_2 = 1
inv : p4i_5_9 + p4il_5_9 = 1
inv : p4i_4_3 + p4il_4_3 = 1
inv : p4i_7_8 + p4il_7_8 = 1
inv : p1o_7_1 + p1ol_7_1 = 1
inv : p4i_8_2 + p4il_8_2 = 1
inv : p1o_2_6 + p1ol_2_6 = 1
inv : pb1_2_4 + pb2_2_4 + pb3_2_4 + pb4_2_4 + pbl_2_4 = 24
inv : p4i_1_2 + p4il_1_2 = 1
inv : p4o_2_2 + p4ol_2_2 = 1
inv : pb1_8_8 + pb2_8_8 + pb3_8_8 + pb4_8_8 + pbl_8_8 = 24
inv : p4i_1_7 + p4il_1_7 = 1
inv : p4i_3_9 + p4il_3_9 = 1
inv : p4o_3_8 + p4ol_3_8 = 1
inv : p4i_5_1 + p4il_5_1 = 1
inv : p4o_6_6 + p4ol_6_6 = 1
inv : p4i_4_5 + p4il_4_5 = 1
inv : pb1_2_5 + pb2_2_5 + pb3_2_5 + pb4_2_5 + pbl_2_5 = 24
inv : p4i_5_6 + p4il_5_6 = 1
inv : p4o_3_3 + p4ol_3_3 = 1
inv : p1o_9_2 + p1ol_9_2 = 1
inv : p4o_2_7 + p4ol_2_7 = 1
inv : p4o_7_2 + p4ol_7_2 = 1
inv : p1o_6_1 + p1ol_6_1 = 1
inv : p4i_6_5 + p4il_6_5 = 1
inv : p1o_4_7 + p1ol_4_7 = 1
inv : p4i_7_6 + p4il_7_6 = 1
inv : p4i_8_4 + p4il_8_4 = 1
inv : p4i_2_6 + p4il_2_6 = 1
inv : pb1_7_2 + pb2_7_2 + pb3_7_2 + pb4_7_2 + pbl_7_2 = 24
inv : p1o_1_6 + p1ol_1_6 = 1
inv : p4i_3_7 + p4il_3_7 = 1
inv : p4o_4_1 + p4ol_4_1 = 1
inv : p4o_4_6 + p4ol_4_6 = 1
inv : pb1_5_3 + pb2_5_3 + pb3_5_3 + pb4_5_3 + pbl_5_3 = 24
inv : pb1_3_4 + pb2_3_4 + pb3_3_4 + pb4_3_4 + pbl_3_4 = 24
inv : p4i_8_9 + p4il_8_9 = 1
inv : p1o_9_7 + p1ol_9_7 = 1
inv : p4i_7_1 + p4il_7_1 = 1
inv : p1o_3_8 + p1ol_3_8 = 1
inv : p1o_5_4 + p1ol_5_4 = 1
inv : p1i_1_5 + p1il_1_5 = 1
inv : p1i_5_8 + p1il_5_8 = 1
inv : p1o_8_3 + p1ol_8_3 = 1
inv : p1o_1_1 + p1ol_1_1 = 1
inv : p4i_3_2 + p4il_3_2 = 1
inv : p1i_6_6 + p1il_6_6 = 1
inv : p4o_8_5 + p4ol_8_5 = 1
inv : p1i_2_3 + p1il_2_3 = 1
inv : p1o_8_6 + p1ol_8_6 = 1
inv : p1o_8_1 + p1ol_8_1 = 1
inv : p1o_9_3 + p1ol_9_3 = 1
inv : p1o_6_7 + p1ol_6_7 = 1
inv : p4o_5_9 + p4ol_5_9 = 1
inv : p1o_9_8 + p1ol_9_8 = 1
inv : p1o_7_4 + p1ol_7_4 = 1
inv : pb1_1_6 + pb2_1_6 + pb3_1_6 + pb4_1_6 + pbl_1_6 = 24
inv : pb1_4_8 + pb2_4_8 + pb3_4_8 + pb4_4_8 + pbl_4_8 = 24
inv : p4o_4_3 + p4ol_4_3 = 1
inv : p1o_1_7 + p1ol_1_7 = 1
inv : p4o_4_8 + p4ol_4_8 = 1
inv : p1o_1_2 + p1ol_1_2 = 1
inv : p4o_5_4 + p4ol_5_4 = 1
inv : p1i_2_2 + p1il_2_2 = 1
inv : p1i_4_1 + p1il_4_1 = 1
inv : p4i_1_3 + p4il_1_3 = 1
inv : pb1_6_5 + pb2_6_5 + pb3_6_5 + pb4_6_5 + pbl_6_5 = 24
inv : p4o_2_6 + p4ol_2_6 = 1
inv : p4o_3_7 + p4ol_3_7 = 1
inv : p1i_5_3 + p1il_5_3 = 1
inv : p1i_7_3 + p1il_7_3 = 1
inv : pb1_1_2 + pb2_1_2 + pb3_1_2 + pb4_1_2 + pbl_1_2 = 24
inv : p4i_5_8 + p4il_5_8 = 1
inv : p1i_1_6 + p1il_1_6 = 1
inv : p4i_3_6 + p4il_3_6 = 1
inv : p4i_5_3 + p4il_5_3 = 1
inv : p1i_1_1 + p1il_1_1 = 1
inv : p4i_3_1 + p4il_3_1 = 1
inv : pb1_8_4 + pb2_8_4 + pb3_8_4 + pb4_8_4 + pbl_8_4 = 24
inv : p4i_6_8 + p4il_6_8 = 1
inv : p1i_9_7 + p1il_9_7 = 1
inv : p4i_6_3 + p4il_6_3 = 1
inv : p1o_4_2 + p1ol_4_2 = 1
inv : p1i_2_7 + p1il_2_7 = 1
inv : p4o_6_4 + p4ol_6_4 = 1
inv : p4o_7_7 + p4ol_7_7 = 1
inv : pb1_3_1 + pb2_3_1 + pb3_3_1 + pb4_3_1 + pbl_3_1 = 24
inv : p1i_7_8 + p1il_7_8 = 1
inv : p4i_8_5 + p4il_8_5 = 1
inv : p1o_6_3 + p1ol_6_3 = 1
inv : p1i_4_6 + p1il_4_6 = 1
inv : p1o_2_3 + p1ol_2_3 = 1
inv : p4o_3_2 + p4ol_3_2 = 1
inv : pb1_7_3 + pb2_7_3 + pb3_7_3 + pb4_7_3 + pbl_7_3 = 24
inv : p4o_1_1 + p4ol_1_1 = 1
inv : p4i_2_3 + p4il_2_3 = 1
inv : p4o_1_6 + p4ol_1_6 = 1
inv : p1o_4_4 + p1ol_4_4 = 1
inv : p1i_6_4 + p1il_6_4 = 1
built 22 ordering constraints for composite.
inv : pb1_4_2 + pb2_4_2 + pb3_4_2 + pb4_4_2 + pbl_4_2 = 24
inv : p4o_8_1 + p4ol_8_1 = 1
inv : p1i_6_2 + p1il_6_2 = 1
inv : p4o_6_9 + p4ol_6_9 = 1
inv : p1i_4_8 + p1il_4_8 = 1
inv : p4i_8_7 + p4il_8_7 = 1
inv : p4o_8_3 + p4ol_8_3 = 1
inv : p1o_2_8 + p1ol_2_8 = 1
inv : pb1_2_3 + pb2_2_3 + pb3_2_3 + pb4_2_3 + pbl_2_3 = 24
inv : p4i_3_4 + p4il_3_4 = 1
inv : p1i_7_6 + p1il_7_6 = 1
inv : p1o_5_6 + p1ol_5_6 = 1
inv : p4i_4_2 + p4il_4_2 = 1
inv : pb1_6_1 + pb2_6_1 + pb3_6_1 + pb4_6_1 + pbl_6_1 = 24
inv : p4i_4_7 + p4il_4_7 = 1
inv : p4o_2_4 + p4ol_2_4 = 1
inv : pb1_3_5 + pb2_3_5 + pb3_3_5 + pb4_3_5 + pbl_3_5 = 24
inv : p4i_7_9 + p4il_7_9 = 1
inv : p4o_2_9 + p4ol_2_9 = 1
inv : p1i_9_2 + p1il_9_2 = 1
inv : p4i_7_4 + p4il_7_4 = 1
inv : p1i_8_5 + p1il_8_5 = 1
inv : p1o_6_5 + p1ol_6_5 = 1
inv : p1o_7_2 + p1ol_7_2 = 1
inv : pb1_8_5 + pb2_8_5 + pb3_8_5 + pb4_8_5 + pbl_8_5 = 24
inv : p4i_1_5 + p4il_1_5 = 1
inv : p1i_5_5 + p1il_5_5 = 1
inv : p4o_7_5 + p4ol_7_5 = 1
inv : p4o_8_8 + p4ol_8_8 = 1
inv : p1i_3_4 + p1il_3_4 = 1
inv : p1o_3_5 + p1ol_3_5 = 1
inv : pb1_7_8 + pb2_7_8 + pb3_7_8 + pb4_7_8 + pbl_7_8 = 24
inv : p1i_7_1 + p1il_7_1 = 1
inv : pb1_5_4 + pb2_5_4 + pb3_5_4 + pb4_5_4 + pbl_5_4 = 24
inv : p4o_5_6 + p4ol_5_6 = 1
inv : p1o_1_4 + p1ol_1_4 = 1
inv : p1o_5_1 + p1ol_5_1 = 1
inv : p1i_1_8 + p1il_1_8 = 1
inv : pb1_6_6 + pb2_6_6 + pb3_6_6 + pb4_6_6 + pbl_6_6 = 24
inv : p4i_2_8 + p4il_2_8 = 1
Total of 353 invariants.
[2020-05-26 11:59:32] [INFO ] Computed 353 place invariants in 133 ms
built 22 ordering constraints for composite.
built 12 ordering constraints for composite.
built 22 ordering constraints for composite.
built 22 ordering constraints for composite.
built 22 ordering constraints for composite.
built 22 ordering constraints for composite.
built 22 ordering constraints for composite.
built 22 ordering constraints for composite.
[2020-05-26 11:59:33] [INFO ] Proved 896 variables to be positive in 1640 ms
[2020-05-26 11:59:33] [INFO ] Computing symmetric may disable matrix : 1056 transitions.
[2020-05-26 11:59:33] [INFO ] Computation of disable matrix completed :0/1056 took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
[2020-05-26 11:59:34] [INFO ] Computation of Complete disable matrix. took 112 ms. Total solver calls (SAT/UNSAT): 0(0/0)
[2020-05-26 11:59:34] [INFO ] Computing symmetric may enable matrix : 1056 transitions.
[2020-05-26 11:59:34] [INFO ] Computation of Complete enable matrix. took 87 ms. Total solver calls (SAT/UNSAT): 0(0/0)
[2020-05-26 11:59:36] [INFO ] Computing symmetric co enabling matrix : 1056 transitions.
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown' twice, overapproximating result to 1.
[2020-05-26 11:59:40] [INFO ] Computation of co-enabling matrix(0/1056) took 3573 ms. Total solver calls (SAT/UNSAT): 55(55/0)
[2020-05-26 11:59:40] [INFO ] Computation of Finished co-enabling matrix. took 3664 ms. Total solver calls (SAT/UNSAT): 55(55/0)
[2020-05-26 11:59:40] [INFO ] Computing Do-Not-Accords matrix : 1056 transitions.
[2020-05-26 11:59:41] [WARNING] SMT solver unexpectedly returned 'unknown' answer, retrying.
[2020-05-26 11:59:41] [WARNING] SMT solver unexpectedly returned 'unknown' answer, retrying.
[2020-05-26 11:59:56] [WARNING] SMT solver unexpectedly returned 'unknown' answer, retrying.
[2020-05-26 12:00:02] [WARNING] SMT solver unexpectedly returned 'unknown' answer, retrying.
[2020-05-26 12:00:07] [WARNING] SMT solver unexpectedly returned 'unknown' answer, retrying.
[2020-05-26 12:00:15] [WARNING] SMT solver unexpectedly returned 'unknown' answer, retrying.
[2020-05-26 12:00:21] [WARNING] SMT solver unexpectedly returned 'unknown' answer, retrying.
[2020-05-26 12:00:23] [WARNING] SMT solver unexpectedly returned 'unknown' answer, retrying.
[2020-05-26 12:00:47] [WARNING] SMT solver unexpectedly returned 'unknown' answer, retrying.
[2020-05-26 12:00:49] [WARNING] SMT solver unexpectedly returned 'unknown' answer, retrying.
[2020-05-26 12:00:55] [WARNING] SMT solver unexpectedly returned 'unknown' answer, retrying.
[2020-05-26 12:01:00] [WARNING] SMT solver unexpectedly returned 'unknown' answer, retrying.
[2020-05-26 12:01:04] [WARNING] SMT solver unexpectedly returned 'unknown' answer, retrying.
[2020-05-26 12:01:05] [WARNING] SMT solver unexpectedly returned 'unknown' answer, retrying.
[2020-05-26 12:01:06] [WARNING] SMT solver unexpectedly returned 'unknown' answer, retrying.
Skipping mayMatrices nes/nds SMT solver raised an error :unknown
java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:320)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:307)
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.computeDoNotAccord(NecessaryEnablingsolver.java:630)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:538)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:831)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:73)
at java.base/java.lang.Thread.run(Thread.java:834)
[2020-05-26 12:01:06] [INFO ] Built C files in 95663ms conformant to PINS in folder :/home/mcc/execution
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O2, model.c], workingDir=/home/mcc/execution]
Compilation finished in 14028 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 76 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, ( !( ((LTLAP0==true))U((LTLAP1==true))) ) || ( !( <>((LTLAP1==true))) ) , --buchi-type=spotba], workingDir=/home/mcc/execution]
/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc: error while loading shared libraries: libltdl.so.7: cannot open shared object file: No such file or directory
WARNING : LTS min runner thread failed on error :java.lang.RuntimeException: Unexpected exception when executing ltsmin :CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, ( !( ((LTLAP0==true))U((LTLAP1==true))) ) || ( !( <>((LTLAP1==true))) ) , --buchi-type=spotba], workingDir=/home/mcc/execution]
127
java.lang.RuntimeException: Unexpected exception when executing ltsmin :CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, ( !( ((LTLAP0==true))U((LTLAP1==true))) ) || ( !( <>((LTLAP1==true))) ) , --buchi-type=spotba], workingDir=/home/mcc/execution]
127
at fr.lip6.move.gal.application.LTSminRunner.checkProperty(LTSminRunner.java:170)
at fr.lip6.move.gal.application.LTSminRunner.access$10(LTSminRunner.java:124)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:93)
at java.base/java.lang.Thread.run(Thread.java:834)
Detected timeout of ITS tools.
[2020-05-26 12:19:32] [INFO ] Flatten gal took : 49 ms
[2020-05-26 12:19:32] [INFO ] Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 7 ms
[2020-05-26 12:19:32] [INFO ] Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 1 ms
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.202005100927/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock, --gen-order, FOLLOW], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.202005100927/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock --gen-order FOLLOW
Read 13 LTL properties
Checking formula 0 : !(((!(("((p4il_8_3>=1)&&(pb2_8_2>=1))")U("((p4i_1_6>=1)&&(pbl_1_6>=1))")))||(!(F("((p4i_1_6>=1)&&(pbl_1_6>=1))")))))
Formula 0 simplified : !(!("((p4il_8_3>=1)&&(pb2_8_2>=1))" U "((p4i_1_6>=1)&&(pbl_1_6>=1))") | !F"((p4i_1_6>=1)&&(pbl_1_6>=1))")
Detected timeout of ITS tools.
[2020-05-26 12:39:34] [INFO ] Flatten gal took : 464 ms

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ LTLFireability = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -greatspnpath /home/mcc/BenchKit//greatspn/ -order META -manyOrder -smt -timeout 3600
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -greatspnpath /home/mcc/BenchKit//greatspn/ -order META -manyOrder -smt -timeout 3600 -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss128m -Xms40m -Xmx16000m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SquareGrid-PT-080408"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool itstools"
echo " Input is SquareGrid-PT-080408, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r193-csrt-159033388500218"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SquareGrid-PT-080408.tgz
mv SquareGrid-PT-080408 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;