Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/local/x2003239/mcc2020-input.r190-csrt-159033383000636.qcow2', fmt=qcow2 size=4294967296 backing_file=/local/x2003239/mcc2020-input.qcow2 encryption=off cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.......................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool smart
Input is ResAllocation-PT-R003C002, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 1
Run identifier is r190-csrt-159033383000636
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 192K
-rw-r--r-- 1 mcc users 4.1K May 14 00:23 CTLCardinality.txt
-rw-r--r-- 1 mcc users 23K May 14 00:23 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K May 13 17:33 CTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 13 17:33 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 12 20:53 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 12 20:53 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.2K May 14 10:00 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K May 14 10:00 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 14 10:00 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K May 14 10:00 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K May 13 13:04 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K May 13 13:04 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.5K May 13 07:32 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 12K May 13 07:32 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K May 13 16:53 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 13 16:53 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 12 20:53 equiv_col
-rw-r--r-- 1 mcc users 9 May 12 20:53 instance
-rw-r--r-- 1 mcc users 6 May 12 20:53 iscolored
-rw-r--r-- 1 mcc users 14K May 12 20:53 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-00
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-01
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-02
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-03
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-04
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-05
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-06
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-07
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-08
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-09
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-10
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-11
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-12
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-13
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-14
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1590409381462

======================================================
========== this is Smart for the MCC'2018 ============
======================================================
Running ResAllocation (PT), instance R003C002
Examination CTLFireability
Parser /home/mcc/BenchKit/bin/parser/CTLFire.jar
Model checker /home/mcc/BenchKit/bin/rem_exec/smart

GOT IT HERE. BS
Petri model created: 12 places, 8 transitions, 30 arcs.
AT ITER 0 NEW BEST:: SOT 77 SOS 55 HAS SOPS 55 HAS SOUS 53 HAS SOUPS 53 WITH SCORE 53.055
AT ITER 2 NEW BEST:: SOT 79 SOS 48 HAS SOPS 48 HAS SOUS 48 HAS SOUPS 48 WITH SCORE 48.048
AT ITER 13 NEW BEST:: SOT 79 SOS 47 HAS SOPS 47 HAS SOUS 47 HAS SOUPS 47 WITH SCORE 47.047
AT ITER 24 NEW BEST:: SOT 79 SOS 46 HAS SOPS 46 HAS SOUS 46 HAS SOUPS 46 WITH SCORE 46.046
AT ITER 37 NEW BEST:: SOT 79 SOS 45 HAS SOPS 45 HAS SOUS 45 HAS SOUPS 45 WITH SCORE 45.045
AT ITER 64 NEW BEST:: SOT 79 SOS 44 HAS SOPS 44 HAS SOUS 44 HAS SOUPS 44 WITH SCORE 44.044
Bounds file is: CTLFireability.xml
PROPERTY: ResAllocation-PT-R003C002-CTLFireability-00 ( (! ((potential((tk(P4)>=1) & (tk(P10)>=1) & (tk(P11)>=1))))) | (! ( (AF( ((potential((tk(P2)>=1) & (tk(P8)>=1) & (tk(P9)>=1)))))) & (! ( ( ((potential((tk(P2)>=1) & (tk(P8)>=1) & (tk(P9)>=1)))) & ((potential((tk(P2)>=1) & (tk(P8)>=1) & (tk(P9)>=1)))) ) & ( ((potential((tk(P1)>=1) & (tk(P4)>=1)))) & ((potential((tk(P5)>=1)))) ) )) )) )
PROPERTY: ResAllocation-PT-R003C002-CTLFireability-01 ( ( ( (AF( ( ((potential((tk(P4)>=1) & (tk(P10)>=1) & (tk(P11)>=1)))) & ((potential((tk(P7)>=1)))) ))) & ((potential((tk(P2)>=1) & (tk(P8)>=1) & (tk(P9)>=1)))) ) & (EX( (AX( ((potential((tk(P2)>=1) & (tk(P8)>=1) & (tk(P9)>=1)))))))) ) & (! ((potential((tk(P6)>=1) & (tk(P12)>=1))))) )
PROPERTY: ResAllocation-PT-R003C002-CTLFireability-02 ( ((potential((tk(P2)>=1)))) | ((potential((tk(P7)>=1)))) )
PROPERTY: ResAllocation-PT-R003C002-CTLFireability-03 ( (! (AF( (AG( ((potential((tk(P7)>=1))))))))) | (EF( ( (EX( ((potential((tk(P6)>=1) & (tk(P12)>=1)))))) | ( (! ((potential((tk(P2)>=1) & (tk(P8)>=1) & (tk(P9)>=1))))) | ((potential((tk(P2)>=1)))) ) ))) )
PROPERTY: ResAllocation-PT-R003C002-CTLFireability-04 ( ( ( (EF( ( ((potential((tk(P2)>=1)))) | ((potential((tk(P6)>=1) & (tk(P12)>=1)))) ))) | ( ( (! ((potential((tk(P5)>=1))))) | (! ((potential((tk(P4)>=1) & (tk(P10)>=1) & (tk(P11)>=1))))) ) & (! ( ((potential((tk(P2)>=1) & (tk(P8)>=1) & (tk(P9)>=1)))) & ((potential((tk(P6)>=1) & (tk(P12)>=1)))) )) ) ) & (! (! (AX( ((potential((tk(P2)>=1) & (tk(P8)>=1) & (tk(P9)>=1)))))))) ) & (EX( ( (EG( ((potential((tk(P6)>=1) & (tk(P12)>=1)))))) & ( ((potential((tk(P4)>=1) & (tk(P10)>=1) & (tk(P11)>=1)))) | (! ((potential((tk(P7)>=1))))) ) ))) )
PROPERTY: ResAllocation-PT-R003C002-CTLFireability-05 ((potential((tk(P7)>=1))))
PROPERTY: ResAllocation-PT-R003C002-CTLFireability-06 ((potential((tk(P5)>=1))))
PROPERTY: ResAllocation-PT-R003C002-CTLFireability-07 (EG( (EU( ((potential((tk(P1)>=1) & (tk(P4)>=1)))) , ((potential((tk(P7)>=1)))) ))))
PROPERTY: ResAllocation-PT-R003C002-CTLFireability-08 ((potential((tk(P2)>=1))))
PROPERTY: ResAllocation-PT-R003C002-CTLFireability-09 (! (! ( ((potential((tk(P3)>=1) & (tk(P6)>=1)))) & (EX( (! ((potential((tk(P7)>=1))))))) )))
PROPERTY: ResAllocation-PT-R003C002-CTLFireability-10 (! (EG( (AX( ((potential((tk(P6)>=1) & (tk(P12)>=1)))))))))
PROPERTY: ResAllocation-PT-R003C002-CTLFireability-11 (AG( (EU( ( ((potential((tk(P2)>=1) & (tk(P8)>=1) & (tk(P9)>=1)))) & ((potential((tk(P2)>=1)))) ) , ( ((potential((tk(P6)>=1) & (tk(P12)>=1)))) | ((potential((tk(P4)>=1) & (tk(P10)>=1) & (tk(P11)>=1)))) ) ))))
PROPERTY: ResAllocation-PT-R003C002-CTLFireability-12 ( ( (! (EG( (! ((potential((tk(P5)>=1)))))))) & (AF( ( ( ((potential((tk(P5)>=1)))) & ((potential((tk(P6)>=1) & (tk(P12)>=1)))) ) | ( ((potential((tk(P4)>=1) & (tk(P10)>=1) & (tk(P11)>=1)))) & ((potential((tk(P2)>=1) & (tk(P8)>=1) & (tk(P9)>=1)))) ) ))) ) & ( ( (AX( ( ((potential((tk(P2)>=1)))) | ((potential((tk(P5)>=1)))) ))) | ( (EX( ((potential((tk(P5)>=1)))))) & (AF( ((potential((tk(P7)>=1)))))) ) ) & (! ((potential((tk(P6)>=1) & (tk(P12)>=1))))) ) )
PROPERTY: ResAllocation-PT-R003C002-CTLFireability-13 (AF( (! (AU( ((potential((tk(P2)>=1)))) , ((potential((tk(P2)>=1) & (tk(P8)>=1) & (tk(P9)>=1)))) )))))
PROPERTY: ResAllocation-PT-R003C002-CTLFireability-14 (! (AU( ( ( ((potential((tk(P2)>=1)))) | ((potential((tk(P3)>=1) & (tk(P6)>=1)))) ) & (! ((potential((tk(P5)>=1))))) ) , (EX( ((potential((tk(P3)>=1) & (tk(P6)>=1)))))) )))
PROPERTY: ResAllocation-PT-R003C002-CTLFireability-15 ( ((potential((tk(P4)>=1) & (tk(P10)>=1) & (tk(P11)>=1)))) | (! ( ( ( ( ((potential((tk(P1)>=1) & (tk(P4)>=1)))) | ((potential((tk(P6)>=1) & (tk(P12)>=1)))) ) & ( ((potential((tk(P7)>=1)))) | ((potential((tk(P3)>=1) & (tk(P6)>=1)))) ) ) & (EF( ((potential((tk(P3)>=1) & (tk(P6)>=1)))))) ) & (! ( ( ((potential((tk(P2)>=1)))) | ((potential((tk(P2)>=1) & (tk(P8)>=1) & (tk(P9)>=1)))) ) & ( ((potential((tk(P2)>=1) & (tk(P8)>=1) & (tk(P9)>=1)))) & ((potential((tk(P2)>=1)))) ) )) )) )
FORMULA ResAllocation-PT-R003C002-CTLFireability-00 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA ResAllocation-PT-R003C002-CTLFireability-01 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA ResAllocation-PT-R003C002-CTLFireability-02 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA ResAllocation-PT-R003C002-CTLFireability-03 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA ResAllocation-PT-R003C002-CTLFireability-04 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA ResAllocation-PT-R003C002-CTLFireability-05 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA ResAllocation-PT-R003C002-CTLFireability-06 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA ResAllocation-PT-R003C002-CTLFireability-07 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA ResAllocation-PT-R003C002-CTLFireability-08 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA ResAllocation-PT-R003C002-CTLFireability-09 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA ResAllocation-PT-R003C002-CTLFireability-10 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA ResAllocation-PT-R003C002-CTLFireability-11 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA ResAllocation-PT-R003C002-CTLFireability-12 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA ResAllocation-PT-R003C002-CTLFireability-13 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA ResAllocation-PT-R003C002-CTLFireability-14 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA ResAllocation-PT-R003C002-CTLFireability-15 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS

BK_STOP 1590409382502

--------------------
content from stderr:

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResAllocation-PT-R003C002"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="smart"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool smart"
echo " Input is ResAllocation-PT-R003C002, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 1"
echo " Run identifier is r190-csrt-159033383000636"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ResAllocation-PT-R003C002.tgz
mv ResAllocation-PT-R003C002 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;