Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/local/x2003239/mcc2020-input.r193-csrt-159033388300076.qcow2', fmt=qcow2 size=4294967296 backing_file=/local/x2003239/mcc2020-input.qcow2 encryption=off cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool itstools
Input is SmallOperatingSystem-PT-MT0512DC0128, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r193-csrt-159033388300076
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 216K
-rw-r--r-- 1 mcc users 4.6K Apr 12 17:46 CTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Apr 12 17:46 CTLCardinality.xml
-rw-r--r-- 1 mcc users 3.5K Apr 11 20:03 CTLFireability.txt
-rw-r--r-- 1 mcc users 22K Apr 11 20:03 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 24 05:38 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Mar 24 05:38 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.1K Apr 14 12:52 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 28 14:02 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Apr 14 12:52 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 28 14:02 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Apr 10 20:33 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K Apr 10 20:33 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.6K Apr 10 05:24 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 10 05:24 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Apr 10 22:29 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Apr 10 22:29 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 24 05:38 equiv_col
-rw-r--r-- 1 mcc users 13 Mar 24 05:38 instance
-rw-r--r-- 1 mcc users 6 Mar 24 05:38 iscolored
-rw-r--r-- 1 mcc users 8.2K Mar 24 05:38 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-00
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-02
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-06
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-13
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1590470041762

[2020-05-26 05:14:04] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -greatspnpath, /home/mcc/BenchKit//greatspn/, -order, META, -manyOrder, -smt, -timeout, 3600]
[2020-05-26 05:14:04] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2020-05-26 05:14:04] [INFO ] Load time of PNML (sax parser for PT used): 27 ms
[2020-05-26 05:14:04] [INFO ] Transformed 9 places.
[2020-05-26 05:14:04] [INFO ] Transformed 8 transitions.
[2020-05-26 05:14:04] [INFO ] Parsed PT model containing 9 places and 8 transitions in 71 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 46 ms.
Incomplete random walk after 100096 steps, including 0 resets, run finished after 66 ms. (steps per millisecond=1516 ) properties seen :[1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1]
// Phase 1: matrix 8 rows 9 cols
[2020-05-26 05:14:04] [INFO ] Computed 4 place invariants in 2 ms
[2020-05-26 05:14:05] [INFO ] [Real]Absence check using 4 positive place invariants in 18 ms returned unsat
Successfully simplified 1 atomic propositions for a total of 1 simplifications.
[2020-05-26 05:14:05] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2020-05-26 05:14:05] [INFO ] Flatten gal took : 33 ms
[2020-05-26 05:14:05] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2020-05-26 05:14:05] [INFO ] Flatten gal took : 4 ms
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2020-05-26 05:14:05] [INFO ] Applying decomposition
[2020-05-26 05:14:05] [INFO ] Flatten gal took : 4 ms
Converted graph to binary with : CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.louvain.binaries_1.0.0.202005100927/bin/convert-linux64, -i, /tmp/graph2995019506800051887.txt, -o, /tmp/graph2995019506800051887.bin, -w, /tmp/graph2995019506800051887.weights], workingDir=null]
Built communities with : CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.louvain.binaries_1.0.0.202005100927/bin/louvain-linux64, /tmp/graph2995019506800051887.bin, -l, -1, -v, -w, /tmp/graph2995019506800051887.weights, -q, 0, -e, 0.001], workingDir=null]
[2020-05-26 05:14:05] [INFO ] Decomposing Gal with order
[2020-05-26 05:14:05] [INFO ] Rewriting arrays to variables to allow decomposition.
[2020-05-26 05:14:05] [INFO ] Removed a total of 1 redundant transitions.
[2020-05-26 05:14:05] [INFO ] Flatten gal took : 180 ms
[2020-05-26 05:14:05] [INFO ] Fuse similar labels procedure discarded/fused a total of 0 labels/synchronizations in 0 ms.
[2020-05-26 05:14:05] [INFO ] Time to serialize gal into /home/mcc/execution/CTLFireability.pnml.gal : 2 ms
[2020-05-26 05:14:05] [INFO ] Time to serialize properties into /home/mcc/execution/CTLFireability.ctl : 3 ms
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.202005100927/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/CTLFireability.pnml.gal, -t, CGAL, -ctl, /home/mcc/execution/CTLFireability.ctl], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.202005100927/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/CTLFireability.pnml.gal -t CGAL -ctl /home/mcc/execution/CTLFireability.ctl
No direction supplied, using forward translation only.
Parsed 15 CTL formulae.
built 3 ordering constraints for composite.
built 8 ordering constraints for composite.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,1.04014e+11,1059.6,2200616,26953,18566,3.23089e+06,412670,45,8.15583e+06,20,8.6094e+06,0


Converting to forward existential form...Done !
Detected timeout of ITS tools.
[2020-05-26 05:34:05] [INFO ] Flatten gal took : 4 ms
[2020-05-26 05:34:05] [INFO ] Time to serialize gal into /home/mcc/execution/CTLFireability.pnml.gal : 26 ms
[2020-05-26 05:34:05] [INFO ] Time to serialize properties into /home/mcc/execution/CTLFireability.ctl : 1 ms
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.202005100927/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/CTLFireability.pnml.gal, -t, CGAL, -ctl, /home/mcc/execution/CTLFireability.ctl, --gen-order, FOLLOW], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.202005100927/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/CTLFireability.pnml.gal -t CGAL -ctl /home/mcc/execution/CTLFireability.ctl --gen-order FOLLOW
No direction supplied, using forward translation only.
Parsed 15 CTL formulae.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,1.04014e+11,89.0644,463536,2,18570,5,1.21945e+06,6,0,47,1.30437e+06,0


Converting to forward existential form...Done !
original formula: EG(((ExecutingTask>=1)||((TaskReady<1)&&((TaskSuspended<1)||(CPUUnit<1)))))
=> equivalent forward existential formula: [FwdG(Init,((ExecutingTask>=1)||((TaskReady<1)&&((TaskSuspended<1)||(CPUUnit<1)))))] != FALSE
Hit Full ! (commute/partial/dont) 1/0/7
(forward)formula 0,0,100.221,463536,1,0,7,1.21945e+06,19,1,2784,1.30437e+06,8
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: !(AG(((((TaskOnDisk>=1)&&(FreeMemSegment>=1))&&(DiskControllerUnit>=1))||(((TaskReady<1)||(CPUUnit<1))&&(LoadingMem<1)))))
=> equivalent forward existential formula: [(FwdU(Init,TRUE) * !(((((TaskOnDisk>=1)&&(FreeMemSegment>=1))&&(DiskControllerUnit>=1))||(((TaskReady<1)||(CPUUnit<1))&&(LoadingMem<1)))))] != FALSE
(forward)formula 1,1,100.492,463536,1,0,10,1.21945e+06,21,3,2798,1.30437e+06,9
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: EF(AG(((((TaskReady<1)&&(TaskOnDisk>=1))&&(DiskControllerUnit>=1))&&(TaskSuspended>=1))))
=> equivalent forward existential formula: [(FwdU(Init,TRUE) * !(E(TRUE U !(((((TaskReady<1)&&(TaskOnDisk>=1))&&(DiskControllerUnit>=1))&&(TaskSuspended>=1))))))] != FALSE
Reverse transition relation is exact ! Faster fixpoint algorithm enabled.
(forward)formula 2,0,115.554,463536,1,0,11,1.21945e+06,27,3,2812,1.30437e+06,12
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-02 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: !(AF((TaskReady>=1)))
=> equivalent forward existential formula: [FwdG(Init,!((TaskReady>=1)))] != FALSE
Hit Full ! (commute/partial/dont) 4/0/4
(forward)formula 3,0,115.587,463536,1,0,12,1.21945e+06,35,4,2830,1.30437e+06,15
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: E((AF((TransferToDisk>=1)) * (((TransferToDisk<1)||(TaskReady<1))||(CPUUnit<1))) U EG((TaskReady<1)))
=> equivalent forward existential formula: [FwdG(FwdU(Init,(!(EG(!((TransferToDisk>=1)))) * (((TransferToDisk<1)||(TaskReady<1))||(CPUUnit<1)))),(TaskReady<1))] != FALSE
(forward)formula 4,0,115.685,463536,1,0,16,1.21945e+06,48,7,2835,1.30437e+06,21
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: E(((ExecutingTask>=1) + AX((ExecutingTask>=1))) U EF((((TaskOnDisk<1)||(FreeMemSegment<1))||(DiskControllerUnit<1))))
=> equivalent forward existential formula: [(FwdU(FwdU(Init,((ExecutingTask>=1) + !(EX(!((ExecutingTask>=1)))))),TRUE) * (((TaskOnDisk<1)||(FreeMemSegment<1))||(DiskControllerUnit<1)))] != FALSE
(forward)formula 5,1,207.395,751884,1,0,21,2.16143e+06,56,11,2841,2.24167e+06,30
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: !(EG(((((((TaskOnDisk<1)||(FreeMemSegment<1))||(DiskControllerUnit<1))||(TaskReady<1))||(CPUUnit<1)) * AF(((TaskReady>=1)&&(CPUUnit>=1))))))
=> equivalent forward existential formula: [FwdG(Init,((((((TaskOnDisk<1)||(FreeMemSegment<1))||(DiskControllerUnit<1))||(TaskReady<1))||(CPUUnit<1)) * !(EG(!(((TaskReady>=1)&&(CPUUnit>=1)))))))] = FALSE
(forward)formula 6,1,220.12,863060,1,0,409,2.71104e+06,68,272,2847,2.70255e+06,292
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-06 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: AF((A((((TaskOnDisk>=1)&&(FreeMemSegment>=1))&&(DiskControllerUnit>=1)) U ((TaskReady>=1)&&(CPUUnit>=1))) * EF((((LoadingMem>=1)&&(TaskReady>=1))&&(CPUUnit>=1)))))
=> equivalent forward existential formula: [FwdG(Init,!((!((E(!(((TaskReady>=1)&&(CPUUnit>=1))) U (!((((TaskOnDisk>=1)&&(FreeMemSegment>=1))&&(DiskControllerUnit>=1))) * !(((TaskReady>=1)&&(CPUUnit>=1))))) + EG(!(((TaskReady>=1)&&(CPUUnit>=1)))))) * E(TRUE U (((LoadingMem>=1)&&(TaskReady>=1))&&(CPUUnit>=1))))))] = FALSE
Hit Full ! (commute/partial/dont) 2/0/6
(forward)formula 7,1,241.482,1247820,1,0,412,5.05918e+06,76,406,2862,4.83325e+06,429
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: !(AF(((((((TaskSuspended>=1)&&(CPUUnit>=1))&&((ExecutingTask>=1)||((TaskSuspended>=1)&&(CPUUnit>=1))))||((TaskReady>=1)&&(CPUUnit>=1)))||(ExecutingTask>=1))||(TaskReady>=1))))
=> equivalent forward existential formula: [FwdG(Init,!(((((((TaskSuspended>=1)&&(CPUUnit>=1))&&((ExecutingTask>=1)||((TaskSuspended>=1)&&(CPUUnit>=1))))||((TaskReady>=1)&&(CPUUnit>=1)))||(ExecutingTask>=1))||(TaskReady>=1))))] != FALSE
Hit Full ! (commute/partial/dont) 1/6/7
(forward)formula 8,0,241.545,1249404,1,0,413,5.05918e+06,84,407,2888,4.83325e+06,432
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: (!(EF(AG(((TaskSuspended>=1)&&(CPUUnit>=1))))) + !(EF(((TaskReady>=1)&&(CPUUnit>=1)))))
=> equivalent forward existential formula: [(FwdU((Init * !(!(E(TRUE U !(E(TRUE U !(((TaskSuspended>=1)&&(CPUUnit>=1))))))))),TRUE) * ((TaskReady>=1)&&(CPUUnit>=1)))] = FALSE
(forward)formula 9,1,283.528,1479764,1,0,415,5.20575e+06,86,407,2888,5.02781e+06,436
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: ((EF(AG((((TaskOnDisk>=1)&&(FreeMemSegment>=1))&&(DiskControllerUnit>=1)))) * E(((TaskReady<1)||(CPUUnit<1)) U (((TaskOnDisk>=1)&&(DiskControllerUnit>=1))&&(TaskSuspended>=1)))) * EF(((ExecutingTask>=1)&&(((TaskOnDisk<1)||(DiskControllerUnit<1))||(TaskSuspended<1)))))
=> equivalent forward existential formula: [(FwdU((Init * (E(TRUE U !(E(TRUE U !((((TaskOnDisk>=1)&&(FreeMemSegment>=1))&&(DiskControllerUnit>=1)))))) * E(((TaskReady<1)||(CPUUnit<1)) U (((TaskOnDisk>=1)&&(DiskControllerUnit>=1))&&(TaskSuspended>=1))))),TRUE) * ((ExecutingTask>=1)&&(((TaskOnDisk<1)||(DiskControllerUnit<1))||(TaskSuspended<1))))] != FALSE
Hit Full ! (commute/partial/dont) 2/0/6
(forward)formula 10,0,321.966,2135780,1,0,419,8.85935e+06,88,407,2893,8.31958e+06,443
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: (!(AF(EG(((TaskReady>=1)&&(CPUUnit>=1))))) * E(AX((ExecutingTask>=1)) U (((TaskOnDisk>=1)&&(FreeMemSegment>=1))&&(DiskControllerUnit>=1))))
=> equivalent forward existential formula: [(FwdU((Init * !(!(EG(!(EG(((TaskReady>=1)&&(CPUUnit>=1)))))))),!(EX(!((ExecutingTask>=1))))) * (((TaskOnDisk>=1)&&(FreeMemSegment>=1))&&(DiskControllerUnit>=1)))] != FALSE
Using saturation style SCC detection
(forward)formula 11,0,325.199,2168116,1,0,422,9.06316e+06,103,408,2906,8.569e+06,446
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: (AG((((TaskReady<1)||(CPUUnit<1)) + EX(((TaskReady>=1)&&(CPUUnit>=1))))) * EG((((TransferToDisk<1)&&(TaskReady<1))||((((TaskOnDisk<1)||(FreeMemSegment<1))||(DiskControllerUnit<1))&&(TransferToDisk<1)))))
=> equivalent forward existential formula: ([((FwdU(Init,TRUE) * !(((TaskReady<1)||(CPUUnit<1)))) * !(EX(((TaskReady>=1)&&(CPUUnit>=1)))))] = FALSE * [(Init * !(EG((((TransferToDisk<1)&&(TaskReady<1))||((((TaskOnDisk<1)||(FreeMemSegment<1))||(DiskControllerUnit<1))&&(TransferToDisk<1))))))] = FALSE)
(forward)formula 12,0,326.684,2181052,1,0,425,9.12208e+06,110,410,2912,8.62586e+06,448
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !
Detected timeout of ITS tools.
[2020-05-26 05:54:06] [INFO ] Flatten gal took : 6 ms
[2020-05-26 05:54:06] [INFO ] Input system was already deterministic with 8 transitions.
[2020-05-26 05:54:06] [INFO ] Transformed 9 places.
[2020-05-26 05:54:06] [INFO ] Transformed 8 transitions.
Running greatSPN : CommandLine [args=[/home/mcc/BenchKit//greatspn//bin/pinvar, /home/mcc/execution/gspn], workingDir=/home/mcc/execution]
Run of greatSPN captured in /home/mcc/execution/outPut.txt
Running greatSPN : CommandLine [args=[/home/mcc/BenchKit//greatspn//bin/RGMEDD2, /home/mcc/execution/gspn, -META, -varord-only], workingDir=/home/mcc/execution]
Run of greatSPN captured in /home/mcc/execution/outPut.txt
Using order generated by GreatSPN with heuristic : META
[2020-05-26 05:54:06] [INFO ] Time to serialize gal into /home/mcc/execution/CTLFireability.pnml.gal : 1 ms
[2020-05-26 05:54:06] [INFO ] Time to serialize properties into /home/mcc/execution/CTLFireability.ctl : 0 ms
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.202005100927/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/CTLFireability.pnml.gal, -t, CGAL, -ctl, /home/mcc/execution/CTLFireability.ctl, --load-order, /home/mcc/execution/model.ord, --gen-order, FOLLOW], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.202005100927/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/CTLFireability.pnml.gal -t CGAL -ctl /home/mcc/execution/CTLFireability.ctl --load-order /home/mcc/execution/model.ord --gen-order FOLLOW
Successfully loaded order from file /home/mcc/execution/model.ord
No direction supplied, using forward translation only.
Parsed 2 CTL formulae.

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ CTLFireability = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution CTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -greatspnpath /home/mcc/BenchKit//greatspn/ -order META -manyOrder -smt -timeout 3600
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination CTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -greatspnpath /home/mcc/BenchKit//greatspn/ -order META -manyOrder -smt -timeout 3600 -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss128m -Xms40m -Xmx16000m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT0512DC0128"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool itstools"
echo " Input is SmallOperatingSystem-PT-MT0512DC0128, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r193-csrt-159033388300076"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT0512DC0128.tgz
mv SmallOperatingSystem-PT-MT0512DC0128 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;