Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/local/x2003239/mcc2020-input.r190-csrt-159033383000668.qcow2', fmt=qcow2 size=4294967296 backing_file=/local/x2003239/mcc2020-input.qcow2 encryption=off cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.......................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool smart
Input is ResAllocation-PT-R003C015, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 1
Run identifier is r190-csrt-159033383000668
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 296K
-rw-r--r-- 1 mcc users 3.4K May 14 00:24 CTLCardinality.txt
-rw-r--r-- 1 mcc users 18K May 14 00:24 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K May 13 17:34 CTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 13 17:34 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 12 20:53 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 12 20:53 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K May 14 10:00 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K May 14 10:00 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K May 14 10:00 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 14 10:00 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K May 13 13:04 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K May 13 13:04 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.4K May 13 07:33 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 23K May 13 07:33 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K May 13 16:53 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 13 16:53 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 12 20:53 equiv_col
-rw-r--r-- 1 mcc users 9 May 12 20:53 instance
-rw-r--r-- 1 mcc users 6 May 12 20:53 iscolored
-rw-r--r-- 1 mcc users 107K May 12 20:53 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-00
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-01
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-02
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-03
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-04
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-05
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-06
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-07
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-08
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-09
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-10
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-11
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-12
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-13
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-14
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1590409469441

======================================================
========== this is Smart for the MCC'2018 ============
======================================================
Running ResAllocation (PT), instance R003C015
Examination CTLFireability
Parser /home/mcc/BenchKit/bin/parser/CTLFire.jar
Model checker /home/mcc/BenchKit/bin/rem_exec/smart

GOT IT HERE. BS
Petri model created: 90 places, 60 transitions, 264 arcs.
AT ITER 0 NEW BEST:: SOT 3002 SOS 441 HAS SOPS 441 HAS SOUS 441 HAS SOUPS 441 WITH SCORE 441.441
AT ITER 874 NEW BEST:: SOT 3002 SOS 439 HAS SOPS 439 HAS SOUS 439 HAS SOUPS 439 WITH SCORE 439.439
AT ITER 1040 NEW BEST:: SOT 3002 SOS 437 HAS SOPS 437 HAS SOUS 437 HAS SOUPS 437 WITH SCORE 437.437
AT ITER 1177 NEW BEST:: SOT 3004 SOS 435 HAS SOPS 435 HAS SOUS 435 HAS SOUPS 435 WITH SCORE 435.435
AT ITER 2005 NEW BEST:: SOT 3004 SOS 434 HAS SOPS 434 HAS SOUS 434 HAS SOUPS 434 WITH SCORE 434.434
Bounds file is: CTLFireability.xml
PROPERTY: ResAllocation-PT-R003C015-CTLFireability-00 (EF( ( (AG( ((potential((tk(P42)>=1) & (tk(P48)>=1)))))) & (! (! ((potential((tk(P2)>=1)))))) )))
PROPERTY: ResAllocation-PT-R003C015-CTLFireability-01 (AF( (EG( ( ( ((potential((tk(P65)>=1)))) & ((potential((tk(P44)>=1) & (tk(P50)>=1)))) ) | ( ((potential((tk(P43)>=1)))) | ((potential((tk(P36)>=1) & (tk(P39)>=1) & (tk(P42)>=1)))) ) )))))
PROPERTY: ResAllocation-PT-R003C015-CTLFireability-02 ( (EF( ( (EG( ((potential((tk(P78)>=1) & (tk(P84)>=1)))))) & (AF( ((potential((tk(P60)>=1) & (tk(P63)>=1) & (tk(P66)>=1)))))) ))) | (AX( (EX( ( ((potential((tk(P79)>=1)))) & ((potential((tk(P67)>=1)))) ))))) )
PROPERTY: ResAllocation-PT-R003C015-CTLFireability-03 (EU( ( ( (! ((potential((tk(P12)>=1) & (tk(P15)>=1) & (tk(P18)>=1))))) & ( ((potential((tk(P54)>=1) & (tk(P60)>=1)))) & ((potential((tk(P66)>=1) & (tk(P72)>=1)))) ) ) | ( (! ((potential((tk(P82)>=1) & (tk(P85)>=1) & (tk(P88)>=1))))) | ( ((potential((tk(P58)>=1) & (tk(P61)>=1) & (tk(P64)>=1)))) | ((potential((tk(P52)>=1) & (tk(P58)>=1) & (tk(P59)>=1)))) ) ) ) , ( ((potential((tk(P62)>=1) & (tk(P68)>=1) & (tk(P69)>=1)))) & ( ( ((potential((tk(P58)>=1) & (tk(P61)>=1) & (tk(P64)>=1)))) & ((potential((tk(P14)>=1) & (tk(P20)>=1) & (tk(P21)>=1)))) ) & ( ((potential((tk(P44)>=1) & (tk(P50)>=1)))) | ((potential((tk(P40)>=1) & (tk(P46)>=1) & (tk(P47)>=1)))) ) ) ) ))
PROPERTY: ResAllocation-PT-R003C015-CTLFireability-04 (EG( ( (! (AG( ((potential((tk(P77)>=1))))))) & ( ( ( ((potential((tk(P8)>=1) & (tk(P14)>=1)))) | ((potential((tk(P70)>=1) & (tk(P73)>=1) & (tk(P76)>=1)))) ) & (! ((potential((tk(P34)>=1) & (tk(P37)>=1) & (tk(P40)>=1))))) ) | (EG( ((potential((tk(P34)>=1) & (tk(P37)>=1) & (tk(P40)>=1)))))) ) )))
PROPERTY: ResAllocation-PT-R003C015-CTLFireability-05 ( (! ( (AF( ((potential((tk(P62)>=1) & (tk(P68)>=1) & (tk(P69)>=1)))))) | ( ( (! ((potential((tk(P17)>=1))))) & ( ((potential((tk(P16)>=1) & (tk(P22)>=1) & (tk(P23)>=1)))) & ((potential((tk(P24)>=1) & (tk(P27)>=1) & (tk(P30)>=1)))) ) ) | (EX( ((potential((tk(P78)>=1) & (tk(P84)>=1)))))) ) )) | (AG( (AF( ( ((potential((tk(P8)>=1) & (tk(P14)>=1)))) | ((potential((tk(P56)>=1) & (tk(P62)>=1)))) ))))) )
PROPERTY: ResAllocation-PT-R003C015-CTLFireability-06 (EU( ( ( (! ((potential((tk(P8)>=1) & (tk(P14)>=1))))) & ((potential((tk(P60)>=1) & (tk(P63)>=1) & (tk(P66)>=1)))) ) | ( ((potential((tk(P68)>=1) & (tk(P74)>=1)))) | ((potential((tk(P34)>=1) & (tk(P37)>=1) & (tk(P40)>=1)))) ) ) , (AX( ( ((potential((tk(P46)>=1) & (tk(P49)>=1) & (tk(P52)>=1)))) & ((potential((tk(P79)>=1)))) ))) ))
PROPERTY: ResAllocation-PT-R003C015-CTLFireability-07 (EF( (EX( ( ( ((potential((tk(P40)>=1) & (tk(P46)>=1) & (tk(P47)>=1)))) & ((potential((tk(P40)>=1) & (tk(P46)>=1) & (tk(P47)>=1)))) ) & ( ((potential((tk(P77)>=1)))) & ((potential((tk(P30)>=1) & (tk(P36)>=1)))) ) )))))
PROPERTY: ResAllocation-PT-R003C015-CTLFireability-08 ( (AX( (AX( (! ((potential((tk(P53)>=1))))))))) & (EX( (EF( ( ((potential((tk(P70)>=1) & (tk(P73)>=1) & (tk(P76)>=1)))) & ((potential((tk(P31)>=1)))) ))))) )
PROPERTY: ResAllocation-PT-R003C015-CTLFireability-09 (EU( (! (AX( ((potential((tk(P67)>=1))))))) , ( (! (! ((potential((tk(P1)>=1) & (tk(P4)>=1)))))) & (AG( ((potential((tk(P82)>=1) & (tk(P85)>=1) & (tk(P88)>=1)))))) ) ))
PROPERTY: ResAllocation-PT-R003C015-CTLFireability-10 (EF( (AG( ( ( ((potential((tk(P5)>=1)))) & ((potential((tk(P46)>=1) & (tk(P49)>=1) & (tk(P52)>=1)))) ) & ((potential((tk(P22)>=1) & (tk(P25)>=1) & (tk(P28)>=1)))) )))))
PROPERTY: ResAllocation-PT-R003C015-CTLFireability-11 (! (EF( ( ( ( ((potential((tk(P65)>=1)))) & ((potential((tk(P65)>=1)))) ) & (! ((potential((tk(P7)>=1))))) ) & (EG( ((potential((tk(P50)>=1) & (tk(P56)>=1) & (tk(P57)>=1)))))) ))))
PROPERTY: ResAllocation-PT-R003C015-CTLFireability-12 (AG( (! (AX( ((potential((tk(P20)>=1) & (tk(P26)>=1)))))))))
PROPERTY: ResAllocation-PT-R003C015-CTLFireability-13 (AG( (EX( (EF( ((potential((tk(P48)>=1) & (tk(P51)>=1) & (tk(P54)>=1))))))))))
PROPERTY: ResAllocation-PT-R003C015-CTLFireability-14 ((potential((tk(P76)>=1) & (tk(P82)>=1) & (tk(P83)>=1))))
PROPERTY: ResAllocation-PT-R003C015-CTLFireability-15 (AU( (! (AX( ((potential((tk(P53)>=1))))))) , ((potential((tk(P1)>=1) & (tk(P4)>=1)))) ))
FORMULA ResAllocation-PT-R003C015-CTLFireability-00 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA ResAllocation-PT-R003C015-CTLFireability-01 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResAllocation-PT-R003C015"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="smart"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool smart"
echo " Input is ResAllocation-PT-R003C015, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 1"
echo " Run identifier is r190-csrt-159033383000668"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ResAllocation-PT-R003C015.tgz
mv ResAllocation-PT-R003C015 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;