Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/local/x2003239/mcc2020-input.r190-csrt-159033382100028.qcow2', fmt=qcow2 size=4294967296 backing_file=/local/x2003239/mcc2020-input.qcow2 encryption=off cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.....................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool smart
Input is SmallOperatingSystem-PT-MT0064DC0016, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 1
Run identifier is r190-csrt-159033382100028
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 200K
-rw-r--r-- 1 mcc users 4.7K Apr 12 17:45 CTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Apr 12 17:45 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Apr 11 20:02 CTLFireability.txt
-rw-r--r-- 1 mcc users 13K Apr 11 20:02 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 24 05:38 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Mar 24 05:38 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Apr 14 12:52 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Apr 28 14:02 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Apr 14 12:52 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 28 14:02 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K Apr 10 20:33 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 14K Apr 10 20:33 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 4.0K Apr 10 05:23 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 22K Apr 10 05:23 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Apr 10 22:29 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Apr 10 22:29 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 24 05:38 equiv_col
-rw-r--r-- 1 mcc users 13 Mar 24 05:38 instance
-rw-r--r-- 1 mcc users 6 Mar 24 05:38 iscolored
-rw-r--r-- 1 mcc users 8.2K Mar 24 05:38 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-00
FORMULA_NAME SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-01
FORMULA_NAME SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-02
FORMULA_NAME SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-03
FORMULA_NAME SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-04
FORMULA_NAME SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-05
FORMULA_NAME SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-06
FORMULA_NAME SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-07
FORMULA_NAME SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-08
FORMULA_NAME SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-09
FORMULA_NAME SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-10
FORMULA_NAME SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-11
FORMULA_NAME SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-12
FORMULA_NAME SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-13
FORMULA_NAME SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-14
FORMULA_NAME SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1590405206484

======================================================
========== this is Smart for the MCC'2018 ============
======================================================
Running SmallOperatingSystem (PT), instance MT0064DC0016
Examination CTLFireability
Parser /home/mcc/BenchKit/bin/parser/CTLFire.jar
Model checker /home/mcc/BenchKit/bin/rem_exec/smart

GOT IT HERE. BS
Petri model created: 9 places, 8 transitions, 27 arcs.
AT ITER 0 NEW BEST:: SOT 52 SOS 34 HAS SOPS 34 HAS SOUS 33 HAS SOUPS 33 WITH SCORE 33.034
AT ITER 9 NEW BEST:: SOT 50 SOS 36 HAS SOPS 36 HAS SOUS 32 HAS SOUPS 32 WITH SCORE 32.036
AT ITER 12 NEW BEST:: SOT 50 SOS 35 HAS SOPS 35 HAS SOUS 30 HAS SOUPS 30 WITH SCORE 30.035
AT ITER 60 NEW BEST:: SOT 49 SOS 34 HAS SOPS 34 HAS SOUS 29 HAS SOUPS 29 WITH SCORE 29.034
AT ITER 74 NEW BEST:: SOT 49 SOS 34 HAS SOPS 34 HAS SOUS 28 HAS SOUPS 28 WITH SCORE 28.034
Bounds file is: CTLFireability.xml
PROPERTY: SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-00 (AG( (EF( (AX( ((potential((tk(P4)>=1))))))))))
PROPERTY: SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-01 (! (AG( (! (AG( ((potential((tk(P6)>=1) & (tk(P3)>=1) & (tk(P1)>=1))))))))))
PROPERTY: SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-02 (EF( (AG( ((potential((tk(P4)>=1))))))))
PROPERTY: SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-03 ((potential((tk(P9)>=1))))
PROPERTY: SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-04 ((potential((tk(P9)>=1))))
PROPERTY: SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-05 (! ( ((potential((tk(P4)>=1)))) & ((potential((tk(P7)>=1) & (tk(P6)>=1)))) ))
PROPERTY: SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-06 (! (AG( ( ( ( ((potential((tk(P1)>=1) & (tk(P2)>=1) & (tk(P3)>=1)))) & ((potential((tk(P5)>=1) & (tk(P7)>=1)))) ) | ( ((potential((tk(P6)>=1) & (tk(P3)>=1) & (tk(P1)>=1)))) & ((potential((tk(P5)>=1)))) ) ) & (EG( ((potential((tk(P5)>=1)))))) ))))
PROPERTY: SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-07 (EG( (EX( ( (! ((potential((tk(P1)>=1) & (tk(P2)>=1) & (tk(P3)>=1))))) & ( ((potential((tk(P5)>=1) & (tk(P7)>=1)))) & ((potential((tk(P7)>=1) & (tk(P6)>=1)))) ) )))))
PROPERTY: SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-08 (AF( (EU( ( ((potential((tk(P5)>=1)))) | ((potential((tk(P1)>=1) & (tk(P2)>=1) & (tk(P3)>=1)))) ) , ( ((potential((tk(P5)>=1) & (tk(P7)>=1)))) & ((potential((tk(P8)>=1)))) ) ))))
PROPERTY: SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-09 (AX( ((potential((tk(P4)>=1))))))
PROPERTY: SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-10 ( (! ((potential((tk(P6)>=1) & (tk(P3)>=1) & (tk(P1)>=1))))) & ( (! ( ( ((potential((tk(P5)>=1) & (tk(P7)>=1)))) & ( ((potential((tk(P6)>=1) & (tk(P3)>=1) & (tk(P1)>=1)))) | ((potential((tk(P5)>=1)))) ) ) & (EG( ((potential((tk(P6)>=1) & (tk(P3)>=1) & (tk(P1)>=1)))))) )) | ( ((potential((tk(P1)>=1) & (tk(P2)>=1) & (tk(P3)>=1)))) | (! ( ((potential((tk(P8)>=1)))) & ((potential((tk(P6)>=1) & (tk(P3)>=1) & (tk(P1)>=1)))) )) ) ) )
PROPERTY: SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-11 (EX( ( (AX( ((potential((tk(P6)>=1) & (tk(P3)>=1) & (tk(P1)>=1)))))) | ((potential((tk(P7)>=1) & (tk(P6)>=1)))) )))
PROPERTY: SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-12 ( ( ( ( ( ((potential((tk(P9)>=1)))) | ( ((potential((tk(P8)>=1)))) & ((potential((tk(P7)>=1) & (tk(P6)>=1)))) ) ) & (EG( ((potential((tk(P5)>=1) & (tk(P7)>=1)))))) ) & (AG( (! ((potential((tk(P1)>=1) & (tk(P2)>=1) & (tk(P3)>=1))))))) ) | (AF( ((potential((tk(P8)>=1)))))) ) & (AX( (! (AF( ((potential((tk(P5)>=1))))))))) )
PROPERTY: SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-13 ( (AX( (AU( ((potential((tk(P1)>=1) & (tk(P2)>=1) & (tk(P3)>=1)))) , ((potential((tk(P7)>=1) & (tk(P6)>=1)))) )))) & ((potential((tk(P6)>=1) & (tk(P3)>=1) & (tk(P1)>=1)))) )
PROPERTY: SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-14 (AG( ((potential((tk(P5)>=1))))))
PROPERTY: SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-15 ( (EF( ((potential((tk(P6)>=1) & (tk(P3)>=1) & (tk(P1)>=1)))))) & ( (EF( ( ( ((potential((tk(P5)>=1) & (tk(P7)>=1)))) | ((potential((tk(P5)>=1)))) ) | ( ((potential((tk(P1)>=1) & (tk(P2)>=1) & (tk(P3)>=1)))) & ((potential((tk(P4)>=1)))) ) ))) & (EX( ((potential((tk(P8)>=1)))))) ) )
FORMULA SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-00 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-01 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-02 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-03 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-04 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-05 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-06 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-07 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-08 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-09 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-10 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-11 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-12 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-13 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-14 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA SmallOperatingSystem-PT-MT0064DC0016-CTLFireability-15 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS

BK_STOP 1590405423441

--------------------
content from stderr:

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT0064DC0016"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="smart"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool smart"
echo " Input is SmallOperatingSystem-PT-MT0064DC0016, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 1"
echo " Run identifier is r190-csrt-159033382100028"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT0064DC0016.tgz
mv SmallOperatingSystem-PT-MT0064DC0016 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;