About the Execution of ITS-LoLa for DLCround-PT-11b
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
15756.720 | 3600000.00 | 3644006.00 | 1895.70 | ??TFT?F??F?TTTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2020-input.r180-ebro-158987900400588.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2020-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool itslola
Input is DLCround-PT-11b, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r180-ebro-158987900400588
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.9M
-rw-r--r-- 1 mcc users 3.9K Mar 30 20:21 CTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Mar 30 20:21 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Mar 29 10:28 CTLFireability.txt
-rw-r--r-- 1 mcc users 14K Mar 29 10:28 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 24 05:37 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K Mar 24 05:37 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.3K Apr 8 14:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Apr 28 14:00 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Apr 8 14:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 28 14:00 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K Mar 28 06:05 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 20K Mar 28 06:05 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Mar 27 00:31 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 27 00:31 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 28 14:49 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Mar 28 14:49 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 24 05:37 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 24 05:37 instance
-rw-r--r-- 1 mcc users 6 Mar 24 05:37 iscolored
-rw-r--r-- 1 mcc users 1.7M Mar 24 05:37 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-11b-CTLFireability-00
FORMULA_NAME DLCround-PT-11b-CTLFireability-01
FORMULA_NAME DLCround-PT-11b-CTLFireability-02
FORMULA_NAME DLCround-PT-11b-CTLFireability-03
FORMULA_NAME DLCround-PT-11b-CTLFireability-04
FORMULA_NAME DLCround-PT-11b-CTLFireability-05
FORMULA_NAME DLCround-PT-11b-CTLFireability-06
FORMULA_NAME DLCround-PT-11b-CTLFireability-07
FORMULA_NAME DLCround-PT-11b-CTLFireability-08
FORMULA_NAME DLCround-PT-11b-CTLFireability-09
FORMULA_NAME DLCround-PT-11b-CTLFireability-10
FORMULA_NAME DLCround-PT-11b-CTLFireability-11
FORMULA_NAME DLCround-PT-11b-CTLFireability-12
FORMULA_NAME DLCround-PT-11b-CTLFireability-13
FORMULA_NAME DLCround-PT-11b-CTLFireability-14
FORMULA_NAME DLCround-PT-11b-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1591255856235
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
[2020-06-04 07:30:59] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -timeout, 3600, -rebuildPNML]
[2020-06-04 07:30:59] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2020-06-04 07:31:00] [INFO ] Load time of PNML (sax parser for PT used): 575 ms
[2020-06-04 07:31:00] [INFO ] Transformed 4375 places.
[2020-06-04 07:31:00] [INFO ] Transformed 6991 transitions.
[2020-06-04 07:31:00] [INFO ] Found NUPN structural information;
[2020-06-04 07:31:00] [INFO ] Parsed PT model containing 4375 places and 6991 transitions in 867 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 572 ms.
Incomplete random walk after 100000 steps, including 0 resets, run finished after 1476 ms. (steps per millisecond=67 ) properties seen :[1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1]
// Phase 1: matrix 6991 rows 4375 cols
[2020-06-04 07:31:02] [INFO ] Computed 244 place invariants in 198 ms
[2020-06-04 07:31:05] [INFO ] [Real]Absence check using 244 positive place invariants in 1401 ms returned sat
[2020-06-04 07:31:05] [INFO ] [Real]Adding state equation constraints to refine reachable states.
[2020-06-04 07:31:23] [INFO ] [Real]Absence check using state equation in 17605 ms returned (error "Solver has unexpectedly terminated")
[2020-06-04 07:31:25] [INFO ] [Real]Absence check using 244 positive place invariants in 1444 ms returned sat
[2020-06-04 07:31:25] [INFO ] [Real]Adding state equation constraints to refine reachable states.
[2020-06-04 07:31:43] [INFO ] SMT solver returned unknown. Retrying;
[2020-06-04 07:31:43] [INFO ] [Real]Absence check using state equation in 17674 ms returned unknown
[2020-06-04 07:31:46] [INFO ] [Real]Absence check using 244 positive place invariants in 1626 ms returned sat
[2020-06-04 07:31:46] [INFO ] [Real]Adding state equation constraints to refine reachable states.
[2020-06-04 07:32:03] [INFO ] SMT solver returned unknown. Retrying;
[2020-06-04 07:32:03] [INFO ] [Real]Absence check using state equation in 16895 ms returned (error "Failed to check-sat")
[2020-06-04 07:32:04] [INFO ] Flatten gal took : 938 ms
[2020-06-04 07:32:05] [INFO ] Flatten gal took : 443 ms
[2020-06-04 07:32:05] [INFO ] Export to MCC properties in file /home/mcc/execution/CTLFireability.sr.xml took 8 ms.
[2020-06-04 07:32:05] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml took 126 ms.
info: Time: 3600 - MCC
vrfy: Checking CTLFireability @ DLCround-PT-11b @ 3570 seconds
FORMULA DLCround-PT-11b-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-11b-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-11b-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-11b-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-11b-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-11b-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-11b-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-11b-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-11b-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-11b-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16427456 kB
MemFree: 3981484 kB
After kill :
MemTotal: 16427456 kB
MemFree: 4277672 kB
--------------------
content from stderr:
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-11b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="itslola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool itslola"
echo " Input is DLCround-PT-11b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r180-ebro-158987900400588"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-11b.tgz
mv DLCround-PT-11b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;