Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fko/mcc2020-input.r153-oct2-158972909600012.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fko/mcc2020-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool smart
Input is RefineWMG-PT-002003, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 1
Run identifier is r153-oct2-158972909600012
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 184K
-rw-r--r-- 1 mcc users 3.2K Apr 12 10:51 CTLCardinality.txt
-rw-r--r-- 1 mcc users 18K Apr 12 10:51 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Apr 11 11:56 CTLFireability.txt
-rw-r--r-- 1 mcc users 15K Apr 11 11:56 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 24 05:38 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.8K Mar 24 05:38 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.2K Apr 14 12:48 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Apr 28 14:02 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9K Apr 14 12:48 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 28 14:02 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.9K Apr 10 16:31 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 23K Apr 10 16:31 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 9 22:55 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 9 22:55 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.4K Apr 10 22:28 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.4K Apr 10 22:28 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 24 05:38 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 24 05:38 instance
-rw-r--r-- 1 mcc users 6 Mar 24 05:38 iscolored
-rw-r--r-- 1 mcc users 6.8K Mar 24 05:38 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME n0-CTLFireability-00
FORMULA_NAME n0-CTLFireability-01
FORMULA_NAME n0-CTLFireability-02
FORMULA_NAME n0-CTLFireability-03
FORMULA_NAME n0-CTLFireability-04
FORMULA_NAME n0-CTLFireability-05
FORMULA_NAME n0-CTLFireability-06
FORMULA_NAME n0-CTLFireability-07
FORMULA_NAME n0-CTLFireability-08
FORMULA_NAME n0-CTLFireability-09
FORMULA_NAME n0-CTLFireability-10
FORMULA_NAME n0-CTLFireability-11
FORMULA_NAME n0-CTLFireability-12
FORMULA_NAME n0-CTLFireability-13
FORMULA_NAME n0-CTLFireability-14
FORMULA_NAME n0-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1589740468050

======================================================
========== this is Smart for the MCC'2018 ============
======================================================
Running RefineWMG (PT), instance 002003
Examination CTLFireability
Parser /home/mcc/BenchKit/bin/parser/CTLFire.jar
Model checker /home/mcc/BenchKit/bin/rem_exec/smart

GOT IT HERE. BS
Petri model created: 14 places, 11 transitions, 32 arcs.
AT ITER 0 NEW BEST:: SOT 94 SOS 49 HAS SOPS 49 HAS SOUS 45 HAS SOUPS 45 WITH SCORE 45.049
AT ITER 26 NEW BEST:: SOT 94 SOS 48 HAS SOPS 48 HAS SOUS 44 HAS SOUPS 44 WITH SCORE 44.048
AT ITER 50 NEW BEST:: SOT 92 SOS 44 HAS SOPS 44 HAS SOUS 40 HAS SOUPS 40 WITH SCORE 40.044
AT ITER 53 NEW BEST:: SOT 91 SOS 42 HAS SOPS 42 HAS SOUS 38 HAS SOUPS 38 WITH SCORE 38.042
AT ITER 62 NEW BEST:: SOT 91 SOS 40 HAS SOPS 40 HAS SOUS 38 HAS SOUPS 38 WITH SCORE 38.04
AT ITER 76 NEW BEST:: SOT 90 SOS 38 HAS SOPS 38 HAS SOUS 36 HAS SOUPS 36 WITH SCORE 36.038
Bounds file is: CTLFireability.xml
PROPERTY: n0-CTLFireability-00 (EF( (AG( ( ((potential((tk(P11)>=1)))) | ( ((potential((tk(P5)>=5)))) | ((potential((tk(P13)>=1)))) ) )))))
PROPERTY: n0-CTLFireability-01 ( (EF( ( ( ( ((potential((tk(P14)>=1)))) | ((potential((tk(P9)>=1)))) ) & (! ((potential((tk(P11)>=1))))) ) & (! ( ((potential((tk(P11)>=1)))) & ((potential((tk(P12)>=1) & (tk(P13)>=1) & (tk(P1)>=1)))) )) ))) & (EF( ( (AX( ((potential((tk(P14)>=1)))))) & (AG( ((potential((tk(P5)>=5)))))) ))) )
PROPERTY: n0-CTLFireability-02 (EF( (AG( ( (! ((potential((tk(P13)>=1))))) | ( ((potential((tk(P4)>=3)))) | ((potential((tk(P9)>=1)))) ) )))))
PROPERTY: n0-CTLFireability-03 (AG( (! (! (EF( ((potential((tk(P11)>=1))))))))))
PROPERTY: n0-CTLFireability-04 (AG( (! (AG( (! ((potential((tk(P7)>=1) & (tk(P8)>=1) & (tk(P10)>=1))))))))))
PROPERTY: n0-CTLFireability-05 ( (! (AF( (EG( ((potential((tk(P14)>=1))))))))) & (EF( (! (EF( ((potential((tk(P13)>=1))))))))) )
PROPERTY: n0-CTLFireability-06 (AU( (! ( (! ((potential((tk(P3)>=2) & (tk(P2)>=2))))) & ( ((potential((tk(P7)>=1) & (tk(P8)>=1) & (tk(P10)>=1)))) | ((potential((tk(P13)>=1)))) ) )) , ( (! ( ((potential((tk(P4)>=3)))) & ((potential((tk(P9)>=1)))) )) & (AF( ((potential((tk(P9)>=1)))))) ) ))
PROPERTY: n0-CTLFireability-07 (AG( ( ( ( ( ((potential((tk(P12)>=1) & (tk(P13)>=1) & (tk(P1)>=1)))) & ((potential((tk(P13)>=1)))) ) | (! ((potential((tk(P8)>=1))))) ) | (AX( ((potential((tk(P7)>=1) & (tk(P8)>=1) & (tk(P10)>=1)))))) ) | (! ((potential((tk(P11)>=1))))) )))
PROPERTY: n0-CTLFireability-08 (EX( ((potential((tk(P6)>=1))))))
PROPERTY: n0-CTLFireability-09 (AU( ( (EF( ((potential((tk(P12)>=1) & (tk(P13)>=1) & (tk(P1)>=1)))))) | ((potential((tk(P11)>=1)))) ) , ( ( ( ((potential((tk(P3)>=2) & (tk(P2)>=2)))) & ((potential((tk(P9)>=1)))) ) | ( ((potential((tk(P5)>=5)))) | ((potential((tk(P5)>=5)))) ) ) & ((potential((tk(P12)>=1) & (tk(P13)>=1) & (tk(P1)>=1)))) ) ))
PROPERTY: n0-CTLFireability-10 (AF( ( ( ( (! ((potential((tk(P11)>=1))))) | ( ((potential((tk(P9)>=1)))) | ((potential((tk(P7)>=1) & (tk(P8)>=1) & (tk(P10)>=1)))) ) ) | ( ((potential((tk(P4)>=3)))) & ((potential((tk(P14)>=1)))) ) ) | ((potential((tk(P9)>=1)))) )))
PROPERTY: n0-CTLFireability-11 (AX( (! (EF( (! ((potential((tk(P5)>=5))))))))))
PROPERTY: n0-CTLFireability-12 (AG( ((potential((tk(P12)>=1) & (tk(P13)>=1) & (tk(P1)>=1))))))
PROPERTY: n0-CTLFireability-13 (! ( (! (! ( (! ((potential((tk(P13)>=1))))) | ((potential((tk(P8)>=1)))) ))) & ((potential((tk(P7)>=1) & (tk(P8)>=1) & (tk(P10)>=1)))) ))
PROPERTY: n0-CTLFireability-14 ( ( ( (EF( ( ((potential((tk(P6)>=1)))) | ((potential((tk(P8)>=1)))) ))) | (AU( ((potential((tk(P4)>=3)))) , ((potential((tk(P11)>=1)))) )) ) | (AF( (EX( ((potential((tk(P13)>=1)))))))) ) & ( ((potential((tk(P6)>=1)))) & ( (! ( ( ((potential((tk(P3)>=2) & (tk(P2)>=2)))) | ((potential((tk(P13)>=1)))) ) | ( ((potential((tk(P5)>=5)))) | ((potential((tk(P8)>=1)))) ) )) & ((potential((tk(P11)>=1)))) ) ) )
PROPERTY: n0-CTLFireability-15 ((potential((tk(P5)>=5))))
FORMULA n0-CTLFireability-00 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA n0-CTLFireability-01 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA n0-CTLFireability-02 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA n0-CTLFireability-03 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA n0-CTLFireability-04 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA n0-CTLFireability-05 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA n0-CTLFireability-06 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA n0-CTLFireability-07 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA n0-CTLFireability-08 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA n0-CTLFireability-09 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA n0-CTLFireability-10 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA n0-CTLFireability-11 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA n0-CTLFireability-12 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA n0-CTLFireability-13 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA n0-CTLFireability-14 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS
FORMULA n0-CTLFireability-15 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS

BK_STOP 1589740469999

--------------------
content from stderr:

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RefineWMG-PT-002003"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="smart"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool smart"
echo " Input is RefineWMG-PT-002003, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 1"
echo " Run identifier is r153-oct2-158972909600012"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RefineWMG-PT-002003.tgz
mv RefineWMG-PT-002003 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;