Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/local/x2003239/mcc2020-input.r111-csrt-158961257700505.qcow2', fmt=qcow2 size=4294967296 backing_file=/local/x2003239/mcc2020-input.qcow2 encryption=off cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool itstools
Input is ParamProductionCell-PT-5, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r111-csrt-158961257700505
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 372K
-rw-r--r-- 1 mcc users 4.1K Apr 13 14:04 CTLCardinality.txt
-rw-r--r-- 1 mcc users 19K Apr 13 14:04 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Apr 13 14:03 CTLFireability.txt
-rw-r--r-- 1 mcc users 14K Apr 13 14:03 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 24 05:37 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.8K Mar 24 05:37 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.2K Apr 13 12:53 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 28 14:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Apr 13 12:53 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 28 14:01 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.4K Apr 13 14:01 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 21K Apr 13 14:01 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.5K Apr 13 14:00 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 13 14:00 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Apr 13 14:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 13 14:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 24 05:37 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 24 05:37 instance
-rw-r--r-- 1 mcc users 6 Mar 24 05:37 iscolored
-rw-r--r-- 1 mcc users 174K Mar 24 05:37 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ParamProductionCell-PT-5-00
FORMULA_NAME ParamProductionCell-PT-5-01
FORMULA_NAME ParamProductionCell-PT-5-02
FORMULA_NAME ParamProductionCell-PT-5-03
FORMULA_NAME ParamProductionCell-PT-5-04
FORMULA_NAME ParamProductionCell-PT-5-05
FORMULA_NAME ParamProductionCell-PT-5-06
FORMULA_NAME ParamProductionCell-PT-5-07
FORMULA_NAME ParamProductionCell-PT-5-08
FORMULA_NAME ParamProductionCell-PT-5-09
FORMULA_NAME ParamProductionCell-PT-5-10
FORMULA_NAME ParamProductionCell-PT-5-11
FORMULA_NAME ParamProductionCell-PT-5-12
FORMULA_NAME ParamProductionCell-PT-5-13
FORMULA_NAME ParamProductionCell-PT-5-14
FORMULA_NAME ParamProductionCell-PT-5-15

=== Now, execution of the tool begins

BK_START 1590000624787

[2020-05-20 18:50:26] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -greatspnpath, /home/mcc/BenchKit//greatspn/, -order, META, -manyOrder, -smt, -timeout, 3600]
[2020-05-20 18:50:26] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2020-05-20 18:50:26] [INFO ] Load time of PNML (sax parser for PT used): 90 ms
[2020-05-20 18:50:27] [INFO ] Transformed 231 places.
[2020-05-20 18:50:27] [INFO ] Transformed 202 transitions.
[2020-05-20 18:50:27] [INFO ] Found NUPN structural information;
[2020-05-20 18:50:27] [INFO ] Parsed PT model containing 231 places and 202 transitions in 140 ms.
Parsed 16 properties from file /home/mcc/execution/LTLCardinality.xml in 21 ms.
Working with output stream class java.io.PrintStream
Incomplete random walk after 100000 steps, including 0 resets, run finished after 271 ms. (steps per millisecond=369 ) properties seen :[0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 1]
// Phase 1: matrix 202 rows 231 cols
[2020-05-20 18:50:27] [INFO ] Computed 59 place invariants in 24 ms
[2020-05-20 18:50:27] [INFO ] [Real]Absence check using 35 positive place invariants in 73 ms returned sat
[2020-05-20 18:50:27] [INFO ] [Real]Absence check using 35 positive and 24 generalized place invariants in 43 ms returned sat
[2020-05-20 18:50:27] [INFO ] [Real]Adding state equation constraints to refine reachable states.
[2020-05-20 18:50:28] [INFO ] [Real]Absence check using state equation in 361 ms returned sat
[2020-05-20 18:50:28] [INFO ] Solution in real domain found non-integer solution.
[2020-05-20 18:50:28] [INFO ] [Nat]Absence check using 35 positive place invariants in 19 ms returned unsat
[2020-05-20 18:50:28] [INFO ] [Real]Absence check using 35 positive place invariants in 88 ms returned sat
[2020-05-20 18:50:28] [INFO ] [Real]Absence check using 35 positive and 24 generalized place invariants in 11 ms returned sat
[2020-05-20 18:50:28] [INFO ] [Real]Adding state equation constraints to refine reachable states.
[2020-05-20 18:50:28] [INFO ] [Real]Absence check using state equation in 263 ms returned sat
[2020-05-20 18:50:28] [INFO ] Solution in real domain found non-integer solution.
[2020-05-20 18:50:28] [INFO ] [Nat]Absence check using 35 positive place invariants in 24 ms returned unsat
[2020-05-20 18:50:28] [INFO ] [Real]Absence check using 35 positive place invariants in 25 ms returned sat
[2020-05-20 18:50:28] [INFO ] [Real]Absence check using 35 positive and 24 generalized place invariants in 15 ms returned sat
[2020-05-20 18:50:28] [INFO ] [Real]Adding state equation constraints to refine reachable states.
[2020-05-20 18:50:29] [INFO ] [Real]Absence check using state equation in 536 ms returned sat
[2020-05-20 18:50:29] [INFO ] Solution in real domain found non-integer solution.
[2020-05-20 18:50:29] [INFO ] [Nat]Absence check using 35 positive place invariants in 41 ms returned sat
[2020-05-20 18:50:29] [INFO ] [Nat]Absence check using 35 positive and 24 generalized place invariants in 2 ms returned unsat
[2020-05-20 18:50:29] [INFO ] [Real]Absence check using 35 positive place invariants in 24 ms returned sat
[2020-05-20 18:50:29] [INFO ] [Real]Absence check using 35 positive and 24 generalized place invariants in 15 ms returned sat
[2020-05-20 18:50:29] [INFO ] [Real]Adding state equation constraints to refine reachable states.
[2020-05-20 18:50:30] [INFO ] [Real]Absence check using state equation in 261 ms returned sat
[2020-05-20 18:50:30] [INFO ] Solution in real domain found non-integer solution.
[2020-05-20 18:50:30] [INFO ] [Nat]Absence check using 35 positive place invariants in 43 ms returned unsat
[2020-05-20 18:50:30] [INFO ] [Real]Absence check using 35 positive place invariants in 34 ms returned sat
[2020-05-20 18:50:30] [INFO ] [Real]Absence check using 35 positive and 24 generalized place invariants in 28 ms returned sat
[2020-05-20 18:50:30] [INFO ] [Real]Adding state equation constraints to refine reachable states.
[2020-05-20 18:50:30] [INFO ] [Real]Absence check using state equation in 324 ms returned sat
[2020-05-20 18:50:30] [INFO ] Solution in real domain found non-integer solution.
[2020-05-20 18:50:30] [INFO ] [Nat]Absence check using 35 positive place invariants in 32 ms returned unsat
[2020-05-20 18:50:31] [INFO ] [Real]Absence check using 35 positive place invariants in 32 ms returned sat
[2020-05-20 18:50:31] [INFO ] [Real]Absence check using 35 positive and 24 generalized place invariants in 16 ms returned sat
[2020-05-20 18:50:31] [INFO ] [Real]Adding state equation constraints to refine reachable states.
[2020-05-20 18:50:31] [INFO ] [Real]Absence check using state equation in 224 ms returned sat
[2020-05-20 18:50:31] [INFO ] Solution in real domain found non-integer solution.
[2020-05-20 18:50:31] [INFO ] [Nat]Absence check using 35 positive place invariants in 38 ms returned sat
[2020-05-20 18:50:31] [INFO ] [Nat]Absence check using 35 positive and 24 generalized place invariants in 11 ms returned sat
[2020-05-20 18:50:31] [INFO ] [Nat]Adding state equation constraints to refine reachable states.
[2020-05-20 18:50:31] [INFO ] [Nat]Absence check using state equation in 199 ms returned sat
[2020-05-20 18:50:31] [INFO ] State equation strengthened by 68 read => feed constraints.
[2020-05-20 18:50:31] [INFO ] [Nat]Added 68 Read/Feed constraints in 20 ms returned sat
[2020-05-20 18:50:31] [INFO ] Deduced a trap composed of 10 places in 163 ms
[2020-05-20 18:50:32] [INFO ] Deduced a trap composed of 8 places in 261 ms
[2020-05-20 18:50:32] [INFO ] Deduced a trap composed of 7 places in 63 ms
[2020-05-20 18:50:32] [INFO ] Deduced a trap composed of 10 places in 36 ms
[2020-05-20 18:50:32] [INFO ] Deduced a trap composed of 5 places in 61 ms
[2020-05-20 18:50:32] [INFO ] Deduced a trap composed of 10 places in 71 ms
[2020-05-20 18:50:32] [INFO ] Trap strengthening (SAT) tested/added 7/6 trap constraints in 795 ms
[2020-05-20 18:50:32] [INFO ] Computed and/alt/rep : 197/572/197 causal constraints in 23 ms.
[2020-05-20 18:50:33] [INFO ] Added : 173 causal constraints over 35 iterations in 927 ms. Result :sat
[2020-05-20 18:50:33] [INFO ] Deduced a trap composed of 15 places in 73 ms
[2020-05-20 18:50:33] [INFO ] Deduced a trap composed of 7 places in 60 ms
[2020-05-20 18:50:33] [INFO ] Deduced a trap composed of 21 places in 42 ms
[2020-05-20 18:50:33] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 282 ms
[2020-05-20 18:50:33] [INFO ] [Real]Absence check using 35 positive place invariants in 16 ms returned sat
[2020-05-20 18:50:33] [INFO ] [Real]Absence check using 35 positive and 24 generalized place invariants in 9 ms returned sat
[2020-05-20 18:50:33] [INFO ] [Real]Adding state equation constraints to refine reachable states.
[2020-05-20 18:50:34] [INFO ] [Real]Absence check using state equation in 230 ms returned sat
[2020-05-20 18:50:34] [INFO ] Solution in real domain found non-integer solution.
[2020-05-20 18:50:34] [INFO ] [Nat]Absence check using 35 positive place invariants in 27 ms returned sat
[2020-05-20 18:50:34] [INFO ] [Nat]Absence check using 35 positive and 24 generalized place invariants in 30 ms returned sat
[2020-05-20 18:50:34] [INFO ] [Nat]Adding state equation constraints to refine reachable states.
[2020-05-20 18:50:34] [INFO ] [Nat]Absence check using state equation in 209 ms returned sat
[2020-05-20 18:50:34] [INFO ] [Nat]Added 68 Read/Feed constraints in 13 ms returned sat
[2020-05-20 18:50:34] [INFO ] Deduced a trap composed of 9 places in 94 ms
[2020-05-20 18:50:34] [INFO ] Deduced a trap composed of 5 places in 91 ms
[2020-05-20 18:50:34] [INFO ] Deduced a trap composed of 10 places in 91 ms
[2020-05-20 18:50:34] [INFO ] Deduced a trap composed of 7 places in 61 ms
[2020-05-20 18:50:34] [INFO ] Deduced a trap composed of 5 places in 94 ms
[2020-05-20 18:50:34] [INFO ] Trap strengthening procedure managed to obtain unsat after adding 5 trap constraints in 513 ms
Successfully simplified 6 atomic propositions for a total of 6 simplifications.
[2020-05-20 18:50:35] [INFO ] Initial state reduction rules for CTL removed 13 formulas.
[2020-05-20 18:50:35] [INFO ] Flatten gal took : 162 ms
FORMULA ParamProductionCell-PT-5-15 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ParamProductionCell-PT-5-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ParamProductionCell-PT-5-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ParamProductionCell-PT-5-12 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ParamProductionCell-PT-5-10 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ParamProductionCell-PT-5-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ParamProductionCell-PT-5-08 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ParamProductionCell-PT-5-06 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ParamProductionCell-PT-5-04 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ParamProductionCell-PT-5-03 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ParamProductionCell-PT-5-02 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ParamProductionCell-PT-5-01 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ParamProductionCell-PT-5-00 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2020-05-20 18:50:35] [INFO ] Flatten gal took : 20 ms
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
[2020-05-20 18:50:35] [INFO ] Applying decomposition
[2020-05-20 18:50:35] [INFO ] Flatten gal took : 21 ms
Converted graph to binary with : CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.louvain.binaries_1.0.0.202005100927/bin/convert-linux64, -i, /tmp/graph12620853547030407274.txt, -o, /tmp/graph12620853547030407274.bin, -w, /tmp/graph12620853547030407274.weights], workingDir=null]
[2020-05-20 18:50:36] [INFO ] Input system was already deterministic with 202 transitions.
Built communities with : CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.louvain.binaries_1.0.0.202005100927/bin/louvain-linux64, /tmp/graph12620853547030407274.bin, -l, -1, -v, -w, /tmp/graph12620853547030407274.weights, -q, 0, -e, 0.001], workingDir=null]
[2020-05-20 18:50:36] [INFO ] Decomposing Gal with order
[2020-05-20 18:50:36] [INFO ] Rewriting arrays to variables to allow decomposition.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 202 rows 231 cols
[2020-05-20 18:50:36] [INFO ] Computed 59 place invariants in 26 ms
inv : arm2_storing + arm2_having_swivel_1 + arm2_waiting_for_swivel_2 + A2U_rotated + A2U_in + A2U_rot1_in + A2U_rot2_in + A2U_rot3_in + A2U_rot1_rs + A2U_rot1_run + A2U_rot2_rs + A2U_rot2_run + A2U_rot3_rs + A2U_rot3_run + A2U_extended - arm2_magnet_on + A2U_ext_rs + A2U_ext_run + A2L_out + A2L_loaded + A2L_ret_rs + A2L_ret_run = 0
inv : arm2_magnet_off + arm2_magnet_on = 1
inv : belt1_start - FB_trans_rs - FB_trans_run - FB_deliver_rs - FB_deliver_run = 0
inv : ch_DC_full + ch_CF_full - ch_A1P_free - ch_TA1_free - ch_A2D_free + ch_FT_full + ch_PA2_full - press_ready_for_unloading - PL_in - PL_out - PL_lower_rs - PL_lower_run + table_ready_for_unloading + TU_in + TU_out + table_at_unload_angle + TU_lift_rs + TU_lift_run + TU_rot_rs + TU_rot_run - deposit_belt_empty + feed_belt_occupied + FB_in + FB_at_end + FB_out + FB_trans_rs + FB_trans_run + FB_deliver_rs + FB_deliver_run + arm2_waiting_for_swivel_1 - arm2_waiting_for_swivel_2 - A2U_rotated - A2U_in - A2U_rot1_in - A2U_rot2_in - A2U_rot3_in - A2U_rot1_rs - A2U_rot1_run - A2U_rot2_rs - A2U_rot2_run - A2U_rot3_rs - A2U_rot3_run - A2U_extended + arm2_magnet_on - A2U_ext_rs - A2U_ext_run + A2L_rotated + A2L_in + A2L_rot1_in + A2L_rot2_in + A2L_rot3_in + A2L_rot1_rs + A2L_rot1_run + A2L_rot2_rs + A2L_rot2_run + A2L_rot3_rs + A2L_rot3_run + A2L_extended + A2L_ext_rs + A2L_ext_run - arm1_waiting_for_swivel_2 - A1L_out - A1L_loaded - arm1_magnet_off - A1L_ret_rs - A1L_ret_run - A1U_rotated - A1U_in - A1U_rot1_in - A1U_rot2_in - A1U_rot3_in - A1U_rot1_rs - A1U_rot1_run - A1U_rot2_rs - A1U_rot2_run - A1U_rot3_rs - A1U_rot3_run - A1U_extendet - A1U_ext_rs - A1U_ext_run + crane_mag_on + CU_unloaded + CU_ready_to_transport + CU_out + CU_lift_rs + CU_lift_run + CU_trans_rs + CU_trans_run + CL_in + CL_ready_to_grasp + CL_lower_rs + CL_lower_run = 2
inv : swivel + arm2_having_swivel_2 + arm2_having_swivel_1 + A2U_rotated + A2U_in + A2U_out + A2U_rot1_in + A2U_rot2_in + A2U_rot3_in + A2U_rot1_rs + A2U_rot1_run + A2U_rot2_rs + A2U_rot2_run + A2U_rot3_rs + A2U_rot3_run + A2U_extended + A2U_unloaded + A2U_ext_rs + A2U_ext_run + A2U_ret_rs + A2U_ret_run + A2L_rotated + A2L_in + A2L_out + A2L_rot1_in + A2L_rot2_in + A2L_rot3_in + A2L_rot1_rs + A2L_rot1_run + A2L_rot2_rs + A2L_rot2_run + A2L_rot3_rs + A2L_rot3_run + A2L_extended + A2L_loaded + A2L_ext_rs + A2L_ext_run + A2L_ret_rs + A2L_ret_run + arm1_having_swivel_2 + arm1_having_swivel_1 + A1L_rotated + A1L_in + A1L_out + A1L_rot1_in + A1L_rot2_in + A1L_rot3_in + A1L_rot1_rs + A1L_rot1_run + A1L_rot2_rs + A1L_rot2_run + A1L_rot3_rs + A1L_rot3_run + A1_extended + A1L_loaded + A1L_ext_rs + A1L_ext_run + A1L_ret_rs + A1L_ret_run + A1U_rotated + A1U_out + A1U_in + A1U_rot1_in + A1U_rot2_in + A1U_rot3_in + A1U_rot1_rs + A1U_rot1_run + A1U_rot2_rs + A1U_rot2_run + A1U_rot3_rs + A1U_rot3_run + A1U_extendet + A1U_unloadet + A1U_ext_rs + A1U_ext_run + A1U_ret_rs + A1U_ret_run = 1
inv : arm1_magnet_on + arm1_magnet_off = 1
inv : robot_left - A2U_rot2_rs - A2U_rot2_run - A2L_rot1_rs - A2L_rot1_run - A2L_rot2_rs - A2L_rot2_run - A2L_rot3_rs - A2L_rot3_run - A1L_rot1_rs - A1L_rot1_run - A1L_rot2_rs - A1L_rot2_run - A1L_rot3_rs - A1L_rot3_run - A1U_rot3_rs - A1U_rot3_run = 0
inv : belt2_start - DB_trans_rs - DB_trans_run - DB_deliver_rs - DB_deliver_run = 0
inv : arm1_pick_up_ext + arm1_retract_ext + arm1_release_ext = 1
inv : table_load_angle + table_unload_angle = 1
inv : crane_store_free + crane_mag_on + CU_unloaded + CU_ready_to_transport + CU_out + CU_lift_rs + CU_lift_run + CU_trans_rs + CU_trans_run + CL_in + CL_ready_to_grasp + CL_lower_rs + CL_lower_run = 1
inv : arm2_forward - A2U_ext_rs - A2U_ext_run - A2L_ext_rs - A2L_ext_run = 0
inv : ch_DC_free - ch_CF_full + ch_A1P_free + ch_TA1_free + ch_A2D_free - ch_FT_full - ch_PA2_full + press_ready_for_unloading + PL_in + PL_out + PL_lower_rs + PL_lower_run - table_ready_for_unloading - TU_in - TU_out - table_at_unload_angle - TU_lift_rs - TU_lift_run - TU_rot_rs - TU_rot_run + deposit_belt_empty + DB_in + DB_at_end + DB_out + DB_trans_rs + DB_trans_run + DB_deliver_rs + DB_deliver_run - feed_belt_occupied - FB_in - FB_at_end - FB_out - FB_trans_rs - FB_trans_run - FB_deliver_rs - FB_deliver_run - arm2_waiting_for_swivel_1 + arm2_waiting_for_swivel_2 + A2U_rotated + A2U_in + A2U_rot1_in + A2U_rot2_in + A2U_rot3_in + A2U_rot1_rs + A2U_rot1_run + A2U_rot2_rs + A2U_rot2_run + A2U_rot3_rs + A2U_rot3_run + A2U_extended - arm2_magnet_on + A2U_ext_rs + A2U_ext_run - A2L_rotated - A2L_in - A2L_rot1_in - A2L_rot2_in - A2L_rot3_in - A2L_rot1_rs - A2L_rot1_run - A2L_rot2_rs - A2L_rot2_run - A2L_rot3_rs - A2L_rot3_run - A2L_extended - A2L_ext_rs - A2L_ext_run + arm1_waiting_for_swivel_2 + A1L_out + A1L_loaded + arm1_magnet_off + A1L_ret_rs + A1L_ret_run + A1U_rotated + A1U_in + A1U_rot1_in + A1U_rot2_in + A1U_rot3_in + A1U_rot1_rs + A1U_rot1_run + A1U_rot2_rs + A1U_rot2_run + A1U_rot3_rs + A1U_rot3_run + A1U_extendet + A1U_ext_rs + A1U_ext_run - crane_mag_on - CU_unloaded - CU_ready_to_transport - CU_out - CU_lift_rs - CU_lift_run - CU_trans_rs - CU_trans_run + CL_out + CL_ready_to_transport + CL_loaded + CL_trans_rs + CL_trans_run + CL_lift_rs + CL_lift_run = -1
inv : robot_stop + A2U_rot1_rs + A2U_rot1_run + A2U_rot2_rs + A2U_rot2_run + A2U_rot3_rs + A2U_rot3_run + A2L_rot1_rs + A2L_rot1_run + A2L_rot2_rs + A2L_rot2_run + A2L_rot3_rs + A2L_rot3_run + A1L_rot1_rs + A1L_rot1_run + A1L_rot2_rs + A1L_rot2_run + A1L_rot3_rs + A1L_rot3_run + A1U_rot1_rs + A1U_rot1_run + A1U_rot2_rs + A1U_rot2_run + A1U_rot3_rs + A1U_rot3_run = 1
inv : deposit_belt_idle + deposit_belt_occupied + deposit_belt_empty + DB_in + DB_at_end + DB_out + DB_trans_rs + DB_trans_run + DB_deliver_rs + DB_deliver_run = 1
inv : press_stop + PU_lower_rs + PU_lower_run + forge_rs + forge_run + PL_lower_rs + PL_lower_run = 1
inv : table_ready_for_loading + table_ready_for_unloading + TL_out + TL_in + table_at_load_angle + TL_rot_rs + TL_rot_run + TL_lower_rs + TL_lower_run + TU_in + TU_out + table_at_unload_angle + TU_lift_rs + TU_lift_run + TU_rot_rs + TU_rot_run = 1
inv : crane_storing - crane_mag_on + CU_ready_to_ungrasp + CU_in + CU_lower_rs + CU_lower_run + CL_out + CL_ready_to_transport + CL_loaded + CL_trans_rs + CL_trans_run + CL_lift_rs + CL_lift_run = 0
inv : ch_FT_free + ch_FT_full + table_ready_for_unloading + TL_out + TL_in + table_at_load_angle + TL_rot_rs + TL_rot_run + TL_lower_rs + TL_lower_run + TU_in + TU_out + table_at_unload_angle + TU_lift_rs + TU_lift_run + TU_rot_rs + TU_rot_run + FB_in + FB_at_end + FB_out + FB_trans_rs + FB_trans_run + FB_deliver_rs + FB_deliver_run = 1
inv : arm1_store_free + arm1_waiting_for_swivel_1 + arm1_having_swivel_2 + A1L_rotated + A1L_in + A1L_rot1_in + A1L_rot2_in + A1L_rot3_in + A1L_rot1_rs + A1L_rot1_run + A1L_rot2_rs + A1L_rot2_run + A1L_rot3_rs + A1L_rot3_run + A1_extended - arm1_magnet_off + A1L_ext_rs + A1L_ext_run + A1U_out + A1U_unloadet + A1U_ret_rs + A1U_ret_run = 0
inv : arm1_storing + arm1_having_swivel_1 + arm1_waiting_for_swivel_2 + A1L_out + A1L_loaded + arm1_magnet_off + A1L_ret_rs + A1L_ret_run + A1U_rotated + A1U_in + A1U_rot1_in + A1U_rot2_in + A1U_rot3_in + A1U_rot1_rs + A1U_rot1_run + A1U_rot2_rs + A1U_rot2_run + A1U_rot3_rs + A1U_rot3_run + A1U_extendet + A1U_ext_rs + A1U_ext_run = 1
inv : arm2_release_ext + arm2_retract_ext + arm2_pick_up_ext = 1
inv : press_ready_for_loading + press_ready_for_unloading + PU_out + blank_forged + PU_in + PU_lower_rs + PU_lower_run + forge_rs + forge_run + PL_in + PL_out + PL_lower_rs + PL_lower_run = 1
inv : arm2_backward - A2U_ret_rs - A2U_ret_run - A2L_ret_rs - A2L_ret_run = 0
inv : ch_CF_free + ch_CF_full + feed_belt_occupied + feed_belt_empty + FB_in + FB_at_end + FB_out + FB_trans_rs + FB_trans_run + FB_deliver_rs + FB_deliver_run + CU_unloaded + CU_ready_to_transport + CU_out + CU_ready_to_ungrasp + CU_in + CU_lift_rs + CU_lift_run + CU_trans_rs + CU_trans_run + CU_lower_rs + CU_lower_run = 1
inv : press_at_upper_pos + press_at_lower_pos + press_at_middle_pos = 1
inv : feed_belt_idle + feed_belt_occupied + feed_belt_empty + FB_in + FB_at_end + FB_out + FB_trans_rs + FB_trans_run + FB_deliver_rs + FB_deliver_run = 1
inv : arm2_store_free + arm2_waiting_for_swivel_1 + arm2_having_swivel_2 + A2U_out + A2U_unloaded + arm2_magnet_on + A2U_ret_rs + A2U_ret_run + A2L_rotated + A2L_in + A2L_rot1_in + A2L_rot2_in + A2L_rot3_in + A2L_rot1_rs + A2L_rot1_run + A2L_rot2_rs + A2L_rot2_run + A2L_rot3_rs + A2L_rot3_run + A2L_extended + A2L_ext_rs + A2L_ext_run = 1
inv : table_stop_v + TL_lower_rs + TL_lower_run + TU_lift_rs + TU_lift_run = 1
inv : press_down - PU_lower_rs - PU_lower_run = 0
inv : crane_lower - CU_lower_rs - CU_lower_run - CL_lower_rs - CL_lower_run = 0
inv : ch_TA1_full + ch_TA1_free - table_ready_for_unloading + arm1_waiting_for_swivel_1 + A1L_rotated + A1L_in + A1L_out + A1L_rot1_in + A1L_rot2_in + A1L_rot3_in + A1L_rot1_rs + A1L_rot1_run + A1L_rot2_rs + A1L_rot2_run + A1L_rot3_rs + A1L_rot3_run + A1_extended + A1L_loaded + A1L_ext_rs + A1L_ext_run + A1L_ret_rs + A1L_ret_run = 0
inv : crane_lift - CU_lift_rs - CU_lift_run - CL_lift_rs - CL_lift_run = 0
inv : crane_transport_height + crane_release_height + crane_pick_up_height = 1
inv : table_right - TL_rot_rs - TL_rot_run - TU_rot_rs - TU_rot_run = 0
inv : crane_to_belt2 - CU_trans_rs - CU_trans_run = 0
inv : ch_A1P_full + ch_A1P_free + press_ready_for_unloading + PU_out + blank_forged + PU_in + PU_lower_rs + PU_lower_run + forge_rs + forge_run + PL_in + PL_out + PL_lower_rs + PL_lower_run + arm1_waiting_for_swivel_2 + A1U_rotated + A1U_out + A1U_in + A1U_rot1_in + A1U_rot2_in + A1U_rot3_in + A1U_rot1_rs + A1U_rot1_run + A1U_rot2_rs + A1U_rot2_run + A1U_rot3_rs + A1U_rot3_run + A1U_extendet + A1U_unloadet + A1U_ext_rs + A1U_ext_run + A1U_ret_rs + A1U_ret_run = 1
inv : press_upward - forge_rs - forge_run = 0
inv : belt2_light_barrier_true + belt2_light_barrier_false = 1
inv : ch_A2D_full + ch_A2D_free + deposit_belt_occupied + deposit_belt_empty + DB_in + DB_at_end + DB_out + DB_trans_rs + DB_trans_run + DB_deliver_rs + DB_deliver_run + arm2_waiting_for_swivel_2 + A2U_rotated + A2U_in + A2U_out + A2U_rot1_in + A2U_rot2_in + A2U_rot3_in + A2U_rot1_rs + A2U_rot1_run + A2U_rot2_rs + A2U_rot2_run + A2U_rot3_rs + A2U_rot3_run + A2U_extended + A2U_unloaded + A2U_ext_rs + A2U_ext_run + A2U_ret_rs + A2U_ret_run = 1
inv : crane_stop_h + CU_trans_rs + CU_trans_run + CL_trans_rs + CL_trans_run = 1
inv : crane_stop_v + CU_lift_rs + CU_lift_run + CU_lower_rs + CU_lower_run + CL_lower_rs + CL_lower_run + CL_lift_rs + CL_lift_run = 1
inv : belt2_stop + DB_trans_rs + DB_trans_run + DB_deliver_rs + DB_deliver_run = 1
inv : crane_mag_off + crane_mag_on = 1
inv : robot_right - A2U_rot1_rs - A2U_rot1_run - A2U_rot3_rs - A2U_rot3_run - A1U_rot1_rs - A1U_rot1_run - A1U_rot2_rs - A1U_rot2_run = 0
inv : press_up - PL_lower_rs - PL_lower_run = 0
inv : belt1_stop + FB_trans_rs + FB_trans_run + FB_deliver_rs + FB_deliver_run = 1
inv : arm1_backward - A1L_ret_rs - A1L_ret_run - A1U_ret_rs - A1U_ret_run = 0
inv : ch_PA2_free + ch_PA2_full - press_ready_for_unloading + arm2_waiting_for_swivel_1 + A2L_rotated + A2L_in + A2L_out + A2L_rot1_in + A2L_rot2_in + A2L_rot3_in + A2L_rot1_rs + A2L_rot1_run + A2L_rot2_rs + A2L_rot2_run + A2L_rot3_rs + A2L_rot3_run + A2L_extended + A2L_loaded + A2L_ext_rs + A2L_ext_run + A2L_ret_rs + A2L_ret_run = 0
inv : arm1_forward - A1L_ext_rs - A1L_ext_run - A1U_ext_rs - A1U_ext_run = 0
inv : table_upward - TL_lower_rs - TL_lower_run - TU_lift_rs - TU_lift_run = 0
inv : crane_above_deposit_belt + crane_above_feed_belt = 1
inv : crane_to_belt1 - CL_trans_rs - CL_trans_run = 0
inv : table_bottom_pos + table_top_pos = 1
inv : belt1_light_barrier_true + belt1_light_barrier_false = 1
inv : table_stop_h + TL_rot_rs + TL_rot_run + TU_rot_rs + TU_rot_run = 1
inv : arm1_stop + A1L_ext_rs + A1L_ext_run + A1L_ret_rs + A1L_ret_run + A1U_ext_rs + A1U_ext_run + A1U_ret_rs + A1U_ret_run = 1
inv : arm2_stop + A2U_ext_rs + A2U_ext_run + A2U_ret_rs + A2U_ret_run + A2L_ext_rs + A2L_ext_run + A2L_ret_rs + A2L_ret_run = 1
inv : arm2_release_angle + arm1_pick_up_angle + arm1_release_angle + arm2_pick_up_angle = 1
Total of 59 invariants.
[2020-05-20 18:50:36] [INFO ] Computed 59 place invariants in 28 ms
[2020-05-20 18:50:36] [INFO ] Removed a total of 86 redundant transitions.
[2020-05-20 18:50:37] [INFO ] Flatten gal took : 273 ms
[2020-05-20 18:50:37] [INFO ] Fuse similar labels procedure discarded/fused a total of 0 labels/synchronizations in 21 ms.
[2020-05-20 18:50:37] [INFO ] Time to serialize gal into /home/mcc/execution/LTLCardinality.pnml.gal : 7 ms
[2020-05-20 18:50:37] [INFO ] Time to serialize properties into /home/mcc/execution/LTLCardinality.ltl : 1 ms
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.202005100927/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLCardinality.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLCardinality.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.202005100927/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLCardinality.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLCardinality.ltl -c -stutter-deadlock
Read 3 LTL properties
Checking formula 0 : !((F((G(X("((i1.i0.u20.TU_lift_rs==0)||(i4.i1.u79.CL_trans_rs==1))")))&&("((i7.i2.u2.PL_out==0)||(i3.i2.u6.A2L_out==1))"))))
Formula 0 simplified : !F("((i7.i2.u2.PL_out==0)||(i3.i2.u6.A2L_out==1))" & GX"((i1.i0.u20.TU_lift_rs==0)||(i4.i1.u79.CL_trans_rs==1))")
built 18 ordering constraints for composite.
built 13 ordering constraints for composite.
built 7 ordering constraints for composite.
built 8 ordering constraints for composite.
built 8 ordering constraints for composite.
built 7 ordering constraints for composite.
built 7 ordering constraints for composite.
built 6 ordering constraints for composite.
built 7 ordering constraints for composite.
built 13 ordering constraints for composite.
built 5 ordering constraints for composite.
built 6 ordering constraints for composite.
built 8 ordering constraints for composite.
built 10 ordering constraints for composite.
built 6 ordering constraints for composite.
built 9 ordering constraints for composite.
built 16 ordering constraints for composite.
built 13 ordering constraints for composite.
built 8 ordering constraints for composite.
built 6 ordering constraints for composite.
built 7 ordering constraints for composite.
built 63 ordering constraints for composite.
built 7 ordering constraints for composite.
built 7 ordering constraints for composite.
built 6 ordering constraints for composite.
built 15 ordering constraints for composite.
built 16 ordering constraints for composite.
Reverse transition relation is NOT exact ! Due to transitions forge_Pstart, PL_lower_Pstart, TL_rot_Pstart, TU_rot_Pstart, arm2_unlock_swivel_1, arm2_unlock_swivel_2, A2U_ext_Pstart, A2L_ext_Pstart, A1L_ext_Pstart, A1U_ext_Pstart, CU_lower_Pstart, CL_lower_Pstart, CL_trans_Pstart, i0.PU_lower_Pstart, i1.TL_lower_Pstart, i1.i0.TU_lift_Pstart, i2.FB_trans_Pstart, i2.i2.FB_deliver_Pstart, i4.i1.CU_trans_Pstart, i5.A1U_rot3_Pstart, i5.A1U_rot3_Pstop, i5.A1U_rot2_Pstart, i5.A1U_rot2_Pstop, i5.A1U_rot1_Pstart, i5.A1L_rot3_Pstart, i5.A1L_rot3_Pstop, i5.A1L_rot2_Pstart, i5.A1L_rot2_Pstop, i5.A1L_rot1_Pstart, i5.A1L_rot1_Pstop, i5.A2L_rot3_Pstart, i5.A2L_rot2_Pstart, i5.A2L_rot2_Pstop, i5.A2L_rot1_Pstart, i5.A2L_rot1_Pstop, i5.A2U_rot3_Pstart, i5.A2U_rot3_Pstop, i5.A2U_rot2_Pstart, i5.A2U_rot2_Pstop, i5.A2U_rot1_Pstart, i5.A2U_rot1_Pstop, i6.A2L_ret_Pstart, i6.A2U_ret_Pstart, i7.arm1_unlock_swivel_2, i7.i2.arm1_unlock_swivel_1, i8.A1U_ret_Pstart, i8.A1L_ret_Pstart, i9.DB_trans_Pstart, i9.i0.DB_deliver_Pstart, i10.CL_lift_Pstart, i10.CU_lift_Pstart, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :0/151/51/202
[2020-05-20 18:50:38] [INFO ] Proved 231 variables to be positive in 1970 ms
[2020-05-20 18:50:38] [INFO ] Computing symmetric may disable matrix : 202 transitions.
[2020-05-20 18:50:38] [INFO ] Computation of disable matrix completed :0/202 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
[2020-05-20 18:50:38] [INFO ] Computation of Complete disable matrix. took 22 ms. Total solver calls (SAT/UNSAT): 0(0/0)
[2020-05-20 18:50:38] [INFO ] Computing symmetric may enable matrix : 202 transitions.
[2020-05-20 18:50:38] [INFO ] Computation of Complete enable matrix. took 27 ms. Total solver calls (SAT/UNSAT): 0(0/0)
[2020-05-20 18:50:39] [INFO ] Computing symmetric co enabling matrix : 202 transitions.
[2020-05-20 18:50:43] [INFO ] Computation of co-enabling matrix(2/202) took 3669 ms. Total solver calls (SAT/UNSAT): 236(86/150)
[2020-05-20 18:50:46] [INFO ] Computation of co-enabling matrix(5/202) took 6669 ms. Total solver calls (SAT/UNSAT): 458(194/264)
163 unique states visited
2 strongly connected components in search stack
163 transitions explored
162 items max in DFS search stack
1189 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,11.9727,386408,1,0,850687,516,3750,731545,310,1286,1733223
an accepting run exists (use option '-e' to print it)
Formula 0 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-5-05 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 1 : !((X(X(X(F("((i3.i2.u6.ch_PA2_free==0)||(i0.u9.blank_forged==1))"))))))
Formula 1 simplified : !XXXF"((i3.i2.u6.ch_PA2_free==0)||(i0.u9.blank_forged==1))"
4 unique states visited
0 strongly connected components in search stack
3 transitions explored
4 items max in DFS search stack
1 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,11.9793,386760,1,0,850766,516,3774,731573,311,1286,1733573
no accepting run found
Formula 1 is TRUE no accepting run found.
FORMULA ParamProductionCell-PT-5-07 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 2 : !((F((F("((i1.i1.u14.table_stop_h==0)||(i8.u68.A1U_ret_run==1))"))U((("((i5.u35.A2U_rot3_in!=0)&&(i0.u10.press_at_lower_pos!=1))")U("((i1.i1.u14.table_stop_h==0)||(i8.u68.A1U_ret_run==1))"))||(!(("((i1.i1.u14.table_stop_h==0)||(i8.u68.A1U_ret_run==1))")U("((i9.i1.u70.CU_in==0)||(i0.u10.PU_lower_rs==1))")))))))
Formula 2 simplified : !F(F"((i1.i1.u14.table_stop_h==0)||(i8.u68.A1U_ret_run==1))" U (("((i5.u35.A2U_rot3_in!=0)&&(i0.u10.press_at_lower_pos!=1))" U "((i1.i1.u14.table_stop_h==0)||(i8.u68.A1U_ret_run==1))") | !("((i1.i1.u14.table_stop_h==0)||(i8.u68.A1U_ret_run==1))" U "((i9.i1.u70.CU_in==0)||(i0.u10.PU_lower_rs==1))")))
1 unique states visited
0 strongly connected components in search stack
0 transitions explored
1 items max in DFS search stack
19 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,12.1757,394408,1,0,873128,551,3937,745926,316,1447,1789453
no accepting run found
Formula 2 is TRUE no accepting run found.
FORMULA ParamProductionCell-PT-5-11 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
[2020-05-20 18:50:49] [INFO ] Computation of co-enabling matrix(13/202) took 10081 ms. Total solver calls (SAT/UNSAT): 934(410/524)
Skipping mayMatrices nes/nds SMT solver raised an exception or timeout.
java.lang.RuntimeException: SMT solver raised an exception or timeout.
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.computeCoEnablingMatrix(NecessaryEnablingsolver.java:482)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:530)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:831)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:73)
at java.base/java.lang.Thread.run(Thread.java:834)
[2020-05-20 18:50:52] [INFO ] Built C files in 16066ms conformant to PINS in folder :/home/mcc/execution
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O2, model.c], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1590000652513

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ LTLCardinality = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -greatspnpath /home/mcc/BenchKit//greatspn/ -order META -manyOrder -smt -timeout 3600
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -greatspnpath /home/mcc/BenchKit//greatspn/ -order META -manyOrder -smt -timeout 3600 -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss128m -Xms40m -Xmx16000m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ParamProductionCell-PT-5"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool itstools"
echo " Input is ParamProductionCell-PT-5, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r111-csrt-158961257700505"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ParamProductionCell-PT-5.tgz
mv ParamProductionCell-PT-5 execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;