Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/local/x2003239/mcc2019-input.r184-csrt-155344538100366.qcow2', fmt=qcow2 size=4294967296 backing_file=/local/x2003239/mcc2019-input.qcow2 encryption=off cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................
=====================================================================
Generated by BenchKit 2-3954
Executing tool itstools
Input is NoC3x3-PT-8A, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r184-csrt-155344538100366
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 916K
-rw-r--r-- 1 mcc users 3.1K Mar 23 12:42 CTLCardinality.txt
-rw-r--r-- 1 mcc users 17K Mar 23 12:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Mar 23 12:29 CTLFireability.txt
-rw-r--r-- 1 mcc users 17K Mar 23 12:29 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 23 10:10 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.7K Mar 23 10:10 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.2K Mar 23 12:14 LTLCardinality.txt
-rw-r--r-- 1 mcc users 9.0K Mar 23 12:14 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.8K Mar 23 12:13 LTLFireability.txt
-rw-r--r-- 1 mcc users 9.0K Mar 23 12:13 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Mar 23 10:10 NewModel
-rw-r--r-- 1 mcc users 3.0K Mar 23 12:13 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 15K Mar 23 12:13 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 103 Mar 23 11:58 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 341 Mar 23 11:58 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.8K Mar 23 12:06 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 23 12:06 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Mar 23 12:13 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Mar 23 12:13 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 23 10:10 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 23 10:10 instance
-rw-r--r-- 1 mcc users 6 Mar 23 10:10 iscolored
-rw-r--r-- 1 mcc users 0 Mar 23 10:10 model-fix.log
-rw-r--r-- 1 mcc users 745K Mar 23 10:10 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME NoC3x3-PT-8A-LTLCardinality-00
FORMULA_NAME NoC3x3-PT-8A-LTLCardinality-01
FORMULA_NAME NoC3x3-PT-8A-LTLCardinality-02
FORMULA_NAME NoC3x3-PT-8A-LTLCardinality-03
FORMULA_NAME NoC3x3-PT-8A-LTLCardinality-04
FORMULA_NAME NoC3x3-PT-8A-LTLCardinality-05
FORMULA_NAME NoC3x3-PT-8A-LTLCardinality-06
FORMULA_NAME NoC3x3-PT-8A-LTLCardinality-07
FORMULA_NAME NoC3x3-PT-8A-LTLCardinality-08
FORMULA_NAME NoC3x3-PT-8A-LTLCardinality-09
FORMULA_NAME NoC3x3-PT-8A-LTLCardinality-10
FORMULA_NAME NoC3x3-PT-8A-LTLCardinality-11
FORMULA_NAME NoC3x3-PT-8A-LTLCardinality-12
FORMULA_NAME NoC3x3-PT-8A-LTLCardinality-13
FORMULA_NAME NoC3x3-PT-8A-LTLCardinality-14
FORMULA_NAME NoC3x3-PT-8A-LTLCardinality-15

=== Now, execution of the tool begins

BK_START 1553571046625

Working with output stream class java.io.PrintStream
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903171603/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLCardinality.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLCardinality.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903171603/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLCardinality.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLCardinality.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((X(X(G("((u28.p128==0)||(u7.p32==1))")))))
Formula 0 simplified : !XXG"((u28.p128==0)||(u7.p32==1))"
built 129 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 566
// Phase 1: matrix 566 rows 317 cols
invariant :u49:p238 + u67:p0 = 1
invariant :u43:p209 + u43:p210 + u43:p211 + u43:p212 + u67:p0 = 1
invariant :u48:p231 + u48:p232 + u48:p233 + u48:p234 + u48:p235 + u48:p236 + u48:p237 + u67:p0 = 1
invariant :u27:p122 + u27:p123 + u27:p124 + u27:p125 + u67:p0 = 1
invariant :u33:p165 + u67:p0 = 1
invariant :u8:p34 + u8:p35 + u8:p36 + u8:p37 + u8:p38 + u8:p39 + u8:p40 + u67:p0 = 1
invariant :u37:p178 + u37:p179 + u37:p180 + u37:p181 + u67:p0 = 1
invariant :u18:p79 + u18:p80 + u18:p81 + u18:p82 + u67:p0 = 1
invariant :u55:p266 + u55:p267 + u55:p268 + u55:p269 + u55:p270 + u55:p271 + u55:p272 + u55:p273 + u55:p274 + u67:p0 = 1
invariant :u11:p49 + u11:p50 + u11:p51 + u11:p52 + u67:p0 = 1
invariant :u44:p213 + u44:p214 + u44:p215 + u44:p216 + u67:p0 = 1
invariant :u38:p182 + u38:p183 + u38:p184 + u67:p0 = 1
invariant :u17:p78 + u67:p0 = 1
invariant :u53:p250 + u53:p251 + u53:p252 + u53:p253 + u53:p254 + u53:p255 + u53:p256 + u53:p257 + u53:p258 + u67:p0 = 1
invariant :u63:p305 + u67:p0 = 1
invariant :u2:p6 + u2:p7 + u2:p8 + u2:p9 + u2:p10 + u2:p11 + u2:p12 + u67:p0 = 1
invariant :u6:p22 + u6:p23 + u6:p24 + u67:p0 = 1
invariant :u19:p83 + u19:p84 + u19:p85 + u19:p86 + u67:p0 = 1
invariant :u42:p208 + u67:p0 = 1
invariant :u22:p97 + u22:p98 + u22:p99 + u22:p100 + u22:p101 + u22:p102 + u22:p103 + u22:p104 + u22:p105 + u67:p0 = 1
invariant :u1:p1 + u1:p2 + u1:p3 + u1:p4 + u1:p5 + u67:p0 = 1
invariant :u13:p57 + u13:p58 + u13:p59 + u13:p60 + u67:p0 = 1
invariant :u47:p224 + u47:p225 + u47:p226 + u47:p227 + u47:p228 + u47:p229 + u47:p230 + u67:p0 = 1
invariant :u60:p288 + u60:p289 + u60:p290 + u67:p0 = 1
invariant :u10:p48 + u67:p0 = 1
invariant :u30:p138 + u30:p139 + u30:p140 + u30:p141 + u30:p142 + u30:p143 + u30:p144 + u30:p145 + u30:p146 + u67:p0 = 1
invariant :u57:p276 + u57:p277 + u57:p278 + u57:p279 + u67:p0 = 1
invariant :u64:p306 + u64:p307 + u64:p308 + u64:p309 + u67:p0 = 1
invariant :u66:p314 + u66:p315 + u66:p316 + u67:p0 = 1
invariant :u41:p201 + u41:p202 + u41:p203 + u41:p204 + u41:p205 + u41:p206 + u41:p207 + u67:p0 = 1
invariant :u51:p243 + u51:p244 + u51:p245 + u51:p246 + u67:p0 = 1
invariant :u54:p259 + u54:p260 + u54:p261 + u54:p262 + u54:p263 + u54:p264 + u54:p265 + u67:p0 = 1
invariant :u29:p129 + u29:p130 + u29:p131 + u29:p132 + u29:p133 + u29:p134 + u29:p135 + u29:p136 + u29:p137 + u67:p0 = 1
invariant :u31:p147 + u31:p148 + u31:p149 + u31:p150 + u31:p151 + u31:p152 + u31:p153 + u31:p154 + u31:p155 + u67:p0 = 1
invariant :u45:p217 + u45:p218 + u45:p219 + u45:p220 + u67:p0 = 1
invariant :u36:p174 + u36:p175 + u36:p176 + u36:p177 + u67:p0 = 1
invariant :u59:p284 + u59:p285 + u59:p286 + u59:p287 + u67:p0 = 1
invariant :u58:p280 + u58:p281 + u58:p282 + u58:p283 + u67:p0 = 1
invariant :u4:p14 + u4:p15 + u4:p16 + u4:p17 + u67:p0 = 1
invariant :u24:p113 + u67:p0 = 1
invariant :u26:p118 + u26:p119 + u26:p120 + u26:p121 + u67:p0 = 1
invariant :u15:p64 + u15:p65 + u15:p66 + u15:p67 + u15:p68 + u15:p69 + u15:p70 + u67:p0 = 1
invariant :u9:p41 + u9:p42 + u9:p43 + u9:p44 + u9:p45 + u9:p46 + u9:p47 + u67:p0 = 1
invariant :u28:p126 + u28:p127 + u28:p128 + u67:p0 = 1
invariant :u56:p275 + u67:p0 = 1
invariant :u35:p170 + u35:p171 + u35:p172 + u35:p173 + u67:p0 = 1
invariant :u12:p53 + u12:p54 + u12:p55 + u12:p56 + u67:p0 = 1
invariant :u39:p185 + u39:p186 + u39:p187 + u39:p188 + u39:p189 + u39:p190 + u39:p191 + u67:p0 = 1
invariant :u62:p298 + u62:p299 + u62:p300 + u62:p301 + u62:p302 + u62:p303 + u62:p304 + u67:p0 = 1
invariant :u32:p156 + u32:p157 + u32:p158 + u32:p159 + u32:p160 + u32:p161 + u32:p162 + u32:p163 + u32:p164 + u67:p0 = 1
invariant :u20:p87 + u20:p88 + u20:p89 + u67:p0 = 1
invariant :u14:p61 + u14:p62 + u14:p63 + u67:p0 = 1
invariant :u46:p221 + u46:p222 + u46:p223 + u67:p0 = 1
invariant :u16:p71 + u16:p72 + u16:p73 + u16:p74 + u16:p75 + u16:p76 + u16:p77 + u67:p0 = 1
invariant :u5:p18 + u5:p19 + u5:p20 + u5:p21 + u67:p0 = 1
invariant :u21:p90 + u21:p91 + u21:p92 + u21:p93 + u21:p94 + u21:p95 + u21:p96 + u67:p0 = 1
invariant :u40:p192 + u40:p193 + u40:p194 + u40:p195 + u40:p196 + u40:p197 + u40:p198 + u40:p199 + u40:p200 + u67:p0 = 1
invariant :u25:p114 + u25:p115 + u25:p116 + u25:p117 + u67:p0 = 1
invariant :u52:p247 + u52:p248 + u52:p249 + u67:p0 = 1
invariant :u23:p106 + u23:p107 + u23:p108 + u23:p109 + u23:p110 + u23:p111 + u23:p112 + u67:p0 = 1
invariant :u3:p13 + u67:p0 = 1
invariant :u7:p25 + u7:p26 + u7:p27 + u7:p28 + u7:p29 + u7:p30 + u7:p31 + u7:p32 + u7:p33 + u67:p0 = 1
invariant :u65:p310 + u65:p311 + u65:p312 + u65:p313 + u67:p0 = 1
invariant :u61:p291 + u61:p292 + u61:p293 + u61:p294 + u61:p295 + u61:p296 + u61:p297 + u67:p0 = 1
invariant :u34:p166 + u34:p167 + u34:p168 + u34:p169 + u67:p0 = 1
invariant :u50:p239 + u50:p240 + u50:p241 + u50:p242 + u67:p0 = 1
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O2, model.c], workingDir=/home/mcc/execution]
Compilation finished in 10199 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 128 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X(X([]((LTLAP0==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 7966 ms.
FORMULA NoC3x3-PT-8A-LTLCardinality-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, <>([]((LTLAP1==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 10129 ms.
FORMULA NoC3x3-PT-8A-LTLCardinality-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, false, --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 8455 ms.
FORMULA NoC3x3-PT-8A-LTLCardinality-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, true, --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 6842 ms.
FORMULA NoC3x3-PT-8A-LTLCardinality-03 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, [](<>([]([]((LTLAP2==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, [](<>([]([]((LTLAP2==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, ((LTLAP3==true))U((LTLAP4==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 10070 ms.
FORMULA NoC3x3-PT-8A-LTLCardinality-05 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, false, --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 10553 ms.
FORMULA NoC3x3-PT-8A-LTLCardinality-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X(<>((LTLAP5==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 3369 ms.
FORMULA NoC3x3-PT-8A-LTLCardinality-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, []((LTLAP6==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 138192 ms.
FORMULA NoC3x3-PT-8A-LTLCardinality-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, true, --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 9862 ms.
FORMULA NoC3x3-PT-8A-LTLCardinality-09 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, true, --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 12453 ms.
FORMULA NoC3x3-PT-8A-LTLCardinality-10 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, <>(X(((LTLAP7==true))U((LTLAP8==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 3105 ms.
FORMULA NoC3x3-PT-8A-LTLCardinality-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, true, --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 10370 ms.
FORMULA NoC3x3-PT-8A-LTLCardinality-12 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, <>([]((LTLAP9==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, <>([]((LTLAP9==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, (((LTLAP10==true))U((LTLAP11==true)))U(((LTLAP12==true))U((LTLAP13==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 10240 ms.
FORMULA NoC3x3-PT-8A-LTLCardinality-14 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, <>((LTLAP14==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 9681 ms.
FORMULA NoC3x3-PT-8A-LTLCardinality-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Retrying LTSmin with larger timeout 1800 s
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, [](<>([]([]((LTLAP2==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Reverse transition relation is NOT exact ! Due to transitions u4.t3523, u4.t3524, u4.t3525, u4.t3526, u4.t3527, u4.t3528, u4.t3529, u4.t3530, u4.t3531, u4.t3532, u4.t3533, u4.t3534, u4.t3535, u4.t3536, u4.t3537, u4.t3538, u4.t3539, u4.t3540, u4.t3541, u4.t3542, u4.t3543, u4.t3544, u4.t3545, u4.t3546, u4.t3547, u4.t3548, u4.t3549, u4.t3550, u4.t3551, u4.t3552, u4.t3553, u4.t3554, u4.t3555, u4.t3556, u4.t3557, u4.t3558, u4.t3559, u4.t3560, u4.t3561, u4.t3562, u4.t3563, u4.t3564, u4.t3565, u4.t3566, u4.t3567, u4.t3568, u4.t3569, u4.t3570, u4.t3571, u4.t3572, u4.t3573, u4.t3574, u4.t3575, u4.t3576, u4.t3577, u4.t3578, u4.t3579, u4.t3580, u4.t3581, u4.t3582, u4.t3583, u4.t3584, u4.t3585, u4.t3586, u4.t3587, u4.t3588, u4.t3589, u4.t3590, u4.t3591, u4.t3592, u4.t3593, u4.t3594, u4.t3595, u4.t3596, u4.t3597, u4.t3598, u4.t3599, u4.t3600, u4.t3601, u4.t3602, u4.t3603, u4.t3604, u4.t3605, u4.t3606, u4.t3607, u4.t3608, u4.t3609, u4.t3610, u4.t3611, u4.t3612, u4.t3613, u4.t3614, u4.t3615, u4.t3616, u4.t3617, u4.t3618, u4.t3619, u4.t3620, u4.t3621, u4.t3622, u4.t3623, u4.t3624, u4.t3625, u4.t3626, u4.t3627, u4.t3628, u4.t3629, u4.t3630, u4.t3631, u4.t3632, u4.t3633, u4.t3634, u4.t3635, u4.t3636, u4.t3637, u4.t3638, u4.t3639, u4.t3640, u4.t3641, u4.t3642, u4.t3643, u4.t3644, u4.t3645, u4.t3646, u4.t3647, u4.t3648, u4.t3649, u4.t3650, u4.t3651, u4.t3652, u4.t3653, u4.t3654, u4.t3655, u4.t3656, u4.t3657, u4.t3658, u4.t3659, u4.t3660, u4.t3661, u4.t3662, u4.t3663, u4.t3664, u4.t3665, u4.t3666, u4.t3667, u4.t3668, u4.t3669, u4.t3670, u4.t3671, u5.t3372, u5.t3373, u5.t3374, u5.t3375, u5.t3376, u5.t3377, u5.t3378, u5.t3379, u5.t3380, u5.t3381, u5.t3382, u5.t3383, u5.t3384, u5.t3385, u5.t3386, u5.t3387, u5.t3388, u5.t3389, u5.t3390, u5.t3391, u5.t3392, u5.t3393, u5.t3394, u5.t3395, u5.t3396, u5.t3397, u5.t3398, u5.t3399, u5.t3400, u5.t3401, u5.t3402, u5.t3403, u5.t3404, u5.t3405, u5.t3406, u5.t3407, u5.t3408, u5.t3409, u5.t3410, u5.t3411, u5.t3412, u5.t3413, u5.t3414, u5.t3415, u5.t3416, u5.t3417, u5.t3418, u5.t3419, u5.t3420, u5.t3421, u5.t3422, u5.t3423, u5.t3424, u5.t3425, u5.t3426, u5.t3427, u5.t3428, u5.t3429, u5.t3430, u5.t3431, u5.t3432, u5.t3433, u5.t3434, u5.t3435, u5.t3436, u5.t3437, u5.t3438, u5.t3439, u5.t3440, u5.t3441, u5.t3442, u5.t3443, u5.t3444, u5.t3445, u5.t3446, u5.t3447, u5.t3448, u5.t3449, u5.t3450, u5.t3451, u5.t3452, u5.t3453, u5.t3454, u5.t3455, u5.t3456, u5.t3457, u5.t3458, u5.t3459, u5.t3460, u5.t3461, u5.t3462, u5.t3463, u5.t3464, u5.t3465, u5.t3466, u5.t3467, u5.t3468, u5.t3469, u5.t3470, u5.t3471, u5.t3472, u5.t3473, u5.t3474, u5.t3475, u5.t3476, u5.t3477, u5.t3478, u5.t3479, u5.t3480, u5.t3481, u5.t3482, u5.t3483, u5.t3484, u5.t3485, u5.t3486, u5.t3487, u5.t3488, u5.t3489, u5.t3490, u5.t3491, u5.t3492, u5.t3493, u5.t3494, u5.t3495, u5.t3496, u5.t3497, u5.t3498, u5.t3499, u5.t3500, u5.t3501, u5.t3502, u5.t3503, u5.t3504, u5.t3505, u5.t3506, u5.t3507, u5.t3508, u5.t3509, u5.t3510, u5.t3511, u5.t3512, u5.t3513, u5.t3514, u5.t3515, u5.t3516, u5.t3517, u5.t3518, u5.t3519, u5.t3520, u11.t3217, u11.t3218, u11.t3219, u11.t3220, u11.t3221, u11.t3222, u11.t3223, u11.t3224, u11.t3225, u11.t3226, u11.t3227, u11.t3228, u11.t3229, u11.t3230, u11.t3231, u11.t3232, u11.t3233, u11.t3234, u11.t3235, u11.t3236, u11.t3237, u11.t3238, u11.t3239, u11.t3240, u11.t3241, u11.t3242, u11.t3243, u11.t3244, u11.t3245, u11.t3246, u11.t3247, u11.t3248, u11.t3249, u11.t3250, u11.t3251, u11.t3252, u11.t3253, u11.t3254, u11.t3255, u11.t3256, u11.t3257, u11.t3258, u11.t3259, u11.t3260, u11.t3261, u11.t3262, u11.t3263, u11.t3264, u11.t3265, u11.t3266, u11.t3267, u11.t3268, u11.t3269, u11.t3270, u11.t3271, u11.t3272, u11.t3273, u11.t3274, u11.t3275, u11.t3276, u11.t3277, u11.t3278, u11.t3279, u11.t3280, u11.t3281, u11.t3282, u11.t3283, u11.t3284, u11.t3285, u11.t3286, u11.t3287, u11.t3288, u11.t3289, u11.t3290, u11.t3291, u11.t3292, u11.t3293, u11.t3294, u11.t3295, u11.t3296, u11.t3297, u11.t3298, u11.t3299, u11.t3300, u11.t3301, u11.t3302, u11.t3303, u11.t3304, u11.t3305, u11.t3306, u11.t3307, u11.t3308, u11.t3309, u11.t3310, u11.t3311, u11.t3312, u11.t3313, u11.t3314, u11.t3315, u11.t3316, u11.t3317, u11.t3318, u11.t3319, u11.t3320, u11.t3321, u11.t3322, u11.t3323, u11.t3324, u11.t3325, u11.t3326, u11.t3327, u11.t3328, u11.t3329, u11.t3330, u11.t3331, u11.t3332, u11.t3333, u11.t3334, u11.t3335, u11.t3336, u11.t3337, u11.t3338, u11.t3339, u11.t3340, u11.t3341, u11.t3342, u11.t3343, u11.t3344, u11.t3345, u11.t3346, u11.t3347, u11.t3348, u11.t3349, u11.t3350, u11.t3351, u11.t3352, u11.t3353, u11.t3354, u11.t3355, u11.t3356, u11.t3357, u11.t3358, u11.t3359, u11.t3360, u11.t3361, u11.t3362, u11.t3363, u11.t3364, u11.t3365, u12.t3066, u12.t3067, u12.t3068, u12.t3069, u12.t3070, u12.t3071, u12.t3072, u12.t3073, u12.t3074, u12.t3075, u12.t3076, u12.t3077, u12.t3078, u12.t3079, u12.t3080, u12.t3081, u12.t3082, u12.t3083, u12.t3084, u12.t3085, u12.t3086, u12.t3087, u12.t3088, u12.t3089, u12.t3090, u12.t3091, u12.t3092, u12.t3093, u12.t3094, u12.t3095, u12.t3096, u12.t3097, u12.t3098, u12.t3099, u12.t3100, u12.t3101, u12.t3102, u12.t3103, u12.t3104, u12.t3105, u12.t3106, u12.t3107, u12.t3108, u12.t3109, u12.t3110, u12.t3111, u12.t3112, u12.t3113, u12.t3114, u12.t3115, u12.t3116, u12.t3117, u12.t3118, u12.t3119, u12.t3120, u12.t3121, u12.t3122, u12.t3123, u12.t3124, u12.t3125, u12.t3126, u12.t3127, u12.t3128, u12.t3129, u12.t3130, u12.t3131, u12.t3132, u12.t3133, u12.t3134, u12.t3135, u12.t3136, u12.t3137, u12.t3138, u12.t3139, u12.t3140, u12.t3141, u12.t3142, u12.t3143, u12.t3144, u12.t3145, u12.t3146, u12.t3147, u12.t3148, u12.t3149, u12.t3150, u12.t3151, u12.t3152, u12.t3153, u12.t3154, u12.t3155, u12.t3156, u12.t3157, u12.t3158, u12.t3159, u12.t3160, u12.t3161, u12.t3162, u12.t3163, u12.t3164, u12.t3165, u12.t3166, u12.t3167, u12.t3168, u12.t3169, u12.t3170, u12.t3171, u12.t3172, u12.t3173, u12.t3174, u12.t3175, u12.t3176, u12.t3177, u12.t3178, u12.t3179, u12.t3180, u12.t3181, u12.t3182, u12.t3183, u12.t3184, u12.t3185, u12.t3186, u12.t3187, u12.t3188, u12.t3189, u12.t3190, u12.t3191, u12.t3192, u12.t3193, u12.t3194, u12.t3195, u12.t3196, u12.t3197, u12.t3198, u12.t3199, u12.t3200, u12.t3201, u12.t3202, u12.t3203, u12.t3204, u12.t3205, u12.t3206, u12.t3207, u12.t3208, u12.t3209, u12.t3210, u12.t3211, u12.t3212, u12.t3213, u12.t3214, u13.t2915, u13.t2916, u13.t2917, u13.t2918, u13.t2919, u13.t2920, u13.t2921, u13.t2922, u13.t2923, u13.t2924, u13.t2925, u13.t2926, u13.t2927, u13.t2928, u13.t2929, u13.t2930, u13.t2931, u13.t2932, u13.t2933, u13.t2934, u13.t2935, u13.t2936, u13.t2937, u13.t2938, u13.t2939, u13.t2940, u13.t2941, u13.t2942, u13.t2943, u13.t2944, u13.t2945, u13.t2946, u13.t2947, u13.t2948, u13.t2949, u13.t2950, u13.t2951, u13.t2952, u13.t2953, u13.t2954, u13.t2955, u13.t2956, u13.t2957, u13.t2958, u13.t2959, u13.t2960, u13.t2961, u13.t2962, u13.t2963, u13.t2964, u13.t2965, u13.t2966, u13.t2967, u13.t2968, u13.t2969, u13.t2970, u13.t2971, u13.t2972, u13.t2973, u13.t2974, u13.t2975, u13.t2976, u13.t2977, u13.t2978, u13.t2979, u13.t2980, u13.t2981, u13.t2982, u13.t2983, u13.t2984, u13.t2985, u13.t2986, u13.t2987, u13.t2988, u13.t2989, u13.t2990, u13.t2991, u13.t2992, u13.t2993, u13.t2994, u13.t2995, u13.t2996, u13.t2997, u13.t2998, u13.t2999, u13.t3000, u13.t3001, u13.t3002, u13.t3003, u13.t3004, u13.t3005, u13.t3006, u13.t3007, u13.t3008, u13.t3009, u13.t3010, u13.t3011, u13.t3012, u13.t3013, u13.t3014, u13.t3015, u13.t3016, u13.t3017, u13.t3018, u13.t3019, u13.t3020, u13.t3021, u13.t3022, u13.t3023, u13.t3024, u13.t3025, u13.t3026, u13.t3027, u13.t3028, u13.t3029, u13.t3030, u13.t3031, u13.t3032, u13.t3033, u13.t3034, u13.t3035, u13.t3036, u13.t3037, u13.t3038, u13.t3039, u13.t3040, u13.t3041, u13.t3042, u13.t3043, u13.t3044, u13.t3045, u13.t3046, u13.t3047, u13.t3048, u13.t3049, u13.t3050, u13.t3051, u13.t3052, u13.t3053, u13.t3054, u13.t3055, u13.t3056, u13.t3057, u13.t3058, u13.t3059, u13.t3060, u13.t3061, u13.t3062, u13.t3063, u18.t2758, u18.t2759, u18.t2760, u18.t2761, u18.t2762, u18.t2763, u18.t2764, u18.t2765, u18.t2766, u18.t2767, u18.t2768, u18.t2769, u18.t2770, u18.t2771, u18.t2772, u18.t2773, u18.t2774, u18.t2775, u18.t2776, u18.t2777, u18.t2778, u18.t2779, u18.t2780, u18.t2781, u18.t2782, u18.t2783, u18.t2784, u18.t2785, u18.t2786, u18.t2787, u18.t2788, u18.t2789, u18.t2790, u18.t2791, u18.t2792, u18.t2793, u18.t2794, u18.t2795, u18.t2796, u18.t2797, u18.t2798, u18.t2799, u18.t2800, u18.t2801, u18.t2802, u18.t2803, u18.t2804, u18.t2805, u18.t2806, u18.t2807, u18.t2808, u18.t2809, u18.t2810, u18.t2811, u18.t2812, u18.t2813, u18.t2814, u18.t2815, u18.t2816, u18.t2817, u18.t2818, u18.t2819, u18.t2820, u18.t2821, u18.t2822, u18.t2823, u18.t2824, u18.t2825, u18.t2826, u18.t2827, u18.t2828, u18.t2829, u18.t2830, u18.t2831, u18.t2832, u18.t2833, u18.t2834, u18.t2835, u18.t2836, u18.t2837, u18.t2838, u18.t2839, u18.t2840, u18.t2841, u18.t2842, u18.t2843, u18.t2844, u18.t2845, u18.t2846, u18.t2847, u18.t2848, u18.t2849, u18.t2850, u18.t2851, u18.t2852, u18.t2853, u18.t2854, u18.t2855, u18.t2856, u18.t2857, u18.t2858, u18.t2859, u18.t2860, u18.t2861, u18.t2862, u18.t2863, u18.t2864, u18.t2865, u18.t2866, u18.t2867, u18.t2868, u18.t2869, u18.t2870, u18.t2871, u18.t2872, u18.t2873, u18.t2874, u18.t2875, u18.t2876, u18.t2877, u18.t2878, u18.t2879, u18.t2880, u18.t2881, u18.t2882, u18.t2883, u18.t2884, u18.t2885, u18.t2886, u18.t2887, u18.t2888, u18.t2889, u18.t2890, u18.t2891, u18.t2892, u18.t2893, u18.t2894, u18.t2895, u18.t2896, u18.t2897, u18.t2898, u18.t2899, u18.t2900, u18.t2901, u18.t2902, u18.t2903, u18.t2904, u18.t2905, u18.t2906, u19.t2607, u19.t2608, u19.t2609, u19.t2610, u19.t2611, u19.t2612, u19.t2613, u19.t2614, u19.t2615, u19.t2616, u19.t2617, u19.t2618, u19.t2619, u19.t2620, u19.t2621, u19.t2622, u19.t2623, u19.t2624, u19.t2625, u19.t2626, u19.t2627, u19.t2628, u19.t2629, u19.t2630, u19.t2631, u19.t2632, u19.t2633, u19.t2634, u19.t2635, u19.t2636, u19.t2637, u19.t2638, u19.t2639, u19.t2640, u19.t2641, u19.t2642, u19.t2643, u19.t2644, u19.t2645, u19.t2646, u19.t2647, u19.t2648, u19.t2649, u19.t2650, u19.t2651, u19.t2652, u19.t2653, u19.t2654, u19.t2655, u19.t2656, u19.t2657, u19.t2658, u19.t2659, u19.t2660, u19.t2661, u19.t2662, u19.t2663, u19.t2664, u19.t2665, u19.t2666, u19.t2667, u19.t2668, u19.t2669, u19.t2670, u19.t2671, u19.t2672, u19.t2673, u19.t2674, u19.t2675, u19.t2676, u19.t2677, u19.t2678, u19.t2679, u19.t2680, u19.t2681, u19.t2682, u19.t2683, u19.t2684, u19.t2685, u19.t2686, u19.t2687, u19.t2688, u19.t2689, u19.t2690, u19.t2691, u19.t2692, u19.t2693, u19.t2694, u19.t2695, u19.t2696, u19.t2697, u19.t2698, u19.t2699, u19.t2700, u19.t2701, u19.t2702, u19.t2703, u19.t2704, u19.t2705, u19.t2706, u19.t2707, u19.t2708, u19.t2709, u19.t2710, u19.t2711, u19.t2712, u19.t2713, u19.t2714, u19.t2715, u19.t2716, u19.t2717, u19.t2718, u19.t2719, u19.t2720, u19.t2721, u19.t2722, u19.t2723, u19.t2724, u19.t2725, u19.t2726, u19.t2727, u19.t2728, u19.t2729, u19.t2730, u19.t2731, u19.t2732, u19.t2733, u19.t2734, u19.t2735, u19.t2736, u19.t2737, u19.t2738, u19.t2739, u19.t2740, u19.t2741, u19.t2742, u19.t2743, u19.t2744, u19.t2745, u19.t2746, u19.t2747, u19.t2748, u19.t2749, u19.t2750, u19.t2751, u19.t2752, u19.t2753, u19.t2754, u19.t2755, u25.t2452, u25.t2453, u25.t2454, u25.t2455, u25.t2456, u25.t2457, u25.t2458, u25.t2459, u25.t2460, u25.t2461, u25.t2462, u25.t2463, u25.t2464, u25.t2465, u25.t2466, u25.t2467, u25.t2468, u25.t2469, u25.t2470, u25.t2471, u25.t2472, u25.t2473, u25.t2474, u25.t2475, u25.t2476, u25.t2477, u25.t2478, u25.t2479, u25.t2480, u25.t2481, u25.t2482, u25.t2483, u25.t2484, u25.t2485, u25.t2486, u25.t2487, u25.t2488, u25.t2489, u25.t2490, u25.t2491, u25.t2492, u25.t2493, u25.t2494, u25.t2495, u25.t2496, u25.t2497, u25.t2498, u25.t2499, u25.t2500, u25.t2501, u25.t2502, u25.t2503, u25.t2504, u25.t2505, u25.t2506, u25.t2507, u25.t2508, u25.t2509, u25.t2510, u25.t2511, u25.t2512, u25.t2513, u25.t2514, u25.t2515, u25.t2516, u25.t2517, u25.t2518, u25.t2519, u25.t2520, u25.t2521, u25.t2522, u25.t2523, u25.t2524, u25.t2525, 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u51.t857, u51.t858, u51.t859, u51.t860, u51.t861, u51.t862, u51.t863, u51.t864, u51.t865, u51.t866, u51.t867, u51.t868, u51.t869, u51.t870, u51.t871, u51.t872, u51.t873, u51.t874, u51.t875, u51.t876, u51.t877, u51.t878, u51.t879, u51.t880, u51.t881, u51.t882, u51.t883, u51.t884, u51.t885, u51.t886, u51.t887, u51.t888, u51.t889, u51.t890, u51.t891, u51.t892, u51.t893, u51.t894, u51.t895, u51.t896, u51.t897, u51.t898, u51.t899, u51.t900, u51.t901, u51.t902, u51.t903, u51.t904, u51.t905, u51.t906, u51.t907, u51.t908, u51.t909, u51.t910, u51.t911, u51.t912, u51.t913, u51.t914, u51.t915, u51.t916, u51.t917, u57.t614, u57.t615, u57.t616, u57.t617, u57.t618, u57.t619, u57.t620, u57.t621, u57.t622, u57.t623, u57.t624, u57.t625, u57.t626, u57.t627, u57.t628, u57.t629, u57.t630, u57.t631, u57.t632, u57.t633, u57.t634, u57.t635, u57.t636, u57.t637, u57.t638, u57.t639, u57.t640, u57.t641, u57.t642, u57.t643, u57.t644, u57.t645, u57.t646, u57.t647, u57.t648, u57.t649, u57.t650, u57.t651, u57.t652, u57.t653, u57.t654, u57.t655, u57.t656, u57.t657, u57.t658, u57.t659, u57.t660, u57.t661, u57.t662, u57.t663, u57.t664, u57.t665, u57.t666, u57.t667, u57.t668, u57.t669, u57.t670, u57.t671, u57.t672, u57.t673, u57.t674, u57.t675, u57.t676, u57.t677, u57.t678, u57.t679, u57.t680, u57.t681, u57.t682, u57.t683, u57.t684, u57.t685, u57.t686, u57.t687, u57.t688, u57.t689, u57.t690, u57.t691, u57.t692, u57.t693, u57.t694, u57.t695, u57.t696, u57.t697, u57.t698, u57.t699, u57.t700, u57.t701, u57.t702, u57.t703, u57.t704, u57.t705, u57.t706, u57.t707, u57.t708, u57.t709, u57.t710, u57.t711, u57.t712, u57.t713, u57.t714, u57.t715, u57.t716, u57.t717, u57.t718, u57.t719, u57.t720, u57.t721, u57.t722, u57.t723, u57.t724, u57.t725, u57.t726, u57.t727, u57.t728, u57.t729, u57.t730, u57.t731, u57.t732, u57.t733, u57.t734, u57.t735, u57.t736, u57.t737, u57.t738, u57.t739, u57.t740, u57.t741, u57.t742, u57.t743, u57.t744, u57.t745, u57.t746, u57.t747, u57.t748, u57.t749, u57.t750, u57.t751, u57.t752, u57.t753, u57.t754, u57.t755, u57.t756, u57.t757, u57.t758, u57.t759, u57.t760, u57.t761, u57.t762, u58.t463, u58.t464, u58.t465, u58.t466, u58.t467, u58.t468, u58.t469, u58.t470, u58.t471, u58.t472, u58.t473, u58.t474, u58.t475, u58.t476, u58.t477, u58.t478, u58.t479, u58.t480, u58.t481, u58.t482, u58.t483, u58.t484, u58.t485, u58.t486, u58.t487, u58.t488, u58.t489, u58.t490, u58.t491, u58.t492, u58.t493, u58.t494, u58.t495, u58.t496, u58.t497, u58.t498, u58.t499, u58.t500, u58.t501, u58.t502, u58.t503, u58.t504, u58.t505, u58.t506, u58.t507, u58.t508, u58.t509, u58.t510, u58.t511, u58.t512, u58.t513, u58.t514, u58.t515, u58.t516, u58.t517, u58.t518, u58.t519, u58.t520, u58.t521, u58.t522, u58.t523, u58.t524, u58.t525, u58.t526, u58.t527, u58.t528, u58.t529, u58.t530, u58.t531, u58.t532, u58.t533, u58.t534, u58.t535, u58.t536, u58.t537, u58.t538, u58.t539, u58.t540, u58.t541, u58.t542, u58.t543, u58.t544, u58.t545, u58.t546, u58.t547, u58.t548, u58.t549, u58.t550, u58.t551, u58.t552, u58.t553, u58.t554, u58.t555, u58.t556, u58.t557, u58.t558, u58.t559, u58.t560, u58.t561, u58.t562, u58.t563, u58.t564, u58.t565, u58.t566, u58.t567, u58.t568, u58.t569, u58.t570, u58.t571, u58.t572, u58.t573, u58.t574, u58.t575, u58.t576, u58.t577, u58.t578, u58.t579, u58.t580, u58.t581, u58.t582, u58.t583, u58.t584, u58.t585, u58.t586, u58.t587, u58.t588, u58.t589, u58.t590, u58.t591, u58.t592, u58.t593, u58.t594, u58.t595, u58.t596, u58.t597, u58.t598, u58.t599, u58.t600, u58.t601, u58.t602, u58.t603, u58.t604, u58.t605, u58.t606, u58.t607, u58.t608, u58.t609, u58.t610, u58.t611, u59.t312, u59.t313, u59.t314, u59.t315, u59.t316, u59.t317, u59.t318, u59.t319, u59.t320, u59.t321, u59.t322, u59.t323, u59.t324, u59.t325, u59.t326, u59.t327, u59.t328, u59.t329, u59.t330, u59.t331, u59.t332, u59.t333, u59.t334, u59.t335, u59.t336, u59.t337, u59.t338, u59.t339, u59.t340, u59.t341, u59.t342, u59.t343, u59.t344, u59.t345, u59.t346, u59.t347, u59.t348, u59.t349, u59.t350, u59.t351, u59.t352, u59.t353, u59.t354, u59.t355, u59.t356, u59.t357, u59.t358, u59.t359, u59.t360, u59.t361, u59.t362, u59.t363, u59.t364, u59.t365, u59.t366, u59.t367, u59.t368, u59.t369, u59.t370, u59.t371, u59.t372, u59.t373, u59.t374, u59.t375, u59.t376, u59.t377, u59.t378, u59.t379, u59.t380, u59.t381, u59.t382, u59.t383, u59.t384, u59.t385, u59.t386, u59.t387, u59.t388, u59.t389, u59.t390, u59.t391, u59.t392, u59.t393, u59.t394, u59.t395, u59.t396, u59.t397, u59.t398, u59.t399, u59.t400, u59.t401, u59.t402, u59.t403, u59.t404, u59.t405, u59.t406, u59.t407, u59.t408, u59.t409, u59.t410, u59.t411, u59.t412, u59.t413, u59.t414, u59.t415, u59.t416, u59.t417, u59.t418, u59.t419, u59.t420, u59.t421, u59.t422, u59.t423, u59.t424, u59.t425, u59.t426, u59.t427, u59.t428, u59.t429, u59.t430, u59.t431, u59.t432, u59.t433, u59.t434, u59.t435, u59.t436, u59.t437, u59.t438, u59.t439, u59.t440, u59.t441, u59.t442, u59.t443, u59.t444, u59.t445, u59.t446, u59.t447, u59.t448, u59.t449, u59.t450, u59.t451, u59.t452, u59.t453, u59.t454, u59.t455, u59.t456, u59.t457, u59.t458, u59.t459, u59.t460, u64.t156, u64.t157, u64.t158, u64.t159, u64.t160, u64.t161, u64.t162, u64.t163, u64.t164, u64.t165, u64.t166, u64.t167, u64.t168, u64.t169, u64.t170, u64.t171, u64.t172, u64.t173, u64.t174, u64.t175, u64.t176, u64.t177, u64.t178, u64.t179, u64.t180, u64.t181, u64.t182, u64.t183, u64.t184, u64.t185, u64.t186, u64.t187, u64.t188, u64.t189, u64.t190, u64.t191, u64.t192, u64.t193, u64.t194, u64.t195, u64.t196, u64.t197, u64.t198, u64.t199, u64.t200, u64.t201, u64.t202, u64.t203, u64.t204, u64.t205, u64.t206, u64.t207, u64.t208, u64.t209, u64.t210, u64.t211, u64.t212, u64.t213, u64.t214, u64.t215, u64.t216, u64.t217, u64.t218, u64.t219, u64.t220, u64.t221, u64.t222, u64.t223, u64.t224, u64.t225, u64.t226, u64.t227, u64.t228, u64.t229, u64.t230, u64.t231, u64.t232, u64.t233, u64.t234, u64.t235, u64.t236, u64.t237, u64.t238, u64.t239, u64.t240, u64.t241, u64.t242, u64.t243, u64.t244, u64.t245, u64.t246, u64.t247, u64.t248, u64.t249, u64.t250, u64.t251, u64.t252, u64.t253, u64.t254, u64.t255, u64.t256, u64.t257, u64.t258, u64.t259, u64.t260, u64.t261, u64.t262, u64.t263, u64.t264, u64.t265, u64.t266, u64.t267, u64.t268, u64.t269, u64.t270, u64.t271, u64.t272, u64.t273, u64.t274, u64.t275, u64.t276, u64.t277, u64.t278, u64.t279, u64.t280, u64.t281, u64.t282, u64.t283, u64.t284, u64.t285, u64.t286, u64.t287, u64.t288, u64.t289, u64.t290, u64.t291, u64.t292, u64.t293, u64.t294, u64.t295, u64.t296, u64.t297, u64.t298, u64.t299, u64.t300, u64.t301, u64.t302, u64.t303, u64.t304, u65.t5, u65.t6, u65.t7, u65.t8, u65.t9, u65.t10, u65.t11, u65.t12, u65.t13, u65.t14, u65.t15, u65.t16, u65.t17, u65.t18, u65.t19, u65.t20, u65.t21, u65.t22, u65.t23, u65.t24, u65.t25, u65.t26, u65.t27, u65.t28, u65.t29, u65.t30, u65.t31, u65.t32, u65.t33, u65.t34, u65.t35, u65.t36, u65.t37, u65.t38, u65.t39, u65.t40, u65.t41, u65.t42, u65.t43, u65.t44, u65.t45, u65.t46, u65.t47, u65.t48, u65.t49, u65.t50, u65.t51, u65.t52, u65.t53, u65.t54, u65.t55, u65.t56, u65.t57, u65.t58, u65.t59, u65.t60, u65.t61, u65.t62, u65.t63, u65.t64, u65.t65, u65.t66, u65.t67, u65.t68, u65.t69, u65.t70, u65.t71, u65.t72, u65.t73, u65.t74, u65.t75, u65.t76, u65.t77, u65.t78, u65.t79, u65.t80, u65.t81, u65.t82, u65.t83, u65.t84, u65.t85, u65.t86, u65.t87, u65.t88, u65.t89, u65.t90, u65.t91, u65.t92, u65.t93, u65.t94, u65.t95, u65.t96, u65.t97, u65.t98, u65.t99, u65.t100, u65.t101, u65.t102, u65.t103, u65.t104, u65.t105, u65.t106, u65.t107, u65.t108, u65.t109, u65.t110, u65.t111, u65.t112, u65.t113, u65.t114, u65.t115, u65.t116, u65.t117, u65.t118, u65.t119, u65.t120, u65.t121, u65.t122, u65.t123, u65.t124, u65.t125, u65.t126, u65.t127, u65.t128, u65.t129, u65.t130, u65.t131, u65.t132, u65.t133, u65.t134, u65.t135, u65.t136, u65.t137, u65.t138, u65.t139, u65.t140, u65.t141, u65.t142, u65.t143, u65.t144, u65.t145, u65.t146, u65.t147, u65.t148, u65.t149, u65.t150, u65.t151, u65.t152, u65.t153, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :3607/662/24/4293
LTSmin run took 737872 ms.
FORMULA NoC3x3-PT-8A-LTLCardinality-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, <>([]((LTLAP9==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 154093 ms.
FORMULA NoC3x3-PT-8A-LTLCardinality-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1553572813591

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ LTLCardinality = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Mar 26, 2019 3:30:49 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Mar 26, 2019 3:30:49 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Mar 26, 2019 3:30:49 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 216 ms
Mar 26, 2019 3:30:49 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 317 places.
Mar 26, 2019 3:30:49 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 4293 transitions.
Mar 26, 2019 3:30:49 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
Mar 26, 2019 3:30:50 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 51 ms
Mar 26, 2019 3:30:50 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Mar 26, 2019 3:30:50 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 623 ms
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 380 ms
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 3 events :t3825,t3825,t3825,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 17 events :t3964,t3964,t3964,t3964,t3964,t3964,t3964,t3955,t3955,t3955,t3955,t3955,t3955,t3955,t3955,t3937,t3937,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 12 events :t4159,t4158,t3851,t3850,t3849,t3848,t3847,t3846,t3829,t3828,t3807,t3806,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 20 events :t4056,t4055,t3963,t4029,t4028,t3962,t3959,t3958,t3963,t3962,t3959,t3958,t3963,t3962,t3961,t3960,t3959,t3958,t3945,t3944,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 14 events :t3810,t3810,t3810,t3810,t3810,t3810,t3810,t3802,t3802,t3802,t3802,t3802,t3802,t3802,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 14 events :t4169,t4169,t4169,t4162,t4162,t4162,t4162,t4162,t4162,t4156,t4156,t4156,t4156,t4156,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 1 events :t3922,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 6 events :t4003,t4002,t4001,t4000,t3978,t3977,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 15 events :t4176,t4176,t3930,t3930,t3930,t3930,t3930,t3930,t3922,t3922,t3922,t3922,t3922,t3922,t3922,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 6 events :t3738,t3738,t3738,t3734,t3734,t3734,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 9 events :t4218,t4218,t4213,t4213,t4213,t4213,t4209,t4209,t4209,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 10 events :t3769,t3769,t3769,t3769,t3769,t3763,t3763,t3763,t3763,t3763,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 10 events :t3872,t3872,t3872,t3872,t3872,t3866,t3866,t3866,t3866,t3866,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 8 events :t4120,t4115,t4115,t4115,t4115,t4111,t4111,t4111,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 6 events :t4182,t4181,t3784,t3783,t3764,t3763,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 8 events :t4257,t4256,t4237,t4236,t3721,t3720,t3702,t3701,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 9 events :t4200,t4200,t4195,t4195,t4195,t4195,t4191,t4191,t4191,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 2 events :t3881,t3881,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 1 events :t3986,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 14 events :t4265,t4265,t4265,t4258,t4258,t4258,t4258,t4258,t4258,t4252,t4252,t4252,t4252,t4252,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 2 events :t3955,t3955,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 19 events :t4022,t4022,t4009,t4009,t4009,t4009,t4009,t4009,t4009,t4009,t4009,t4000,t4000,t4000,t4000,t4000,t4000,t4000,t4000,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 9 events :t4210,t4209,t3752,t3751,t3750,t3749,t3748,t3737,t3736,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 28 events :t4125,t4125,t4125,t3895,t3895,t3895,t3895,t3895,t3895,t3895,t3895,t3895,t3895,t3895,t3895,t3881,t3881,t3881,t3881,t3881,t3881,t3881,t3881,t3881,t3881,t3881,t3881,t3881,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 22 events :t4224,t4224,t4224,t3852,t3852,t3852,t3852,t3852,t3852,t3852,t3852,t3852,t3841,t3841,t3841,t3841,t3841,t3841,t3841,t3841,t3841,t3841,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 1 events :t3689,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 10 events :t3707,t3707,t3707,t3707,t3707,t3701,t3701,t3701,t3701,t3701,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 6 events :t4098,t4097,t3883,t3882,t3867,t3866,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 12 events :t4157,t4156,t4137,t4136,t4135,t4134,t4133,t4132,t3831,t3830,t3809,t3808,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 9 events :t4058,t4057,t4035,t4034,t4033,t4032,t4031,t3943,t3942,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 8 events :t4194,t4193,t4180,t4179,t3786,t3785,t3766,t3765,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 6 events :t4279,t4278,t3693,t3692,t3677,t3676,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 21 events :t4272,t4272,t4238,t4238,t4238,t4238,t4238,t4238,t4238,t4238,t4238,t4238,t4228,t4228,t4228,t4228,t4228,t4228,t4228,t4228,t4228,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 6 events :t4192,t4191,t3788,t3787,t3768,t3767,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 2 events :t3719,t3719,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 1 events :t3745,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 15 events :t3991,t3988,t4006,t4005,t3987,t3991,t3988,t3987,t3991,t3990,t3989,t3988,t3987,t3976,t3975,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 12 events :t4253,t4252,t4233,t4232,t4231,t4230,t4229,t4228,t3723,t3722,t3706,t3705,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 6 events :t4255,t4254,t4235,t4234,t3704,t3703,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 6 events :t4212,t4211,t3747,t3746,t3735,t3734,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 17 events :t4099,t4099,t4099,t4099,t4099,t4099,t4099,t4099,t4091,t4091,t4091,t4091,t4091,t4091,t4091,t3760,t3760,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 2 events :t3782,t3782,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 10 events :t3694,t3694,t3694,t3689,t3689,t3689,t3689,t3685,t3685,t3685,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 9 events :t4287,t4287,t4282,t4282,t4282,t4282,t4278,t4278,t4278,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 6 events :t4037,t4036,t3957,t3956,t3941,t3940,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 14 events :t3789,t3789,t3789,t3789,t3789,t3782,t3782,t3782,t3782,t3782,t3782,t3778,t3778,t3778,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 9 events :t4082,t4082,t4077,t4077,t4077,t4077,t4073,t4073,t4073,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 9 events :t4074,t4073,t3929,t3928,t3927,t3926,t3925,t3914,t3913,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 15 events :t3753,t3753,t3753,t3753,t3753,t3753,t3745,t3745,t3745,t3745,t3745,t3745,t3745,t3731,t3731,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 9 events :t4183,t4183,t4183,t4183,t4179,t4179,t4179,t3698,t3698,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 8 events :t4161,t4160,t4139,t4138,t3845,t3844,t3805,t3804,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 6 events :t3915,t3915,t3915,t3911,t3911,t3911,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 22 events :t4142,t4142,t4142,t4142,t4142,t4142,t4142,t4142,t4142,t4142,t4132,t4132,t4132,t4132,t4132,t4132,t4132,t4132,t4132,t3798,t3798,t3798,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 28 events :t4038,t4038,t4038,t4038,t4038,t4038,t4038,t4038,t4038,t4038,t4038,t4038,t4038,t4025,t4025,t4025,t4025,t4025,t4025,t4025,t4025,t4025,t4025,t4025,t4025,t3862,t3862,t3862,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 20 events :t4114,t4113,t3889,t3888,t3885,t4093,t4092,t3884,t3889,t3888,t3885,t3884,t3889,t3888,t3887,t3886,t3885,t3884,t3869,t3868,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 10 events :t3946,t3946,t3946,t3946,t3946,t3940,t3940,t3940,t3940,t3940,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 6 events :t3979,t3979,t3979,t3975,t3975,t3975,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 6 events :t3678,t3678,t3678,t3674,t3674,t3674,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 8 events :t4141,t4140,t3843,t3842,t3827,t3826,t3803,t3802,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 9 events :t3724,t3724,t3724,t3719,t3719,t3719,t3719,t3716,t3716,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 9 events :t4112,t4111,t3894,t3893,t3892,t3891,t3890,t3871,t3870,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 6 events :t4076,t4075,t3924,t3923,t3912,t3911,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 9 events :t4064,t4064,t4059,t4059,t4059,t4059,t4055,t4055,t4055,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 6 events :t4281,t4280,t3691,t3690,t3675,t3674,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 14 events :t3832,t3832,t3832,t3832,t3832,t3825,t3825,t3825,t3825,t3825,t3825,t3821,t3821,t3821,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 11 events :t4088,t4088,t3992,t3992,t3992,t3992,t3986,t3986,t3986,t3986,t3986,
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 664 redundant transitions.
Mar 26, 2019 3:30:51 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 567 ms
Mar 26, 2019 3:30:52 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLCardinality.pnml.gal : 36 ms
Mar 26, 2019 3:30:52 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLCardinality.ltl : 1 ms
Mar 26, 2019 3:30:53 AM fr.lip6.move.gal.semantics.CompositeNextBuilder getNextForLabel
INFO: Semantic construction discarded 3607 identical transitions.
Mar 26, 2019 3:30:53 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 686 transitions.
Mar 26, 2019 3:30:54 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 66 place invariants in 309 ms
Mar 26, 2019 3:30:58 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 317 variables to be positive in 4807 ms
Mar 26, 2019 3:30:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 686 transitions.
Mar 26, 2019 3:30:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/686 took 13 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 26, 2019 3:30:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 138 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 26, 2019 3:30:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 686 transitions.
Mar 26, 2019 3:30:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 40 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 26, 2019 3:31:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 686 transitions.
Mar 26, 2019 3:31:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/686) took 2671 ms. Total solver calls (SAT/UNSAT): 685(0/685)
Mar 26, 2019 3:31:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(14/686) took 6112 ms. Total solver calls (SAT/UNSAT): 1032(59/973)
Mar 26, 2019 3:31:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(34/686) took 9219 ms. Total solver calls (SAT/UNSAT): 1457(157/1300)
Mar 26, 2019 3:31:16 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(55/686) took 12666 ms. Total solver calls (SAT/UNSAT): 1981(241/1740)
Mar 26, 2019 3:31:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(65/686) took 16092 ms. Total solver calls (SAT/UNSAT): 2183(295/1888)
Mar 26, 2019 3:31:23 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(73/686) took 19326 ms. Total solver calls (SAT/UNSAT): 2297(325/1972)
Mar 26, 2019 3:31:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(81/686) took 22545 ms. Total solver calls (SAT/UNSAT): 2499(357/2142)
Mar 26, 2019 3:31:30 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(90/686) took 26664 ms. Total solver calls (SAT/UNSAT): 2710(405/2305)
Mar 26, 2019 3:31:34 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(109/686) took 30517 ms. Total solver calls (SAT/UNSAT): 3196(485/2711)
Mar 26, 2019 3:31:37 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(112/686) took 33819 ms. Total solver calls (SAT/UNSAT): 3301(507/2794)
Mar 26, 2019 3:31:40 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(120/686) took 36908 ms. Total solver calls (SAT/UNSAT): 3569(571/2998)
Mar 26, 2019 3:31:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(137/686) took 40176 ms. Total solver calls (SAT/UNSAT): 4137(676/3461)
Mar 26, 2019 3:31:47 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(153/686) took 43236 ms. Total solver calls (SAT/UNSAT): 4585(780/3805)
Mar 26, 2019 3:31:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(163/686) took 46308 ms. Total solver calls (SAT/UNSAT): 4794(836/3958)
Mar 26, 2019 3:31:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(173/686) took 49744 ms. Total solver calls (SAT/UNSAT): 5122(874/4248)
Mar 26, 2019 3:31:57 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(178/686) took 53561 ms. Total solver calls (SAT/UNSAT): 5262(906/4356)
Mar 26, 2019 3:32:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(189/686) took 56806 ms. Total solver calls (SAT/UNSAT): 5698(1013/4685)
Mar 26, 2019 3:32:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(194/686) took 59935 ms. Total solver calls (SAT/UNSAT): 5853(1028/4825)
Mar 26, 2019 3:32:07 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(205/686) took 63177 ms. Total solver calls (SAT/UNSAT): 6160(1120/5040)
Mar 26, 2019 3:32:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(213/686) took 66227 ms. Total solver calls (SAT/UNSAT): 6328(1157/5171)
Mar 26, 2019 3:32:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(217/686) took 69490 ms. Total solver calls (SAT/UNSAT): 6424(1182/5242)
Mar 26, 2019 3:32:16 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(229/686) took 72794 ms. Total solver calls (SAT/UNSAT): 6682(1234/5448)
Mar 26, 2019 3:32:19 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(234/686) took 75872 ms. Total solver calls (SAT/UNSAT): 6805(1247/5558)
Mar 26, 2019 3:32:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(247/686) took 78979 ms. Total solver calls (SAT/UNSAT): 7194(1335/5859)
Mar 26, 2019 3:32:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(259/686) took 82171 ms. Total solver calls (SAT/UNSAT): 7557(1405/6152)
Mar 26, 2019 3:32:29 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(268/686) took 85486 ms. Total solver calls (SAT/UNSAT): 7804(1447/6357)
Mar 26, 2019 3:32:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(277/686) took 88877 ms. Total solver calls (SAT/UNSAT): 8019(1487/6532)
Mar 26, 2019 3:32:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(295/686) took 91906 ms. Total solver calls (SAT/UNSAT): 8416(1584/6832)
Mar 26, 2019 3:32:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(317/686) took 94980 ms. Total solver calls (SAT/UNSAT): 8942(1700/7242)
Mar 26, 2019 3:32:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(324/686) took 98310 ms. Total solver calls (SAT/UNSAT): 9094(1766/7328)
Mar 26, 2019 3:32:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(345/686) took 101485 ms. Total solver calls (SAT/UNSAT): 9366(1834/7532)
Mar 26, 2019 3:32:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(376/686) took 104564 ms. Total solver calls (SAT/UNSAT): 9788(1933/7855)
Mar 26, 2019 3:32:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(396/686) took 107620 ms. Total solver calls (SAT/UNSAT): 10139(2003/8136)
Mar 26, 2019 3:32:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(421/686) took 110681 ms. Total solver calls (SAT/UNSAT): 10553(2131/8422)
Mar 26, 2019 3:32:57 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(436/686) took 113809 ms. Total solver calls (SAT/UNSAT): 10707(2162/8545)
Mar 26, 2019 3:33:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(451/686) took 116837 ms. Total solver calls (SAT/UNSAT): 10864(2201/8663)
Mar 26, 2019 3:33:04 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(468/686) took 120217 ms. Total solver calls (SAT/UNSAT): 11080(2237/8843)
Mar 26, 2019 3:33:07 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(475/686) took 123921 ms. Total solver calls (SAT/UNSAT): 11276(2279/8997)
Mar 26, 2019 3:33:11 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(486/686) took 127124 ms. Total solver calls (SAT/UNSAT): 11485(2346/9139)
Mar 26, 2019 3:33:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(495/686) took 130288 ms. Total solver calls (SAT/UNSAT): 11633(2383/9250)
Mar 26, 2019 3:33:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(507/686) took 133302 ms. Total solver calls (SAT/UNSAT): 11749(2408/9341)
Mar 26, 2019 3:33:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(539/686) took 136309 ms. Total solver calls (SAT/UNSAT): 11924(2446/9478)
Mar 26, 2019 3:33:23 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(602/686) took 139395 ms. Total solver calls (SAT/UNSAT): 12051(2471/9580)
Mar 26, 2019 3:33:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(649/686) took 142431 ms. Total solver calls (SAT/UNSAT): 12144(2490/9654)
Mar 26, 2019 3:33:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 144723 ms. Total solver calls (SAT/UNSAT): 12214(2504/9710)
Mar 26, 2019 3:33:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 686 transitions.
Mar 26, 2019 3:33:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 166 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 26, 2019 3:33:29 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 156709ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="NoC3x3-PT-8A"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3954"
echo " Executing tool itstools"
echo " Input is NoC3x3-PT-8A, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r184-csrt-155344538100366"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/NoC3x3-PT-8A.tgz
mv NoC3x3-PT-8A execution
cd execution
if [ "LTLCardinality" = "GlobalProperties" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
if [ "LTLCardinality" = "UpperBounds" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;