fond
Model Checking Contest 2019
9th edition, Prague, Czech Republic, April 7, 2019 (TOOLympics)
Execution of r107-oct2-155272231200556
Last Updated
Apr 15, 2019

About the Execution of ITS-Tools for Peterson-PT-5

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
12682.500 611137.00 2001646.00 224.50 FFFFFFFFFFFFFFFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fko/mcc2019-input.r107-oct2-155272231200556.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fko/mcc2019-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................
=====================================================================
Generated by BenchKit 2-3954
Executing tool itstools
Input is Peterson-PT-5, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r107-oct2-155272231200556
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.0M
-rw-r--r-- 1 mcc users 65K Feb 12 04:17 CTLCardinality.txt
-rw-r--r-- 1 mcc users 179K Feb 12 04:17 CTLCardinality.xml
-rw-r--r-- 1 mcc users 30K Feb 8 03:27 CTLFireability.txt
-rw-r--r-- 1 mcc users 105K Feb 8 03:27 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 10 17:31 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K Mar 10 17:31 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 100 Feb 24 15:05 GlobalProperties.txt
-rw-r--r-- 1 mcc users 338 Feb 24 15:05 GlobalProperties.xml
-rw-r--r-- 1 mcc users 26K Feb 5 00:25 LTLCardinality.txt
-rw-r--r-- 1 mcc users 72K Feb 5 00:25 LTLCardinality.xml
-rw-r--r-- 1 mcc users 18K Feb 4 22:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 58K Feb 4 22:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 36K Feb 4 08:00 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 102K Feb 4 08:00 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 66K Feb 1 02:18 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 217K Feb 1 02:18 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 8.7K Feb 4 22:22 UpperBounds.txt
-rw-r--r-- 1 mcc users 19K Feb 4 22:22 UpperBounds.xml

-rw-r--r-- 1 mcc users 5 Jan 29 09:34 equiv_col
-rw-r--r-- 1 mcc users 2 Jan 29 09:34 instance
-rw-r--r-- 1 mcc users 6 Jan 29 09:34 iscolored
-rw-r--r-- 1 mcc users 911K Mar 10 17:31 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Peterson-PT-5-LTLFireability-00
FORMULA_NAME Peterson-PT-5-LTLFireability-01
FORMULA_NAME Peterson-PT-5-LTLFireability-02
FORMULA_NAME Peterson-PT-5-LTLFireability-03
FORMULA_NAME Peterson-PT-5-LTLFireability-04
FORMULA_NAME Peterson-PT-5-LTLFireability-05
FORMULA_NAME Peterson-PT-5-LTLFireability-06
FORMULA_NAME Peterson-PT-5-LTLFireability-07
FORMULA_NAME Peterson-PT-5-LTLFireability-08
FORMULA_NAME Peterson-PT-5-LTLFireability-09
FORMULA_NAME Peterson-PT-5-LTLFireability-10
FORMULA_NAME Peterson-PT-5-LTLFireability-11
FORMULA_NAME Peterson-PT-5-LTLFireability-12
FORMULA_NAME Peterson-PT-5-LTLFireability-13
FORMULA_NAME Peterson-PT-5-LTLFireability-14
FORMULA_NAME Peterson-PT-5-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1552938405010

Working with output stream class java.io.PrintStream
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903111103/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903111103/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !(("(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((Turn_2_1>=1)&&(AskForSection_2_2>=1))||((Turn_2_1>=1)&&(AskForSection_1_2>=1)))||((AskForSection_0_2>=1)&&(Turn_2_1>=1)))||((AskForSection_5_2>=1)&&(Turn_2_0>=1)))||((Turn_2_2>=1)&&(AskForSection_0_2>=1)))||((AskForSection_5_2>=1)&&(Turn_2_1>=1)))||((Turn_2_1>=1)&&(AskForSection_4_2>=1)))||((Turn_2_1>=1)&&(AskForSection_3_2>=1)))||((Turn_2_2>=1)&&(AskForSection_4_2>=1)))||((AskForSection_3_2>=1)&&(Turn_2_2>=1)))||((Turn_2_2>=1)&&(AskForSection_2_2>=1)))||((Turn_2_2>=1)&&(AskForSection_1_2>=1)))||((Turn_2_3>=1)&&(AskForSection_2_2>=1)))||((AskForSection_1_2>=1)&&(Turn_2_3>=1)))||((Turn_2_3>=1)&&(AskForSection_0_2>=1)))||((Turn_2_2>=1)&&(AskForSection_5_2>=1)))||((AskForSection_5_2>=1)&&(Turn_2_3>=1)))||((AskForSection_0_2>=1)&&(Turn_2_4>=1)))||((Turn_2_3>=1)&&(AskForSection_3_2>=1)))||((Turn_2_3>=1)&&(AskForSection_4_2>=1)))||((AskForSection_3_2>=1)&&(Turn_2_4>=1)))||((AskForSection_4_2>=1)&&(Turn_2_4>=1)))||((Turn_2_4>=1)&&(AskForSection_1_2>=1)))||((AskForSection_2_2>=1)&&(Turn_2_4>=1)))||((AskForSection_1_2>=1)&&(Turn_2_5>=1)))||((AskForSection_2_2>=1)&&(Turn_2_5>=1)))||((Turn_2_4>=1)&&(AskForSection_5_2>=1)))||((AskForSection_0_2>=1)&&(Turn_2_5>=1)))||((AskForSection_5_2>=1)&&(Turn_2_5>=1)))||((AskForSection_0_3>=1)&&(Turn_3_0>=1)))||((Turn_2_5>=1)&&(AskForSection_3_2>=1)))||((AskForSection_4_2>=1)&&(Turn_2_5>=1)))||((AskForSection_4_1>=1)&&(Turn_1_1>=1)))||((Turn_1_1>=1)&&(AskForSection_3_1>=1)))||((Turn_1_2>=1)&&(AskForSection_0_1>=1)))||((AskForSection_5_1>=1)&&(Turn_1_1>=1)))||((Turn_1_2>=1)&&(AskForSection_2_1>=1)))||((AskForSection_1_1>=1)&&(Turn_1_2>=1)))||((Turn_1_2>=1)&&(AskForSection_4_1>=1)))||((AskForSection_3_1>=1)&&(Turn_1_2>=1)))||((Turn_1_3>=1)&&(AskForSection_0_1>=1)))||((AskForSection_5_1>=1)&&(Turn_1_2>=1)))||((Turn_1_3>=1)&&(AskForSection_2_1>=1)))||((AskForSection_1_1>=1)&&(Turn_1_3>=1)))||((Turn_1_3>=1)&&(AskForSection_4_1>=1)))||((AskForSection_3_1>=1)&&(Turn_1_3>=1)))||((Turn_1_4>=1)&&(AskForSection_0_1>=1)))||((AskForSection_5_1>=1)&&(Turn_1_3>=1)))||((AskForSection_1_1>=1)&&(Turn_1_4>=1)))||((Turn_1_4>=1)&&(AskForSection_2_1>=1)))||((AskForSection_3_1>=1)&&(Turn_1_4>=1)))||((AskForSection_4_1>=1)&&(Turn_1_4>=1)))||((AskForSection_5_1>=1)&&(Turn_1_4>=1)))||((AskForSection_0_1>=1)&&(Turn_1_5>=1)))||((AskForSection_1_1>=1)&&(Turn_1_5>=1)))||((AskForSection_2_1>=1)&&(Turn_1_5>=1)))||((AskForSection_3_1>=1)&&(Turn_1_5>=1)))||((AskForSection_4_1>=1)&&(Turn_1_5>=1)))||((AskForSection_5_1>=1)&&(Turn_1_5>=1)))||((AskForSection_0_2>=1)&&(Turn_2_0>=1)))||((AskForSection_1_2>=1)&&(Turn_2_0>=1)))||((AskForSection_2_2>=1)&&(Turn_2_0>=1)))||((AskForSection_3_2>=1)&&(Turn_2_0>=1)))||((AskForSection_4_2>=1)&&(Turn_2_0>=1)))||((Turn_0_3>=1)&&(AskForSection_2_0>=1)))||((Turn_0_3>=1)&&(AskForSection_1_0>=1)))||((Turn_0_3>=1)&&(AskForSection_0_0>=1)))||((Turn_0_2>=1)&&(AskForSection_5_0>=1)))||((Turn_0_2>=1)&&(AskForSection_4_0>=1)))||((Turn_0_2>=1)&&(AskForSection_3_0>=1)))||((AskForSection_2_0>=1)&&(Turn_0_2>=1)))||((AskForSection_1_0>=1)&&(Turn_0_2>=1)))||((Turn_0_4>=1)&&(AskForSection_4_0>=1)))||((Turn_0_4>=1)&&(AskForSection_3_0>=1)))||((Turn_0_4>=1)&&(AskForSection_2_0>=1)))||((Turn_0_4>=1)&&(AskForSection_1_0>=1)))||((Turn_0_4>=1)&&(AskForSection_0_0>=1)))||((AskForSection_5_0>=1)&&(Turn_0_3>=1)))||((Turn_0_3>=1)&&(AskForSection_4_0>=1)))||((Turn_0_3>=1)&&(AskForSection_3_0>=1)))||((Turn_0_5>=1)&&(AskForSection_5_0>=1)))||((AskForSection_0_1>=1)&&(Turn_1_0>=1)))||((Turn_0_5>=1)&&(AskForSection_3_0>=1)))||((AskForSection_4_0>=1)&&(Turn_0_5>=1)))||((AskForSection_1_0>=1)&&(Turn_0_5>=1)))||((AskForSection_2_0>=1)&&(Turn_0_5>=1)))||((Turn_0_4>=1)&&(AskForSection_5_0>=1)))||((Turn_0_5>=1)&&(AskForSection_0_0>=1)))||((Turn_1_1>=1)&&(AskForSection_1_1>=1)))||((AskForSection_2_1>=1)&&(Turn_1_1>=1)))||((Turn_1_0>=1)&&(AskForSection_5_1>=1)))||((AskForSection_0_1>=1)&&(Turn_1_1>=1)))||((AskForSection_3_1>=1)&&(Turn_1_0>=1)))||((AskForSection_4_1>=1)&&(Turn_1_0>=1)))||((Turn_1_0>=1)&&(AskForSection_1_1>=1)))||((AskForSection_2_1>=1)&&(Turn_1_0>=1)))||((AskForSection_1_0>=1)&&(Turn_0_0>=1)))||((AskForSection_2_0>=1)&&(Turn_0_0>=1)))||((Turn_0_0>=1)&&(AskForSection_3_0>=1)))||((AskForSection_4_0>=1)&&(Turn_0_0>=1)))||((AskForSection_0_0>=1)&&(Turn_0_0>=1)))||((AskForSection_3_0>=1)&&(Turn_0_1>=1)))||((AskForSection_4_0>=1)&&(Turn_0_1>=1)))||((Turn_0_1>=1)&&(AskForSection_5_0>=1)))||((AskForSection_0_0>=1)&&(Turn_0_2>=1)))||((AskForSection_5_0>=1)&&(Turn_0_0>=1)))||((AskForSection_0_0>=1)&&(Turn_0_1>=1)))||((AskForSection_1_0>=1)&&(Turn_0_1>=1)))||((AskForSection_2_0>=1)&&(Turn_0_1>=1)))||((AskForSection_1_4>=1)&&(Turn_4_5>=1)))||((AskForSection_2_4>=1)&&(Turn_4_5>=1)))||((Turn_4_4>=1)&&(AskForSection_5_4>=1)))||((Turn_4_5>=1)&&(AskForSection_0_4>=1)))||((AskForSection_5_4>=1)&&(Turn_4_5>=1)))||((AskForSection_3_4>=1)&&(Turn_4_5>=1)))||((AskForSection_4_4>=1)&&(Turn_4_5>=1)))||((Turn_4_4>=1)&&(AskForSection_2_4>=1)))||((Turn_4_4>=1)&&(AskForSection_1_4>=1)))||((Turn_4_4>=1)&&(AskForSection_4_4>=1)))||((Turn_4_4>=1)&&(AskForSection_3_4>=1)))||((Turn_4_3>=1)&&(AskForSection_4_4>=1)))||((Turn_4_3>=1)&&(AskForSection_3_4>=1)))||((Turn_4_4>=1)&&(AskForSection_0_4>=1)))||((Turn_4_3>=1)&&(AskForSection_5_4>=1)))||((Turn_4_3>=1)&&(AskForSection_0_4>=1)))||((Turn_4_2>=1)&&(AskForSection_5_4>=1)))||((Turn_4_3>=1)&&(AskForSection_2_4>=1)))||((Turn_4_3>=1)&&(AskForSection_1_4>=1)))||((AskForSection_2_4>=1)&&(Turn_4_2>=1)))||((Turn_4_2>=1)&&(AskForSection_1_4>=1)))||((Turn_4_2>=1)&&(AskForSection_4_4>=1)))||((AskForSection_3_4>=1)&&(Turn_4_2>=1)))||((Turn_4_1>=1)&&(AskForSection_3_4>=1)))||((AskForSection_4_4>=1)&&(Turn_4_1>=1)))||((Turn_4_1>=1)&&(AskForSection_5_4>=1)))||((AskForSection_0_4>=1)&&(Turn_4_2>=1)))||((Turn_4_0>=1)&&(AskForSection_5_4>=1)))||((AskForSection_0_4>=1)&&(Turn_4_1>=1)))||((Turn_4_1>=1)&&(AskForSection_1_4>=1)))||((AskForSection_2_4>=1)&&(Turn_4_1>=1)))||((Turn_4_0>=1)&&(AskForSection_1_4>=1)))||((AskForSection_2_4>=1)&&(Turn_4_0>=1)))||((Turn_4_0>=1)&&(AskForSection_3_4>=1)))||((AskForSection_4_4>=1)&&(Turn_4_0>=1)))||((AskForSection_3_3>=1)&&(Turn_3_5>=1)))||((Turn_3_5>=1)&&(AskForSection_4_3>=1)))||((Turn_3_5>=1)&&(AskForSection_5_3>=1)))||((AskForSection_0_4>=1)&&(Turn_4_0>=1)))||((Turn_3_5>=1)&&(AskForSection_2_3>=1)))||((Turn_3_5>=1)&&(AskForSection_1_3>=1)))||((Turn_3_5>=1)&&(AskForSection_0_3>=1)))||((AskForSection_5_3>=1)&&(Turn_3_4>=1)))||((Turn_3_4>=1)&&(AskForSection_4_3>=1)))||((Turn_3_4>=1)&&(AskForSection_3_3>=1)))||((Turn_3_4>=1)&&(AskForSection_2_3>=1)))||((AskForSection_1_3>=1)&&(Turn_3_4>=1)))||((Turn_3_4>=1)&&(AskForSection_0_3>=1)))||((Turn_3_3>=1)&&(AskForSection_5_3>=1)))||((Turn_3_3>=1)&&(AskForSection_4_3>=1)))||((AskForSection_3_3>=1)&&(Turn_3_3>=1)))||((Turn_3_3>=1)&&(AskForSection_2_3>=1)))||((AskForSection_1_3>=1)&&(Turn_3_3>=1)))||((AskForSection_0_3>=1)&&(Turn_3_3>=1)))||((AskForSection_5_3>=1)&&(Turn_3_2>=1)))||((Turn_3_2>=1)&&(AskForSection_3_3>=1)))||((AskForSection_4_3>=1)&&(Turn_3_2>=1)))||((AskForSection_1_3>=1)&&(Turn_3_2>=1)))||((AskForSection_2_3>=1)&&(Turn_3_2>=1)))||((Turn_3_1>=1)&&(AskForSection_5_3>=1)))||((AskForSection_0_3>=1)&&(Turn_3_2>=1)))||((AskForSection_3_3>=1)&&(Turn_3_1>=1)))||((AskForSection_4_3>=1)&&(Turn_3_1>=1)))||((Turn_3_1>=1)&&(AskForSection_1_3>=1)))||((AskForSection_2_3>=1)&&(Turn_3_1>=1)))||((AskForSection_5_3>=1)&&(Turn_3_0>=1)))||((AskForSection_0_3>=1)&&(Turn_3_1>=1)))||((Turn_3_0>=1)&&(AskForSection_3_3>=1)))||((AskForSection_4_3>=1)&&(Turn_3_0>=1)))||((Turn_3_0>=1)&&(AskForSection_1_3>=1)))||((AskForSection_2_3>=1)&&(Turn_3_0>=1)))"))
Formula 0 simplified : !"(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((Turn_2_1>=1)&&(AskForSection_2_2>=1))||((Turn_2_1>=1)&&(AskForSection_1_2>=1)))||((AskForSection_0_2>=1)&&(Turn_2_1>=1)))||((AskForSection_5_2>=1)&&(Turn_2_0>=1)))||((Turn_2_2>=1)&&(AskForSection_0_2>=1)))||((AskForSection_5_2>=1)&&(Turn_2_1>=1)))||((Turn_2_1>=1)&&(AskForSection_4_2>=1)))||((Turn_2_1>=1)&&(AskForSection_3_2>=1)))||((Turn_2_2>=1)&&(AskForSection_4_2>=1)))||((AskForSection_3_2>=1)&&(Turn_2_2>=1)))||((Turn_2_2>=1)&&(AskForSection_2_2>=1)))||((Turn_2_2>=1)&&(AskForSection_1_2>=1)))||((Turn_2_3>=1)&&(AskForSection_2_2>=1)))||((AskForSection_1_2>=1)&&(Turn_2_3>=1)))||((Turn_2_3>=1)&&(AskForSection_0_2>=1)))||((Turn_2_2>=1)&&(AskForSection_5_2>=1)))||((AskForSection_5_2>=1)&&(Turn_2_3>=1)))||((AskForSection_0_2>=1)&&(Turn_2_4>=1)))||((Turn_2_3>=1)&&(AskForSection_3_2>=1)))||((Turn_2_3>=1)&&(AskForSection_4_2>=1)))||((AskForSection_3_2>=1)&&(Turn_2_4>=1)))||((AskForSection_4_2>=1)&&(Turn_2_4>=1)))||((Turn_2_4>=1)&&(AskForSection_1_2>=1)))||((AskForSection_2_2>=1)&&(Turn_2_4>=1)))||((AskForSection_1_2>=1)&&(Turn_2_5>=1)))||((AskForSection_2_2>=1)&&(Turn_2_5>=1)))||((Turn_2_4>=1)&&(AskForSection_5_2>=1)))||((AskForSection_0_2>=1)&&(Turn_2_5>=1)))||((AskForSection_5_2>=1)&&(Turn_2_5>=1)))||((AskForSection_0_3>=1)&&(Turn_3_0>=1)))||((Turn_2_5>=1)&&(AskForSection_3_2>=1)))||((AskForSection_4_2>=1)&&(Turn_2_5>=1)))||((AskForSection_4_1>=1)&&(Turn_1_1>=1)))||((Turn_1_1>=1)&&(AskForSection_3_1>=1)))||((Turn_1_2>=1)&&(AskForSection_0_1>=1)))||((AskForSection_5_1>=1)&&(Turn_1_1>=1)))||((Turn_1_2>=1)&&(AskForSection_2_1>=1)))||((AskForSection_1_1>=1)&&(Turn_1_2>=1)))||((Turn_1_2>=1)&&(AskForSection_4_1>=1)))||((AskForSection_3_1>=1)&&(Turn_1_2>=1)))||((Turn_1_3>=1)&&(AskForSection_0_1>=1)))||((AskForSection_5_1>=1)&&(Turn_1_2>=1)))||((Turn_1_3>=1)&&(AskForSection_2_1>=1)))||((AskForSection_1_1>=1)&&(Turn_1_3>=1)))||((Turn_1_3>=1)&&(AskForSection_4_1>=1)))||((AskForSection_3_1>=1)&&(Turn_1_3>=1)))||((Turn_1_4>=1)&&(AskForSection_0_1>=1)))||((AskForSection_5_1>=1)&&(Turn_1_3>=1)))||((AskForSection_1_1>=1)&&(Turn_1_4>=1)))||((Turn_1_4>=1)&&(AskForSection_2_1>=1)))||((AskForSection_3_1>=1)&&(Turn_1_4>=1)))||((AskForSection_4_1>=1)&&(Turn_1_4>=1)))||((AskForSection_5_1>=1)&&(Turn_1_4>=1)))||((AskForSection_0_1>=1)&&(Turn_1_5>=1)))||((AskForSection_1_1>=1)&&(Turn_1_5>=1)))||((AskForSection_2_1>=1)&&(Turn_1_5>=1)))||((AskForSection_3_1>=1)&&(Turn_1_5>=1)))||((AskForSection_4_1>=1)&&(Turn_1_5>=1)))||((AskForSection_5_1>=1)&&(Turn_1_5>=1)))||((AskForSection_0_2>=1)&&(Turn_2_0>=1)))||((AskForSection_1_2>=1)&&(Turn_2_0>=1)))||((AskForSection_2_2>=1)&&(Turn_2_0>=1)))||((AskForSection_3_2>=1)&&(Turn_2_0>=1)))||((AskForSection_4_2>=1)&&(Turn_2_0>=1)))||((Turn_0_3>=1)&&(AskForSection_2_0>=1)))||((Turn_0_3>=1)&&(AskForSection_1_0>=1)))||((Turn_0_3>=1)&&(AskForSection_0_0>=1)))||((Turn_0_2>=1)&&(AskForSection_5_0>=1)))||((Turn_0_2>=1)&&(AskForSection_4_0>=1)))||((Turn_0_2>=1)&&(AskForSection_3_0>=1)))||((AskForSection_2_0>=1)&&(Turn_0_2>=1)))||((AskForSection_1_0>=1)&&(Turn_0_2>=1)))||((Turn_0_4>=1)&&(AskForSection_4_0>=1)))||((Turn_0_4>=1)&&(AskForSection_3_0>=1)))||((Turn_0_4>=1)&&(AskForSection_2_0>=1)))||((Turn_0_4>=1)&&(AskForSection_1_0>=1)))||((Turn_0_4>=1)&&(AskForSection_0_0>=1)))||((AskForSection_5_0>=1)&&(Turn_0_3>=1)))||((Turn_0_3>=1)&&(AskForSection_4_0>=1)))||((Turn_0_3>=1)&&(AskForSection_3_0>=1)))||((Turn_0_5>=1)&&(AskForSection_5_0>=1)))||((AskForSection_0_1>=1)&&(Turn_1_0>=1)))||((Turn_0_5>=1)&&(AskForSection_3_0>=1)))||((AskForSection_4_0>=1)&&(Turn_0_5>=1)))||((AskForSection_1_0>=1)&&(Turn_0_5>=1)))||((AskForSection_2_0>=1)&&(Turn_0_5>=1)))||((Turn_0_4>=1)&&(AskForSection_5_0>=1)))||((Turn_0_5>=1)&&(AskForSection_0_0>=1)))||((Turn_1_1>=1)&&(AskForSection_1_1>=1)))||((AskForSection_2_1>=1)&&(Turn_1_1>=1)))||((Turn_1_0>=1)&&(AskForSection_5_1>=1)))||((AskForSection_0_1>=1)&&(Turn_1_1>=1)))||((AskForSection_3_1>=1)&&(Turn_1_0>=1)))||((AskForSection_4_1>=1)&&(Turn_1_0>=1)))||((Turn_1_0>=1)&&(AskForSection_1_1>=1)))||((AskForSection_2_1>=1)&&(Turn_1_0>=1)))||((AskForSection_1_0>=1)&&(Turn_0_0>=1)))||((AskForSection_2_0>=1)&&(Turn_0_0>=1)))||((Turn_0_0>=1)&&(AskForSection_3_0>=1)))||((AskForSection_4_0>=1)&&(Turn_0_0>=1)))||((AskForSection_0_0>=1)&&(Turn_0_0>=1)))||((AskForSection_3_0>=1)&&(Turn_0_1>=1)))||((AskForSection_4_0>=1)&&(Turn_0_1>=1)))||((Turn_0_1>=1)&&(AskForSection_5_0>=1)))||((AskForSection_0_0>=1)&&(Turn_0_2>=1)))||((AskForSection_5_0>=1)&&(Turn_0_0>=1)))||((AskForSection_0_0>=1)&&(Turn_0_1>=1)))||((AskForSection_1_0>=1)&&(Turn_0_1>=1)))||((AskForSection_2_0>=1)&&(Turn_0_1>=1)))||((AskForSection_1_4>=1)&&(Turn_4_5>=1)))||((AskForSection_2_4>=1)&&(Turn_4_5>=1)))||((Turn_4_4>=1)&&(AskForSection_5_4>=1)))||((Turn_4_5>=1)&&(AskForSection_0_4>=1)))||((AskForSection_5_4>=1)&&(Turn_4_5>=1)))||((AskForSection_3_4>=1)&&(Turn_4_5>=1)))||((AskForSection_4_4>=1)&&(Turn_4_5>=1)))||((Turn_4_4>=1)&&(AskForSection_2_4>=1)))||((Turn_4_4>=1)&&(AskForSection_1_4>=1)))||((Turn_4_4>=1)&&(AskForSection_4_4>=1)))||((Turn_4_4>=1)&&(AskForSection_3_4>=1)))||((Turn_4_3>=1)&&(AskForSection_4_4>=1)))||((Turn_4_3>=1)&&(AskForSection_3_4>=1)))||((Turn_4_4>=1)&&(AskForSection_0_4>=1)))||((Turn_4_3>=1)&&(AskForSection_5_4>=1)))||((Turn_4_3>=1)&&(AskForSection_0_4>=1)))||((Turn_4_2>=1)&&(AskForSection_5_4>=1)))||((Turn_4_3>=1)&&(AskForSection_2_4>=1)))||((Turn_4_3>=1)&&(AskForSection_1_4>=1)))||((AskForSection_2_4>=1)&&(Turn_4_2>=1)))||((Turn_4_2>=1)&&(AskForSection_1_4>=1)))||((Turn_4_2>=1)&&(AskForSection_4_4>=1)))||((AskForSection_3_4>=1)&&(Turn_4_2>=1)))||((Turn_4_1>=1)&&(AskForSection_3_4>=1)))||((AskForSection_4_4>=1)&&(Turn_4_1>=1)))||((Turn_4_1>=1)&&(AskForSection_5_4>=1)))||((AskForSection_0_4>=1)&&(Turn_4_2>=1)))||((Turn_4_0>=1)&&(AskForSection_5_4>=1)))||((AskForSection_0_4>=1)&&(Turn_4_1>=1)))||((Turn_4_1>=1)&&(AskForSection_1_4>=1)))||((AskForSection_2_4>=1)&&(Turn_4_1>=1)))||((Turn_4_0>=1)&&(AskForSection_1_4>=1)))||((AskForSection_2_4>=1)&&(Turn_4_0>=1)))||((Turn_4_0>=1)&&(AskForSection_3_4>=1)))||((AskForSection_4_4>=1)&&(Turn_4_0>=1)))||((AskForSection_3_3>=1)&&(Turn_3_5>=1)))||((Turn_3_5>=1)&&(AskForSection_4_3>=1)))||((Turn_3_5>=1)&&(AskForSection_5_3>=1)))||((AskForSection_0_4>=1)&&(Turn_4_0>=1)))||((Turn_3_5>=1)&&(AskForSection_2_3>=1)))||((Turn_3_5>=1)&&(AskForSection_1_3>=1)))||((Turn_3_5>=1)&&(AskForSection_0_3>=1)))||((AskForSection_5_3>=1)&&(Turn_3_4>=1)))||((Turn_3_4>=1)&&(AskForSection_4_3>=1)))||((Turn_3_4>=1)&&(AskForSection_3_3>=1)))||((Turn_3_4>=1)&&(AskForSection_2_3>=1)))||((AskForSection_1_3>=1)&&(Turn_3_4>=1)))||((Turn_3_4>=1)&&(AskForSection_0_3>=1)))||((Turn_3_3>=1)&&(AskForSection_5_3>=1)))||((Turn_3_3>=1)&&(AskForSection_4_3>=1)))||((AskForSection_3_3>=1)&&(Turn_3_3>=1)))||((Turn_3_3>=1)&&(AskForSection_2_3>=1)))||((AskForSection_1_3>=1)&&(Turn_3_3>=1)))||((AskForSection_0_3>=1)&&(Turn_3_3>=1)))||((AskForSection_5_3>=1)&&(Turn_3_2>=1)))||((Turn_3_2>=1)&&(AskForSection_3_3>=1)))||((AskForSection_4_3>=1)&&(Turn_3_2>=1)))||((AskForSection_1_3>=1)&&(Turn_3_2>=1)))||((AskForSection_2_3>=1)&&(Turn_3_2>=1)))||((Turn_3_1>=1)&&(AskForSection_5_3>=1)))||((AskForSection_0_3>=1)&&(Turn_3_2>=1)))||((AskForSection_3_3>=1)&&(Turn_3_1>=1)))||((AskForSection_4_3>=1)&&(Turn_3_1>=1)))||((Turn_3_1>=1)&&(AskForSection_1_3>=1)))||((AskForSection_2_3>=1)&&(Turn_3_1>=1)))||((AskForSection_5_3>=1)&&(Turn_3_0>=1)))||((AskForSection_0_3>=1)&&(Turn_3_1>=1)))||((Turn_3_0>=1)&&(AskForSection_3_3>=1)))||((AskForSection_4_3>=1)&&(Turn_3_0>=1)))||((Turn_3_0>=1)&&(AskForSection_1_3>=1)))||((AskForSection_2_3>=1)&&(Turn_3_0>=1)))"
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 1122
// Phase 1: matrix 1122 rows 834 cols
invariant :IsEndLoop_1_0_0 + IsEndLoop_1_1_0 + IsEndLoop_1_2_0 + IsEndLoop_1_3_0 + IsEndLoop_1_4_0 + IsEndLoop_1_0_1 + IsEndLoop_1_1_1 + IsEndLoop_1_2_1 + IsEndLoop_1_3_1 + IsEndLoop_1_4_1 + IsEndLoop_1_1_2 + IsEndLoop_1_0_2 + IsEndLoop_1_2_2 + IsEndLoop_1_3_2 + IsEndLoop_1_0_3 + IsEndLoop_1_4_2 + IsEndLoop_1_1_3 + IsEndLoop_1_2_3 + IsEndLoop_1_4_3 + IsEndLoop_1_3_3 + IsEndLoop_1_0_4 + IsEndLoop_1_2_4 + IsEndLoop_1_3_4 + IsEndLoop_1_1_4 + IsEndLoop_1_0_5 + IsEndLoop_1_4_4 + IsEndLoop_1_3_5 + IsEndLoop_1_1_5 + IsEndLoop_1_2_5 + EndTurn_1_0 + EndTurn_1_1 + IsEndLoop_1_4_5 + EndTurn_1_3 + EndTurn_1_2 + BeginLoop_1_1_0 + BeginLoop_1_0_0 + EndTurn_1_4 + BeginLoop_1_4_0 + BeginLoop_1_3_0 + BeginLoop_1_2_0 + BeginLoop_1_1_1 + BeginLoop_1_0_1 + BeginLoop_1_0_2 + BeginLoop_1_1_2 + BeginLoop_1_2_2 + BeginLoop_1_2_1 + BeginLoop_1_3_1 + BeginLoop_1_4_1 + BeginLoop_1_0_3 + BeginLoop_1_1_3 + BeginLoop_1_2_3 + BeginLoop_1_3_2 + BeginLoop_1_4_2 + BeginLoop_1_1_4 + BeginLoop_1_2_4 + BeginLoop_1_3_3 + BeginLoop_1_0_4 + BeginLoop_1_4_3 + BeginLoop_1_1_5 + BeginLoop_1_3_5 + BeginLoop_1_2_5 + BeginLoop_1_4_4 + BeginLoop_1_3_4 + BeginLoop_1_0_5 + TestAlone_1_1_0 + TestAlone_1_2_0 + TestAlone_1_0_0 + BeginLoop_1_4_5 + TestAlone_1_4_0 + TestAlone_1_3_0 + TestAlone_1_4_2 + TestAlone_1_3_2 + TestAlone_1_2_2 + TestAlone_1_1_2 + TestAlone_1_0_2 + TestAlone_1_1_4 + TestAlone_1_0_4 + TestAlone_1_4_3 + TestAlone_1_3_3 + TestAlone_1_2_3 + TestAlone_1_1_3 + TestAlone_1_0_3 + TestAlone_1_4_5 + TestAlone_1_3_5 + TestTurn_1_0 + TestTurn_1_1 + TestTurn_1_3 + TestTurn_1_2 + TestAlone_1_2_4 + TestAlone_1_4_4 + TestAlone_1_3_4 + TestAlone_1_0_5 + TestAlone_1_2_5 + TestAlone_1_1_5 + TestIdentity_1_4_0 + TestIdentity_1_0_1 + TestIdentity_1_1_1 + TestIdentity_1_2_1 + TestIdentity_1_3_1 + TestTurn_1_4 + TestIdentity_1_0_0 + TestIdentity_1_1_0 + TestIdentity_1_2_0 + TestIdentity_1_3_0 + TestIdentity_1_1_3 + TestIdentity_1_0_3 + TestIdentity_1_4_3 + TestIdentity_1_3_3 + TestIdentity_1_2_3 + TestIdentity_1_1_2 + TestIdentity_1_0_2 + TestIdentity_1_4_1 + TestIdentity_1_4_2 + TestIdentity_1_3_2 + TestIdentity_1_2_2 + TestIdentity_1_2_5 + TestIdentity_1_0_5 + TestIdentity_1_1_5 + TestIdentity_1_4_5 + TestIdentity_1_3_5 + TestIdentity_1_1_4 + TestIdentity_1_2_4 + TestIdentity_1_0_4 + TestIdentity_1_4_4 + TestIdentity_1_3_4 + AskForSection_1_3 + AskForSection_1_4 + AskForSection_1_0 + AskForSection_1_2 + AskForSection_1_1 + Idle_1 + CS_1 = 1
invariant :Turn_1_0 + Turn_1_5 + Turn_1_4 + Turn_1_1 + Turn_1_3 + Turn_1_2 = 1
invariant :Turn_0_0 + Turn_0_5 + Turn_0_4 + Turn_0_2 + Turn_0_1 + Turn_0_3 = 1
invariant :WantSection_0_F + -1'Idle_0 = 0
invariant :WantSection_1_T + Idle_1 = 1
invariant :IsEndLoop_4_0_0 + IsEndLoop_4_1_0 + IsEndLoop_4_2_0 + IsEndLoop_4_3_0 + IsEndLoop_4_4_0 + IsEndLoop_4_0_1 + IsEndLoop_4_1_1 + IsEndLoop_4_2_1 + IsEndLoop_4_3_1 + IsEndLoop_4_4_1 + IsEndLoop_4_0_2 + IsEndLoop_4_2_2 + IsEndLoop_4_1_2 + IsEndLoop_4_3_2 + IsEndLoop_4_4_2 + IsEndLoop_4_1_3 + IsEndLoop_4_0_3 + IsEndLoop_4_2_3 + IsEndLoop_4_3_3 + IsEndLoop_4_0_4 + IsEndLoop_4_4_3 + IsEndLoop_4_2_4 + IsEndLoop_4_1_4 + IsEndLoop_4_0_5 + IsEndLoop_4_3_4 + IsEndLoop_4_4_4 + IsEndLoop_4_2_5 + IsEndLoop_4_3_5 + IsEndLoop_4_1_5 + EndTurn_4_0 + IsEndLoop_4_4_5 + EndTurn_4_3 + EndTurn_4_2 + EndTurn_4_1 + BeginLoop_4_1_0 + BeginLoop_4_0_0 + EndTurn_4_4 + BeginLoop_4_3_0 + BeginLoop_4_2_0 + BeginLoop_4_1_1 + BeginLoop_4_0_1 + BeginLoop_4_4_0 + BeginLoop_4_0_2 + BeginLoop_4_1_2 + BeginLoop_4_2_1 + BeginLoop_4_3_1 + BeginLoop_4_4_1 + BeginLoop_4_0_3 + BeginLoop_4_1_3 + BeginLoop_4_2_3 + BeginLoop_4_2_2 + BeginLoop_4_3_2 + BeginLoop_4_4_2 + BeginLoop_4_1_4 + BeginLoop_4_0_4 + BeginLoop_4_2_4 + BeginLoop_4_3_3 + BeginLoop_4_4_3 + BeginLoop_4_1_5 + BeginLoop_4_2_5 + BeginLoop_4_3_4 + BeginLoop_4_0_5 + BeginLoop_4_4_4 + TestAlone_4_0_0 + TestAlone_4_1_0 + BeginLoop_4_3_5 + BeginLoop_4_4_5 + TestAlone_4_2_1 + TestAlone_4_0_1 + TestAlone_4_1_1 + TestAlone_4_4_0 + TestAlone_4_2_0 + TestAlone_4_3_0 + TestAlone_4_4_2 + TestAlone_4_3_2 + TestAlone_4_2_2 + TestAlone_4_1_2 + TestAlone_4_0_2 + TestAlone_4_4_1 + TestAlone_4_3_1 + TestAlone_4_4_3 + TestAlone_4_3_3 + TestAlone_4_2_3 + TestAlone_4_1_3 + TestAlone_4_0_3 + TestAlone_4_3_5 + TestAlone_4_2_5 + TestTurn_4_0 + TestAlone_4_4_5 + TestTurn_4_1 + TestTurn_4_2 + TestAlone_4_0_5 + TestAlone_4_1_5 + TestIdentity_4_4_0 + TestIdentity_4_0_1 + TestIdentity_4_1_1 + TestIdentity_4_2_1 + TestIdentity_4_3_1 + TestTurn_4_3 + TestTurn_4_4 + TestIdentity_4_0_0 + TestIdentity_4_1_0 + TestIdentity_4_2_0 + TestIdentity_4_3_0 + TestIdentity_4_1_3 + TestIdentity_4_0_3 + TestIdentity_4_4_2 + TestIdentity_4_4_3 + TestIdentity_4_3_3 + TestIdentity_4_2_3 + TestIdentity_4_1_2 + TestIdentity_4_0_2 + TestIdentity_4_4_1 + TestIdentity_4_3_2 + TestIdentity_4_2_2 + TestIdentity_4_1_5 + TestIdentity_4_2_5 + TestIdentity_4_0_5 + TestIdentity_4_4_5 + TestIdentity_4_3_5 + TestIdentity_4_1_4 + TestIdentity_4_0_4 + TestIdentity_4_4_4 + TestIdentity_4_2_4 + TestIdentity_4_3_4 + AskForSection_4_3 + AskForSection_4_2 + AskForSection_4_4 + AskForSection_4_0 + AskForSection_4_1 + Idle_4 + CS_4 = 1
invariant :Turn_4_4 + Turn_4_3 + Turn_4_5 + Turn_4_1 + Turn_4_0 + Turn_4_2 = 1
invariant :WantSection_3_T + Idle_3 = 1
invariant :WantSection_2_T + Idle_2 = 1
invariant :WantSection_5_T + Idle_5 = 1
invariant :WantSection_4_F + -1'Idle_4 = 0
invariant :IsEndLoop_0_0_0 + IsEndLoop_0_1_0 + IsEndLoop_0_2_0 + IsEndLoop_0_3_0 + IsEndLoop_0_4_0 + IsEndLoop_0_0_1 + IsEndLoop_0_1_1 + IsEndLoop_0_2_1 + IsEndLoop_0_3_1 + IsEndLoop_0_4_1 + IsEndLoop_0_0_2 + IsEndLoop_0_1_2 + IsEndLoop_0_2_2 + IsEndLoop_0_4_2 + IsEndLoop_0_3_2 + IsEndLoop_0_0_3 + IsEndLoop_0_1_3 + IsEndLoop_0_3_3 + IsEndLoop_0_2_3 + IsEndLoop_0_4_3 + IsEndLoop_0_0_4 + IsEndLoop_0_3_4 + IsEndLoop_0_1_4 + IsEndLoop_0_2_4 + IsEndLoop_0_0_5 + IsEndLoop_0_1_5 + IsEndLoop_0_4_4 + IsEndLoop_0_3_5 + IsEndLoop_0_2_5 + EndTurn_0_1 + IsEndLoop_0_4_5 + EndTurn_0_0 + EndTurn_0_4 + EndTurn_0_3 + EndTurn_0_2 + BeginLoop_0_1_0 + BeginLoop_0_0_0 + BeginLoop_0_4_0 + BeginLoop_0_3_0 + BeginLoop_0_2_0 + BeginLoop_0_2_1 + BeginLoop_0_1_1 + BeginLoop_0_0_1 + BeginLoop_0_0_2 + BeginLoop_0_1_2 + BeginLoop_0_2_2 + BeginLoop_0_3_1 + BeginLoop_0_4_1 + BeginLoop_0_1_3 + BeginLoop_0_2_3 + BeginLoop_0_3_2 + BeginLoop_0_4_2 + BeginLoop_0_0_3 + BeginLoop_0_1_4 + BeginLoop_0_3_4 + BeginLoop_0_2_4 + BeginLoop_0_4_3 + BeginLoop_0_3_3 + BeginLoop_0_0_4 + BeginLoop_0_2_5 + BeginLoop_0_1_5 + BeginLoop_0_3_5 + BeginLoop_0_4_4 + BeginLoop_0_0_5 + BeginLoop_0_4_5 + TestAlone_0_2_1 + TestAlone_0_3_1 + TestAlone_0_1_1 + TestAlone_0_0_1 + TestAlone_0_4_2 + TestAlone_0_3_2 + TestAlone_0_2_2 + TestAlone_0_1_2 + TestAlone_0_0_2 + TestAlone_0_4_1 + TestAlone_0_1_4 + TestAlone_0_0_4 + TestAlone_0_4_3 + TestAlone_0_3_3 + TestAlone_0_2_3 + TestAlone_0_1_3 + TestAlone_0_0_3 + TestAlone_0_4_5 + TestAlone_0_3_5 + TestTurn_0_0 + TestTurn_0_2 + TestTurn_0_1 + TestTurn_0_3 + TestAlone_0_2_4 + TestAlone_0_4_4 + TestAlone_0_3_4 + TestAlone_0_1_5 + TestAlone_0_0_5 + TestAlone_0_2_5 + TestIdentity_0_4_0 + TestIdentity_0_0_1 + TestIdentity_0_1_1 + TestIdentity_0_2_1 + TestIdentity_0_3_1 + TestIdentity_0_4_1 + TestTurn_0_4 + TestIdentity_0_0_0 + TestIdentity_0_1_0 + TestIdentity_0_2_0 + TestIdentity_0_3_0 + TestIdentity_0_2_3 + TestIdentity_0_1_3 + TestIdentity_0_0_3 + TestIdentity_0_4_3 + TestIdentity_0_3_3 + TestIdentity_0_1_2 + TestIdentity_0_0_2 + TestIdentity_0_4_2 + TestIdentity_0_3_2 + TestIdentity_0_2_2 + TestIdentity_0_2_5 + TestIdentity_0_1_5 + TestIdentity_0_3_5 + TestIdentity_0_4_5 + TestIdentity_0_2_4 + TestIdentity_0_0_4 + TestIdentity_0_1_4 + TestIdentity_0_4_4 + TestIdentity_0_0_5 + TestIdentity_0_3_4 + AskForSection_0_3 + CS_0 + AskForSection_0_4 + AskForSection_0_1 + AskForSection_0_0 + AskForSection_0_2 + Idle_0 = 1
invariant :IsEndLoop_5_0_0 + IsEndLoop_5_1_0 + IsEndLoop_5_2_0 + IsEndLoop_5_3_0 + IsEndLoop_5_4_0 + IsEndLoop_5_0_1 + IsEndLoop_5_1_1 + IsEndLoop_5_2_1 + IsEndLoop_5_3_1 + IsEndLoop_5_4_1 + IsEndLoop_5_0_2 + IsEndLoop_5_1_2 + IsEndLoop_5_3_2 + IsEndLoop_5_2_2 + IsEndLoop_5_4_2 + IsEndLoop_5_0_3 + IsEndLoop_5_2_3 + IsEndLoop_5_1_3 + IsEndLoop_5_3_3 + IsEndLoop_5_4_3 + IsEndLoop_5_2_4 + IsEndLoop_5_0_4 + IsEndLoop_5_1_4 + IsEndLoop_5_4_4 + IsEndLoop_5_0_5 + IsEndLoop_5_3_4 + IsEndLoop_5_2_5 + IsEndLoop_5_1_5 + EndTurn_5_0 + IsEndLoop_5_3_5 + IsEndLoop_5_4_5 + EndTurn_5_3 + EndTurn_5_2 + EndTurn_5_1 + BeginLoop_5_0_0 + EndTurn_5_4 + BeginLoop_5_3_0 + BeginLoop_5_2_0 + BeginLoop_5_1_0 + BeginLoop_5_1_1 + BeginLoop_5_0_1 + BeginLoop_5_4_0 + BeginLoop_5_4_1 + BeginLoop_5_0_2 + BeginLoop_5_1_2 + BeginLoop_5_2_1 + BeginLoop_5_3_1 + BeginLoop_5_0_3 + BeginLoop_5_1_3 + BeginLoop_5_2_2 + BeginLoop_5_3_2 + BeginLoop_5_4_2 + BeginLoop_5_0_4 + BeginLoop_5_2_4 + BeginLoop_5_1_4 + BeginLoop_5_3_3 + BeginLoop_5_2_3 + BeginLoop_5_4_3 + BeginLoop_5_1_5 + BeginLoop_5_0_5 + BeginLoop_5_2_5 + BeginLoop_5_3_4 + BeginLoop_5_4_4 + TestAlone_5_0_0 + TestAlone_5_1_0 + BeginLoop_5_4_5 + BeginLoop_5_3_5 + TestAlone_5_2_1 + TestAlone_5_0_1 + TestAlone_5_1_1 + TestAlone_5_3_0 + TestAlone_5_4_0 + TestAlone_5_2_0 + TestAlone_5_4_2 + TestAlone_5_3_2 + TestAlone_5_2_2 + TestAlone_5_1_2 + TestAlone_5_0_2 + TestAlone_5_4_1 + TestAlone_5_3_1 + TestAlone_5_0_4 + TestAlone_5_4_3 + TestAlone_5_3_3 + TestAlone_5_2_3 + TestAlone_5_1_3 + TestAlone_5_0_3 + TestTurn_5_1 + TestTurn_5_0 + TestTurn_5_2 + TestAlone_5_2_4 + TestAlone_5_1_4 + TestAlone_5_3_4 + TestAlone_5_4_4 + TestIdentity_5_3_0 + TestIdentity_5_4_0 + TestIdentity_5_0_1 + TestIdentity_5_1_1 + TestIdentity_5_2_1 + TestIdentity_5_3_1 + TestTurn_5_3 + TestTurn_5_4 + TestIdentity_5_0_0 + TestIdentity_5_1_0 + TestIdentity_5_2_0 + TestIdentity_5_1_3 + TestIdentity_5_0_3 + TestIdentity_5_4_2 + TestIdentity_5_3_3 + TestIdentity_5_2_3 + TestIdentity_5_0_2 + TestIdentity_5_4_1 + TestIdentity_5_3_2 + TestIdentity_5_2_2 + TestIdentity_5_1_2 + TestIdentity_5_1_5 + TestIdentity_5_0_5 + TestIdentity_5_4_5 + TestIdentity_5_2_5 + TestIdentity_5_3_5 + TestIdentity_5_1_4 + TestIdentity_5_4_3 + TestIdentity_5_0_4 + TestIdentity_5_3_4 + TestIdentity_5_4_4 + TestIdentity_5_2_4 + AskForSection_5_2 + AskForSection_5_4 + AskForSection_5_3 + AskForSection_5_0 + Idle_5 + AskForSection_5_1 + CS_5 = 1
invariant :WantSection_5_F + -1'Idle_5 = 0
invariant :WantSection_2_F + -1'Idle_2 = 0
invariant :Turn_3_4 + Turn_3_5 + Turn_3_1 + Turn_3_0 + Turn_3_3 + Turn_3_2 = 1
invariant :WantSection_1_F + -1'Idle_1 = 0
invariant :WantSection_4_T + Idle_4 = 1
invariant :IsEndLoop_3_0_0 + IsEndLoop_3_1_0 + IsEndLoop_3_2_0 + IsEndLoop_3_3_0 + IsEndLoop_3_4_0 + IsEndLoop_3_0_1 + IsEndLoop_3_1_1 + IsEndLoop_3_2_1 + IsEndLoop_3_3_1 + IsEndLoop_3_4_1 + IsEndLoop_3_0_2 + IsEndLoop_3_2_2 + IsEndLoop_3_1_2 + IsEndLoop_3_3_2 + IsEndLoop_3_4_2 + IsEndLoop_3_1_3 + IsEndLoop_3_0_3 + IsEndLoop_3_2_3 + IsEndLoop_3_3_3 + IsEndLoop_3_0_4 + IsEndLoop_3_4_3 + IsEndLoop_3_2_4 + IsEndLoop_3_1_4 + IsEndLoop_3_0_5 + IsEndLoop_3_3_4 + IsEndLoop_3_4_4 + IsEndLoop_3_2_5 + IsEndLoop_3_3_5 + IsEndLoop_3_1_5 + EndTurn_3_0 + IsEndLoop_3_4_5 + EndTurn_3_3 + EndTurn_3_2 + EndTurn_3_1 + BeginLoop_3_1_0 + BeginLoop_3_0_0 + EndTurn_3_4 + BeginLoop_3_3_0 + BeginLoop_3_2_0 + BeginLoop_3_1_1 + BeginLoop_3_0_1 + BeginLoop_3_4_0 + BeginLoop_3_0_2 + BeginLoop_3_1_2 + BeginLoop_3_2_1 + BeginLoop_3_3_1 + BeginLoop_3_4_1 + BeginLoop_3_0_3 + BeginLoop_3_1_3 + BeginLoop_3_2_3 + BeginLoop_3_2_2 + BeginLoop_3_3_2 + BeginLoop_3_4_2 + BeginLoop_3_1_4 + BeginLoop_3_0_4 + BeginLoop_3_2_4 + BeginLoop_3_3_3 + BeginLoop_3_4_3 + BeginLoop_3_1_5 + BeginLoop_3_2_5 + BeginLoop_3_3_4 + BeginLoop_3_0_5 + BeginLoop_3_4_4 + TestAlone_3_1_0 + TestAlone_3_0_0 + BeginLoop_3_3_5 + BeginLoop_3_4_5 + TestAlone_3_2_1 + TestAlone_3_3_1 + TestAlone_3_0_1 + TestAlone_3_1_1 + TestAlone_3_4_0 + TestAlone_3_2_0 + TestAlone_3_3_0 + TestAlone_3_4_2 + TestAlone_3_3_2 + TestAlone_3_2_2 + TestAlone_3_1_2 + TestAlone_3_0_2 + TestAlone_3_4_1 + TestAlone_3_0_4 + TestAlone_3_3_5 + TestTurn_3_0 + TestAlone_3_4_5 + TestTurn_3_1 + TestTurn_3_2 + TestAlone_3_2_4 + TestAlone_3_1_4 + TestAlone_3_3_4 + TestAlone_3_0_5 + TestAlone_3_4_4 + TestAlone_3_2_5 + TestAlone_3_1_5 + TestIdentity_3_4_0 + TestIdentity_3_0_1 + TestIdentity_3_1_1 + TestIdentity_3_2_1 + TestIdentity_3_3_1 + TestTurn_3_3 + TestTurn_3_4 + TestIdentity_3_0_0 + TestIdentity_3_1_0 + TestIdentity_3_2_0 + TestIdentity_3_3_0 + TestIdentity_3_1_3 + TestIdentity_3_0_3 + TestIdentity_3_4_2 + TestIdentity_3_4_3 + TestIdentity_3_3_3 + TestIdentity_3_2_3 + TestIdentity_3_1_2 + TestIdentity_3_0_2 + TestIdentity_3_4_1 + TestIdentity_3_3_2 + TestIdentity_3_2_2 + TestIdentity_3_1_5 + TestIdentity_3_2_5 + TestIdentity_3_0_5 + TestIdentity_3_4_5 + TestIdentity_3_3_5 + TestIdentity_3_1_4 + TestIdentity_3_0_4 + TestIdentity_3_4_4 + TestIdentity_3_2_4 + TestIdentity_3_3_4 + AskForSection_3_3 + AskForSection_3_2 + AskForSection_3_4 + AskForSection_3_0 + AskForSection_3_1 + Idle_3 + CS_3 = 1
invariant :WantSection_0_T + Idle_0 = 1
invariant :IsEndLoop_2_0_0 + IsEndLoop_2_1_0 + IsEndLoop_2_2_0 + IsEndLoop_2_3_0 + IsEndLoop_2_4_0 + IsEndLoop_2_0_1 + IsEndLoop_2_1_1 + IsEndLoop_2_2_1 + IsEndLoop_2_3_1 + IsEndLoop_2_4_1 + IsEndLoop_2_1_2 + IsEndLoop_2_0_2 + IsEndLoop_2_2_2 + IsEndLoop_2_3_2 + IsEndLoop_2_0_3 + IsEndLoop_2_4_2 + IsEndLoop_2_1_3 + IsEndLoop_2_2_3 + IsEndLoop_2_4_3 + IsEndLoop_2_3_3 + IsEndLoop_2_0_4 + IsEndLoop_2_2_4 + IsEndLoop_2_3_4 + IsEndLoop_2_1_4 + IsEndLoop_2_0_5 + IsEndLoop_2_4_4 + IsEndLoop_2_3_5 + IsEndLoop_2_1_5 + IsEndLoop_2_2_5 + EndTurn_2_0 + EndTurn_2_1 + IsEndLoop_2_4_5 + EndTurn_2_3 + EndTurn_2_2 + BeginLoop_2_1_0 + BeginLoop_2_0_0 + EndTurn_2_4 + BeginLoop_2_4_0 + BeginLoop_2_3_0 + BeginLoop_2_2_0 + BeginLoop_2_1_1 + BeginLoop_2_0_1 + BeginLoop_2_0_2 + BeginLoop_2_1_2 + BeginLoop_2_2_2 + BeginLoop_2_2_1 + BeginLoop_2_3_1 + BeginLoop_2_4_1 + BeginLoop_2_0_3 + BeginLoop_2_1_3 + BeginLoop_2_2_3 + BeginLoop_2_3_2 + BeginLoop_2_4_2 + BeginLoop_2_1_4 + BeginLoop_2_2_4 + BeginLoop_2_3_3 + BeginLoop_2_0_4 + BeginLoop_2_4_3 + BeginLoop_2_1_5 + BeginLoop_2_3_5 + BeginLoop_2_2_5 + BeginLoop_2_4_4 + BeginLoop_2_3_4 + BeginLoop_2_0_5 + TestAlone_2_1_0 + TestAlone_2_0_0 + BeginLoop_2_4_5 + TestAlone_2_2_1 + TestAlone_2_3_1 + TestAlone_2_1_1 + TestAlone_2_4_0 + TestAlone_2_0_1 + TestAlone_2_2_0 + TestAlone_2_3_0 + TestAlone_2_4_1 + TestAlone_2_0_4 + TestAlone_2_4_3 + TestAlone_2_3_3 + TestAlone_2_2_3 + TestAlone_2_1_3 + TestAlone_2_0_3 + TestAlone_2_3_5 + TestTurn_2_0 + TestAlone_2_4_5 + TestTurn_2_1 + TestTurn_2_3 + TestTurn_2_2 + TestAlone_2_2_4 + TestAlone_2_1_4 + TestAlone_2_4_4 + TestAlone_2_3_4 + TestAlone_2_0_5 + TestAlone_2_2_5 + TestAlone_2_1_5 + TestIdentity_2_4_0 + TestIdentity_2_0_1 + TestIdentity_2_1_1 + TestIdentity_2_2_1 + TestIdentity_2_3_1 + TestTurn_2_4 + TestIdentity_2_0_0 + TestIdentity_2_1_0 + TestIdentity_2_2_0 + TestIdentity_2_3_0 + TestIdentity_2_1_3 + TestIdentity_2_0_3 + TestIdentity_2_4_3 + TestIdentity_2_3_3 + TestIdentity_2_2_3 + TestIdentity_2_1_2 + TestIdentity_2_0_2 + TestIdentity_2_4_1 + TestIdentity_2_4_2 + TestIdentity_2_3_2 + TestIdentity_2_2_2 + TestIdentity_2_2_5 + TestIdentity_2_0_5 + TestIdentity_2_1_5 + TestIdentity_2_4_5 + TestIdentity_2_3_5 + TestIdentity_2_1_4 + TestIdentity_2_2_4 + TestIdentity_2_0_4 + TestIdentity_2_4_4 + TestIdentity_2_3_4 + AskForSection_2_3 + AskForSection_2_4 + AskForSection_2_0 + AskForSection_2_2 + AskForSection_2_1 + Idle_2 + CS_2 = 1
invariant :WantSection_3_F + -1'Idle_3 = 0
invariant :Turn_2_0 + Turn_2_4 + Turn_2_5 + Turn_2_1 + Turn_2_3 + Turn_2_2 = 1
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O2, model.c], workingDir=/home/mcc/execution]
Compilation finished in 12191 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 327 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, (LTLAP0==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 41727 ms.
FORMULA Peterson-PT-5-LTLFireability-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X(<>([]([](X((LTLAP1==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 8250 ms.
FORMULA Peterson-PT-5-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, []([]([](<>((LTLAP2==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 38814 ms.
FORMULA Peterson-PT-5-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X(<>([](<>(X((LTLAP0==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 10068 ms.
FORMULA Peterson-PT-5-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, []([]([](X([]((LTLAP3==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 59087 ms.
FORMULA Peterson-PT-5-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, ((LTLAP4==true))U(<>(((LTLAP5==true))U((LTLAP6==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 36914 ms.
FORMULA Peterson-PT-5-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X(X(<>([](<>((LTLAP3==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 7567 ms.
FORMULA Peterson-PT-5-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, (LTLAP7==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 19420 ms.
FORMULA Peterson-PT-5-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, [](((LTLAP8==true))U(<>(<>((LTLAP9==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 22409 ms.
FORMULA Peterson-PT-5-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X([]((LTLAP10==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 9447 ms.
FORMULA Peterson-PT-5-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, ((<>((LTLAP11==true)))U(X((LTLAP12==true))))U((LTLAP13==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1459 ms.
FORMULA Peterson-PT-5-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, []((LTLAP14==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 33639 ms.
FORMULA Peterson-PT-5-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, (LTLAP15==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 37352 ms.
FORMULA Peterson-PT-5-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, <>([](X(<>(<>((LTLAP15==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 6572 ms.
FORMULA Peterson-PT-5-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, (LTLAP16==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 27517 ms.
FORMULA Peterson-PT-5-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, (LTLAP17==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 33104 ms.
FORMULA Peterson-PT-5-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1552939016147

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ LTLFireability = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Mar 18, 2019 7:46:46 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Mar 18, 2019 7:46:46 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Mar 18, 2019 7:46:46 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 148 ms
Mar 18, 2019 7:46:46 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 834 places.
Mar 18, 2019 7:46:46 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 1242 transitions.
Mar 18, 2019 7:46:46 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 38 ms
Mar 18, 2019 7:46:47 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 194 ms
Mar 18, 2019 7:46:47 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 5 ms
Mar 18, 2019 7:46:47 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 5 ms
Mar 18, 2019 7:46:47 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1242 transitions.
Mar 18, 2019 7:46:48 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 23 place invariants in 350 ms
Mar 18, 2019 7:46:49 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 834 variables to be positive in 1466 ms
Mar 18, 2019 7:46:49 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 1242 transitions.
Mar 18, 2019 7:46:49 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/1242 took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 18, 2019 7:46:49 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 51 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 18, 2019 7:46:49 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 1242 transitions.
Mar 18, 2019 7:46:49 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 33 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 18, 2019 7:47:30 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 1242 transitions.
Mar 18, 2019 7:47:31 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/1242) took 158 ms. Total solver calls (SAT/UNSAT): 206(0/206)
Mar 18, 2019 7:47:36 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(4/1242) took 5692 ms. Total solver calls (SAT/UNSAT): 1030(0/1030)
Mar 18, 2019 7:47:42 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(6/1242) took 11434 ms. Total solver calls (SAT/UNSAT): 1441(0/1441)
Mar 18, 2019 7:47:46 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(7/1242) took 16009 ms. Total solver calls (SAT/UNSAT): 1646(0/1646)
Mar 18, 2019 7:47:51 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(8/1242) took 20443 ms. Total solver calls (SAT/UNSAT): 1876(25/1851)
Mar 18, 2019 7:47:57 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(9/1242) took 26051 ms. Total solver calls (SAT/UNSAT): 2081(25/2056)
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown' twice, overapproximating result to 1.
Mar 18, 2019 7:47:59 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 28168 ms. Total solver calls (SAT/UNSAT): 2140(26/2114)
Mar 18, 2019 7:47:59 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 1242 transitions.
Mar 18, 2019 7:50:09 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 129333 ms. Total solver calls (SAT/UNSAT): 6038(0/6038)
Mar 18, 2019 7:50:09 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 202046ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Peterson-PT-5"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3954"
echo " Executing tool itstools"
echo " Input is Peterson-PT-5, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r107-oct2-155272231200556"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Peterson-PT-5.tgz
mv Peterson-PT-5 execution
cd execution
if [ "LTLFireability" = "GlobalProperties" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
if [ "LTLFireability" = "UpperBounds" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;