Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fko/mcc2019-input.r107-oct2-155272231000448.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fko/mcc2019-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..........................................................................
=====================================================================
Generated by BenchKit 2-3954
Executing tool itstools
Input is PermAdmissibility-PT-10, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r107-oct2-155272231000448
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 960K
-rw-r--r-- 1 mcc users 5.9K Feb 12 04:11 CTLCardinality.txt
-rw-r--r-- 1 mcc users 30K Feb 12 04:11 CTLCardinality.xml
-rw-r--r-- 1 mcc users 26K Feb 8 03:14 CTLFireability.txt
-rw-r--r-- 1 mcc users 100K Feb 8 03:14 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 10 17:31 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K Mar 10 17:31 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 110 Feb 24 15:05 GlobalProperties.txt
-rw-r--r-- 1 mcc users 348 Feb 24 15:05 GlobalProperties.xml
-rw-r--r-- 1 mcc users 2.9K Feb 5 00:23 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K Feb 5 00:23 LTLCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 4 22:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 44K Feb 4 22:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 6.0K Feb 4 07:56 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 29K Feb 4 07:56 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 32K Feb 1 02:10 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 117K Feb 1 02:10 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 4 22:22 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.3K Feb 4 22:22 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Jan 29 09:34 equiv_col
-rw-r--r-- 1 mcc users 3 Jan 29 09:34 instance
-rw-r--r-- 1 mcc users 6 Jan 29 09:34 iscolored
-rw-r--r-- 1 mcc users 484K Mar 10 17:31 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-PT-10-LTLFireability-00
FORMULA_NAME PermAdmissibility-PT-10-LTLFireability-01
FORMULA_NAME PermAdmissibility-PT-10-LTLFireability-02
FORMULA_NAME PermAdmissibility-PT-10-LTLFireability-03
FORMULA_NAME PermAdmissibility-PT-10-LTLFireability-04
FORMULA_NAME PermAdmissibility-PT-10-LTLFireability-05
FORMULA_NAME PermAdmissibility-PT-10-LTLFireability-06
FORMULA_NAME PermAdmissibility-PT-10-LTLFireability-07
FORMULA_NAME PermAdmissibility-PT-10-LTLFireability-08
FORMULA_NAME PermAdmissibility-PT-10-LTLFireability-09
FORMULA_NAME PermAdmissibility-PT-10-LTLFireability-10
FORMULA_NAME PermAdmissibility-PT-10-LTLFireability-11
FORMULA_NAME PermAdmissibility-PT-10-LTLFireability-12
FORMULA_NAME PermAdmissibility-PT-10-LTLFireability-13
FORMULA_NAME PermAdmissibility-PT-10-LTLFireability-14
FORMULA_NAME PermAdmissibility-PT-10-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1552931313077

Working with output stream class java.io.PrintStream
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903111103/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903111103/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !(((X(F(G("((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((aux13_1>=1)&&(c17>=1))&&(aux15_2>=1))||(((aux13_1>=1)&&(c17>=1))&&(aux15_1>=1)))||(((aux13_1>=1)&&(c17>=1))&&(aux15_4>=1)))||(((aux13_1>=1)&&(c17>=1))&&(aux15_3>=1)))||(((c17>=1)&&(aux13_0>=1))&&(aux15_6>=1)))||(((aux15_5>=1)&&(aux13_0>=1))&&(c17>=1)))||(((aux15_0>=1)&&(c17>=1))&&(aux13_1>=1)))||(((c17>=1)&&(aux13_0>=1))&&(aux15_7>=1)))||(((aux15_2>=1)&&(aux13_2>=1))&&(c17>=1)))||(((aux15_1>=1)&&(aux13_2>=1))&&(c17>=1)))||(((c17>=1)&&(aux13_2>=1))&&(aux15_4>=1)))||(((aux15_3>=1)&&(aux13_2>=1))&&(c17>=1)))||(((aux15_6>=1)&&(c17>=1))&&(aux13_1>=1)))||(((aux13_1>=1)&&(c17>=1))&&(aux15_5>=1)))||(((c17>=1)&&(aux13_2>=1))&&(aux15_0>=1)))||(((c17>=1)&&(aux13_1>=1))&&(aux15_7>=1)))||(((aux15_1>=1)&&(c17>=1))&&(aux13_0>=1)))||(((c17>=1)&&(aux13_0>=1))&&(aux15_2>=1)))||(((aux15_3>=1)&&(c17>=1))&&(aux13_0>=1)))||(((aux15_4>=1)&&(aux13_0>=1))&&(c17>=1)))||(((aux13_0>=1)&&(c17>=1))&&(aux15_0>=1)))||(((aux13_5>=1)&&(c17>=1))&&(aux15_7>=1)))||(((aux15_0>=1)&&(aux13_6>=1))&&(c17>=1)))||(((c17>=1)&&(aux13_5>=1))&&(aux15_5>=1)))||(((aux15_6>=1)&&(aux13_5>=1))&&(c17>=1)))||(((aux15_3>=1)&&(c17>=1))&&(aux13_6>=1)))||(((aux15_4>=1)&&(aux13_6>=1))&&(c17>=1)))||(((aux15_1>=1)&&(c17>=1))&&(aux13_6>=1)))||(((c17>=1)&&(aux13_6>=1))&&(aux15_2>=1)))||(((aux15_7>=1)&&(c17>=1))&&(aux13_4>=1)))||(((c17>=1)&&(aux13_5>=1))&&(aux15_0>=1)))||(((aux13_4>=1)&&(c17>=1))&&(aux15_5>=1)))||(((c17>=1)&&(aux13_4>=1))&&(aux15_6>=1)))||(((aux15_3>=1)&&(aux13_5>=1))&&(c17>=1)))||(((aux15_4>=1)&&(c17>=1))&&(aux13_5>=1)))||(((aux15_1>=1)&&(aux13_5>=1))&&(c17>=1)))||(((aux13_5>=1)&&(c17>=1))&&(aux15_2>=1)))||(((aux15_0>=1)&&(c17>=1))&&(aux13_4>=1)))||(((aux15_7>=1)&&(c17>=1))&&(aux13_3>=1)))||(((aux15_6>=1)&&(c17>=1))&&(aux13_3>=1)))||(((aux15_5>=1)&&(aux13_3>=1))&&(c17>=1)))||(((aux13_4>=1)&&(c17>=1))&&(aux15_4>=1)))||(((c17>=1)&&(aux13_4>=1))&&(aux15_3>=1)))||(((c17>=1)&&(aux13_4>=1))&&(aux15_2>=1)))||(((c17>=1)&&(aux13_4>=1))&&(aux15_1>=1)))||(((aux15_0>=1)&&(aux13_3>=1))&&(c17>=1)))||(((aux13_2>=1)&&(c17>=1))&&(aux15_7>=1)))||(((aux15_6>=1)&&(aux13_2>=1))&&(c17>=1)))||(((aux15_5>=1)&&(c17>=1))&&(aux13_2>=1)))||(((aux15_4>=1)&&(aux13_3>=1))&&(c17>=1)))||(((c17>=1)&&(aux13_3>=1))&&(aux15_3>=1)))||(((aux15_2>=1)&&(c17>=1))&&(aux13_3>=1)))||(((c17>=1)&&(aux13_3>=1))&&(aux15_1>=1)))||(((c17>=1)&&(aux13_7>=1))&&(aux15_6>=1)))||(((aux13_7>=1)&&(c17>=1))&&(aux15_5>=1)))||(((c17>=1)&&(aux13_7>=1))&&(aux15_7>=1)))||(((aux15_6>=1)&&(aux13_6>=1))&&(c17>=1)))||(((aux15_5>=1)&&(aux13_6>=1))&&(c17>=1)))||(((aux15_0>=1)&&(aux13_7>=1))&&(c17>=1)))||(((aux15_7>=1)&&(aux13_6>=1))&&(c17>=1)))||(((c17>=1)&&(aux13_7>=1))&&(aux15_2>=1)))||(((aux15_1>=1)&&(c17>=1))&&(aux13_7>=1)))||(((aux15_4>=1)&&(aux13_7>=1))&&(c17>=1)))||(((aux15_3>=1)&&(c17>=1))&&(aux13_7>=1)))"))))U(X(("((((((in1_1>=1)&&(c6>=1))&&(in3_4>=1))||(((in3_5>=1)&&(in1_0>=1))&&(c6>=1)))||(((in1_1>=1)&&(c6>=1))&&(in3_5>=1)))||(((in1_0>=1)&&(c6>=1))&&(in3_4>=1)))")U("((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((c14>=1)&&(aux11_4>=1))&&(aux9_0>=1))||(((aux11_3>=1)&&(aux9_0>=1))&&(c14>=1)))||(((aux11_2>=1)&&(aux9_0>=1))&&(c14>=1)))||(((aux11_1>=1)&&(aux9_0>=1))&&(c14>=1)))||(((c14>=1)&&(aux9_0>=1))&&(aux11_0>=1)))||(((aux11_7>=1)&&(aux9_4>=1))&&(c14>=1)))||(((aux11_0>=1)&&(aux9_5>=1))&&(c14>=1)))||(((aux9_4>=1)&&(aux11_5>=1))&&(c14>=1)))||(((aux9_4>=1)&&(aux11_6>=1))&&(c14>=1)))||(((c14>=1)&&(aux9_5>=1))&&(aux11_3>=1)))||(((aux9_5>=1)&&(aux11_4>=1))&&(c14>=1)))||(((aux11_1>=1)&&(aux9_5>=1))&&(c14>=1)))||(((aux9_5>=1)&&(aux11_2>=1))&&(c14>=1)))||(((aux11_7>=1)&&(aux9_5>=1))&&(c14>=1)))||(((aux9_6>=1)&&(c14>=1))&&(aux11_0>=1)))||(((c14>=1)&&(aux11_5>=1))&&(aux9_5>=1)))||(((aux9_5>=1)&&(c14>=1))&&(aux11_6>=1)))||(((c14>=1)&&(aux9_6>=1))&&(aux11_3>=1)))||(((c14>=1)&&(aux9_6>=1))&&(aux11_4>=1)))||(((aux9_6>=1)&&(c14>=1))&&(aux11_1>=1)))||(((c14>=1)&&(aux9_6>=1))&&(aux11_2>=1)))||(((aux9_7>=1)&&(aux11_0>=1))&&(c14>=1)))||(((c14>=1)&&(aux11_7>=1))&&(aux9_6>=1)))||(((aux11_6>=1)&&(aux9_6>=1))&&(c14>=1)))||(((aux9_6>=1)&&(c14>=1))&&(aux11_5>=1)))||(((c14>=1)&&(aux11_4>=1))&&(aux9_7>=1)))||(((c14>=1)&&(aux11_3>=1))&&(aux9_7>=1)))||(((c14>=1)&&(aux11_2>=1))&&(aux9_7>=1)))||(((c14>=1)&&(aux9_7>=1))&&(aux11_1>=1)))||(((c14>=1)&&(aux9_7>=1))&&(aux11_7>=1)))||(((c14>=1)&&(aux9_7>=1))&&(aux11_6>=1)))||(((aux9_7>=1)&&(aux11_5>=1))&&(c14>=1)))||(((aux11_5>=1)&&(aux9_0>=1))&&(c14>=1)))||(((aux11_6>=1)&&(aux9_0>=1))&&(c14>=1)))||(((aux9_0>=1)&&(aux11_7>=1))&&(c14>=1)))||(((c14>=1)&&(aux9_1>=1))&&(aux11_0>=1)))||(((c14>=1)&&(aux11_1>=1))&&(aux9_1>=1)))||(((aux9_1>=1)&&(c14>=1))&&(aux11_2>=1)))||(((aux9_1>=1)&&(c14>=1))&&(aux11_3>=1)))||(((c14>=1)&&(aux9_1>=1))&&(aux11_4>=1)))||(((c14>=1)&&(aux9_1>=1))&&(aux11_5>=1)))||(((c14>=1)&&(aux9_1>=1))&&(aux11_6>=1)))||(((aux11_7>=1)&&(aux9_1>=1))&&(c14>=1)))||(((aux11_0>=1)&&(aux9_2>=1))&&(c14>=1)))||(((aux11_1>=1)&&(c14>=1))&&(aux9_2>=1)))||(((aux11_2>=1)&&(c14>=1))&&(aux9_2>=1)))||(((aux9_2>=1)&&(aux11_3>=1))&&(c14>=1)))||(((c14>=1)&&(aux11_4>=1))&&(aux9_2>=1)))||(((c14>=1)&&(aux11_6>=1))&&(aux9_2>=1)))||(((c14>=1)&&(aux11_5>=1))&&(aux9_2>=1)))||(((c14>=1)&&(aux9_3>=1))&&(aux11_0>=1)))||(((aux9_2>=1)&&(aux11_7>=1))&&(c14>=1)))||(((aux9_3>=1)&&(aux11_2>=1))&&(c14>=1)))||(((aux9_3>=1)&&(aux11_1>=1))&&(c14>=1)))||(((aux11_4>=1)&&(aux9_3>=1))&&(c14>=1)))||(((c14>=1)&&(aux9_3>=1))&&(aux11_3>=1)))||(((aux9_3>=1)&&(c14>=1))&&(aux11_6>=1)))||(((aux11_5>=1)&&(aux9_3>=1))&&(c14>=1)))||(((aux11_0>=1)&&(c14>=1))&&(aux9_4>=1)))||(((c14>=1)&&(aux9_3>=1))&&(aux11_7>=1)))||(((aux9_4>=1)&&(c14>=1))&&(aux11_2>=1)))||(((c14>=1)&&(aux9_4>=1))&&(aux11_1>=1)))||(((c14>=1)&&(aux9_4>=1))&&(aux11_4>=1)))||(((aux9_4>=1)&&(c14>=1))&&(aux11_3>=1)))")))))
Formula 0 simplified : !(XFG"((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((aux13_1>=1)&&(c17>=1))&&(aux15_2>=1))||(((aux13_1>=1)&&(c17>=1))&&(aux15_1>=1)))||(((aux13_1>=1)&&(c17>=1))&&(aux15_4>=1)))||(((aux13_1>=1)&&(c17>=1))&&(aux15_3>=1)))||(((c17>=1)&&(aux13_0>=1))&&(aux15_6>=1)))||(((aux15_5>=1)&&(aux13_0>=1))&&(c17>=1)))||(((aux15_0>=1)&&(c17>=1))&&(aux13_1>=1)))||(((c17>=1)&&(aux13_0>=1))&&(aux15_7>=1)))||(((aux15_2>=1)&&(aux13_2>=1))&&(c17>=1)))||(((aux15_1>=1)&&(aux13_2>=1))&&(c17>=1)))||(((c17>=1)&&(aux13_2>=1))&&(aux15_4>=1)))||(((aux15_3>=1)&&(aux13_2>=1))&&(c17>=1)))||(((aux15_6>=1)&&(c17>=1))&&(aux13_1>=1)))||(((aux13_1>=1)&&(c17>=1))&&(aux15_5>=1)))||(((c17>=1)&&(aux13_2>=1))&&(aux15_0>=1)))||(((c17>=1)&&(aux13_1>=1))&&(aux15_7>=1)))||(((aux15_1>=1)&&(c17>=1))&&(aux13_0>=1)))||(((c17>=1)&&(aux13_0>=1))&&(aux15_2>=1)))||(((aux15_3>=1)&&(c17>=1))&&(aux13_0>=1)))||(((aux15_4>=1)&&(aux13_0>=1))&&(c17>=1)))||(((aux13_0>=1)&&(c17>=1))&&(aux15_0>=1)))||(((aux13_5>=1)&&(c17>=1))&&(aux15_7>=1)))||(((aux15_0>=1)&&(aux13_6>=1))&&(c17>=1)))||(((c17>=1)&&(aux13_5>=1))&&(aux15_5>=1)))||(((aux15_6>=1)&&(aux13_5>=1))&&(c17>=1)))||(((aux15_3>=1)&&(c17>=1))&&(aux13_6>=1)))||(((aux15_4>=1)&&(aux13_6>=1))&&(c17>=1)))||(((aux15_1>=1)&&(c17>=1))&&(aux13_6>=1)))||(((c17>=1)&&(aux13_6>=1))&&(aux15_2>=1)))||(((aux15_7>=1)&&(c17>=1))&&(aux13_4>=1)))||(((c17>=1)&&(aux13_5>=1))&&(aux15_0>=1)))||(((aux13_4>=1)&&(c17>=1))&&(aux15_5>=1)))||(((c17>=1)&&(aux13_4>=1))&&(aux15_6>=1)))||(((aux15_3>=1)&&(aux13_5>=1))&&(c17>=1)))||(((aux15_4>=1)&&(c17>=1))&&(aux13_5>=1)))||(((aux15_1>=1)&&(aux13_5>=1))&&(c17>=1)))||(((aux13_5>=1)&&(c17>=1))&&(aux15_2>=1)))||(((aux15_0>=1)&&(c17>=1))&&(aux13_4>=1)))||(((aux15_7>=1)&&(c17>=1))&&(aux13_3>=1)))||(((aux15_6>=1)&&(c17>=1))&&(aux13_3>=1)))||(((aux15_5>=1)&&(aux13_3>=1))&&(c17>=1)))||(((aux13_4>=1)&&(c17>=1))&&(aux15_4>=1)))||(((c17>=1)&&(aux13_4>=1))&&(aux15_3>=1)))||(((c17>=1)&&(aux13_4>=1))&&(aux15_2>=1)))||(((c17>=1)&&(aux13_4>=1))&&(aux15_1>=1)))||(((aux15_0>=1)&&(aux13_3>=1))&&(c17>=1)))||(((aux13_2>=1)&&(c17>=1))&&(aux15_7>=1)))||(((aux15_6>=1)&&(aux13_2>=1))&&(c17>=1)))||(((aux15_5>=1)&&(c17>=1))&&(aux13_2>=1)))||(((aux15_4>=1)&&(aux13_3>=1))&&(c17>=1)))||(((c17>=1)&&(aux13_3>=1))&&(aux15_3>=1)))||(((aux15_2>=1)&&(c17>=1))&&(aux13_3>=1)))||(((c17>=1)&&(aux13_3>=1))&&(aux15_1>=1)))||(((c17>=1)&&(aux13_7>=1))&&(aux15_6>=1)))||(((aux13_7>=1)&&(c17>=1))&&(aux15_5>=1)))||(((c17>=1)&&(aux13_7>=1))&&(aux15_7>=1)))||(((aux15_6>=1)&&(aux13_6>=1))&&(c17>=1)))||(((aux15_5>=1)&&(aux13_6>=1))&&(c17>=1)))||(((aux15_0>=1)&&(aux13_7>=1))&&(c17>=1)))||(((aux15_7>=1)&&(aux13_6>=1))&&(c17>=1)))||(((c17>=1)&&(aux13_7>=1))&&(aux15_2>=1)))||(((aux15_1>=1)&&(c17>=1))&&(aux13_7>=1)))||(((aux15_4>=1)&&(aux13_7>=1))&&(c17>=1)))||(((aux15_3>=1)&&(c17>=1))&&(aux13_7>=1)))" U X("((((((in1_1>=1)&&(c6>=1))&&(in3_4>=1))||(((in3_5>=1)&&(in1_0>=1))&&(c6>=1)))||(((in1_1>=1)&&(c6>=1))&&(in3_5>=1)))||(((in1_0>=1)&&(c6>=1))&&(in3_4>=1)))" U "((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((c14>=1)&&(aux11_4>=1))&&(aux9_0>=1))||(((aux11_3>=1)&&(aux9_0>=1))&&(c14>=1)))||(((aux11_2>=1)&&(aux9_0>=1))&&(c14>=1)))||(((aux11_1>=1)&&(aux9_0>=1))&&(c14>=1)))||(((c14>=1)&&(aux9_0>=1))&&(aux11_0>=1)))||(((aux11_7>=1)&&(aux9_4>=1))&&(c14>=1)))||(((aux11_0>=1)&&(aux9_5>=1))&&(c14>=1)))||(((aux9_4>=1)&&(aux11_5>=1))&&(c14>=1)))||(((aux9_4>=1)&&(aux11_6>=1))&&(c14>=1)))||(((c14>=1)&&(aux9_5>=1))&&(aux11_3>=1)))||(((aux9_5>=1)&&(aux11_4>=1))&&(c14>=1)))||(((aux11_1>=1)&&(aux9_5>=1))&&(c14>=1)))||(((aux9_5>=1)&&(aux11_2>=1))&&(c14>=1)))||(((aux11_7>=1)&&(aux9_5>=1))&&(c14>=1)))||(((aux9_6>=1)&&(c14>=1))&&(aux11_0>=1)))||(((c14>=1)&&(aux11_5>=1))&&(aux9_5>=1)))||(((aux9_5>=1)&&(c14>=1))&&(aux11_6>=1)))||(((c14>=1)&&(aux9_6>=1))&&(aux11_3>=1)))||(((c14>=1)&&(aux9_6>=1))&&(aux11_4>=1)))||(((aux9_6>=1)&&(c14>=1))&&(aux11_1>=1)))||(((c14>=1)&&(aux9_6>=1))&&(aux11_2>=1)))||(((aux9_7>=1)&&(aux11_0>=1))&&(c14>=1)))||(((c14>=1)&&(aux11_7>=1))&&(aux9_6>=1)))||(((aux11_6>=1)&&(aux9_6>=1))&&(c14>=1)))||(((aux9_6>=1)&&(c14>=1))&&(aux11_5>=1)))||(((c14>=1)&&(aux11_4>=1))&&(aux9_7>=1)))||(((c14>=1)&&(aux11_3>=1))&&(aux9_7>=1)))||(((c14>=1)&&(aux11_2>=1))&&(aux9_7>=1)))||(((c14>=1)&&(aux9_7>=1))&&(aux11_1>=1)))||(((c14>=1)&&(aux9_7>=1))&&(aux11_7>=1)))||(((c14>=1)&&(aux9_7>=1))&&(aux11_6>=1)))||(((aux9_7>=1)&&(aux11_5>=1))&&(c14>=1)))||(((aux11_5>=1)&&(aux9_0>=1))&&(c14>=1)))||(((aux11_6>=1)&&(aux9_0>=1))&&(c14>=1)))||(((aux9_0>=1)&&(aux11_7>=1))&&(c14>=1)))||(((c14>=1)&&(aux9_1>=1))&&(aux11_0>=1)))||(((c14>=1)&&(aux11_1>=1))&&(aux9_1>=1)))||(((aux9_1>=1)&&(c14>=1))&&(aux11_2>=1)))||(((aux9_1>=1)&&(c14>=1))&&(aux11_3>=1)))||(((c14>=1)&&(aux9_1>=1))&&(aux11_4>=1)))||(((c14>=1)&&(aux9_1>=1))&&(aux11_5>=1)))||(((c14>=1)&&(aux9_1>=1))&&(aux11_6>=1)))||(((aux11_7>=1)&&(aux9_1>=1))&&(c14>=1)))||(((aux11_0>=1)&&(aux9_2>=1))&&(c14>=1)))||(((aux11_1>=1)&&(c14>=1))&&(aux9_2>=1)))||(((aux11_2>=1)&&(c14>=1))&&(aux9_2>=1)))||(((aux9_2>=1)&&(aux11_3>=1))&&(c14>=1)))||(((c14>=1)&&(aux11_4>=1))&&(aux9_2>=1)))||(((c14>=1)&&(aux11_6>=1))&&(aux9_2>=1)))||(((c14>=1)&&(aux11_5>=1))&&(aux9_2>=1)))||(((c14>=1)&&(aux9_3>=1))&&(aux11_0>=1)))||(((aux9_2>=1)&&(aux11_7>=1))&&(c14>=1)))||(((aux9_3>=1)&&(aux11_2>=1))&&(c14>=1)))||(((aux9_3>=1)&&(aux11_1>=1))&&(c14>=1)))||(((aux11_4>=1)&&(aux9_3>=1))&&(c14>=1)))||(((c14>=1)&&(aux9_3>=1))&&(aux11_3>=1)))||(((aux9_3>=1)&&(c14>=1))&&(aux11_6>=1)))||(((aux11_5>=1)&&(aux9_3>=1))&&(c14>=1)))||(((aux11_0>=1)&&(c14>=1))&&(aux9_4>=1)))||(((c14>=1)&&(aux9_3>=1))&&(aux11_7>=1)))||(((aux9_4>=1)&&(c14>=1))&&(aux11_2>=1)))||(((c14>=1)&&(aux9_4>=1))&&(aux11_1>=1)))||(((c14>=1)&&(aux9_4>=1))&&(aux11_4>=1)))||(((aux9_4>=1)&&(c14>=1))&&(aux11_3>=1)))"))
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 592 rows 168 cols
invariant :out1_0 + out1_6 + out1_5 + -1'out2_0 + out1_7 + out1_2 + out1_1 + out1_4 + out1_3 + -1'out2_7 + -1'out2_5 + -1'out2_6 + -1'out2_3 + -1'out2_4 + -1'out2_1 + -1'out2_2 = 0
invariant :aux7_7 + aux7_6 + -1'aux5_1 + -1'aux5_0 + -1'aux5_5 + -1'aux5_4 + aux7_3 + aux7_2 + 2'c7 + -4'c5 + 2'in1_1 + 2'in1_0 = 0
invariant :aux6_0 + -1'aux8_7 + -1'aux8_3 + -1'aux8_6 + aux6_5 + -1'aux8_2 + aux6_1 + aux6_4 + -2'c7 + -2'c8 = 0
invariant :-1'aux16_3 + -1'aux16_6 + aux14_2 + aux14_7 + -1'out7_3 + -1'out7_6 + out8_2 + out8_7 + -1'out5_6 + -1'out5_3 + out6_2 + out6_7 + -1'aux15_6 + -1'aux15_3 + aux13_2 + aux13_7 + -1'out3_6 + -1'out3_3 + out4_7 + out4_2 + -1'out1_6 + -1'out1_3 + out2_7 + out2_2 + -1'aux8_3 + -1'aux8_6 + -1'aux12_6 + -1'aux12_3 + aux11_2 + c11 + -1'aux7_6 + -1'aux10_3 + aux11_7 + aux5_1 + aux5_0 + aux5_5 + aux5_4 + -1'aux7_3 + aux9_7 + in4_7 + -1'in2_3 + -1'aux10_6 + aux9_2 + -2'c7 + -1'c8 + 4'c5 + -2'in1_1 + -2'in1_0 = 0
invariant :c18 + out4_0 + out4_1 + out4_7 + out4_6 + out4_3 + out4_2 + out4_5 + out4_4 + -1'out2_0 + -1'out2_7 + -1'out2_5 + -1'out2_6 + -1'out2_3 + -1'out2_4 + -1'out2_1 + -1'out2_2 = 0
invariant :aux16_3 + aux14_3 + out7_3 + out8_3 + out5_3 + out6_3 + aux15_3 + aux13_3 + out3_3 + out4_3 + out1_3 + out2_3 + aux8_3 + aux12_3 + aux11_3 + aux10_3 + aux7_3 + in2_3 + aux9_3 = 10
invariant :in4_6 + in4_7 + -2'c7 + -1'c8 + 2'c5 + -2'in1_1 + -2'in1_0 = 0
invariant :2'c5 + c6 + -1'in1_1 + -1'in1_0 = 0
invariant :-1'aux8_7 + c12 + -1'aux8_3 + -1'aux8_6 + -1'aux8_2 + 2'c11 + 2'aux5_1 + 2'aux5_0 + 2'aux5_5 + 2'aux5_4 + -2'c9 + -4'c7 + -4'c8 + 8'c5 + -4'in1_1 + -4'in1_0 = 0
invariant :in2_2 + in2_3 + -2'c7 + -1'c8 + 2'c5 + -2'in1_1 + -2'in1_0 = 0
invariant :out7_1 + out7_0 + out7_3 + out7_2 + out7_5 + out7_4 + out7_7 + out7_6 + -1'out8_1 + -1'out8_0 + -1'out8_3 + -1'out8_2 + -1'out8_6 + -1'out8_7 + -1'out8_4 + -1'out8_5 = 0
invariant :-1'aux16_1 + aux16_6 + -1'aux14_1 + -1'aux14_2 + -1'aux14_3 + -1'aux14_7 + -1'out7_1 + out7_6 + -1'out8_1 + -1'out8_3 + -1'out8_2 + -1'out8_7 + out5_2 + out5_0 + out5_5 + 2'out5_6 + out5_3 + out5_4 + -2'out6_1 + -2'out6_2 + out5_7 + -1'out6_0 + -1'out6_6 + -1'out6_5 + -1'out6_4 + -2'out6_3 + -1'aux15_1 + -2'out6_7 + aux15_6 + aux13_0 + -1'out3_1 + aux13_4 + aux13_5 + aux13_6 + out3_6 + out4_0 + out4_6 + 2'c17 + out4_5 + out4_4 + out1_6 + 3'out2_0 + -1'out1_1 + 2'out2_7 + 3'out2_5 + 3'out2_6 + 2'out2_3 + 3'out2_4 + 2'out2_1 + 2'out2_2 + 4'aux8_7 + 4'aux8_3 + 5'aux8_6 + 4'aux8_2 + -1'aux6_1 + 3'aux12_6 + 2'aux12_5 + 2'aux12_4 + 2'aux12_3 + 2'aux12_2 + aux12_1 + 2'aux12_0 + -1'aux11_3 + -1'aux11_2 + -1'aux11_1 + -5'c11 + 2'aux12_7 + aux7_6 + -1'aux10_1 + -1'aux11_7 + -6'aux5_1 + -5'aux5_0 + -5'aux5_5 + -5'aux5_4 + -1'aux9_7 + -1'in4_7 + aux10_6 + 4'c9 + -1'aux9_1 + -1'aux9_2 + -1'aux9_3 + -2'c15 + -2'c14 + 14'c7 + 13'c8 + -24'c5 + 13'in1_1 + 14'in1_0 = 20
invariant :-1'aux16_1 + aux16_6 + -1'aux14_1 + -1'aux14_2 + -1'aux14_3 + -1'aux14_7 + -1'out7_1 + out7_6 + -1'out8_1 + -1'out8_3 + -1'out8_2 + -1'out8_7 + out5_2 + out5_0 + out5_5 + 2'out5_6 + out5_3 + out5_4 + -2'out6_1 + -2'out6_2 + out5_7 + -1'out6_0 + -1'out6_6 + -1'out6_5 + -1'out6_4 + -2'out6_3 + -1'aux15_1 + -2'out6_7 + aux15_6 + aux13_0 + -1'out3_1 + aux13_4 + aux13_5 + aux13_6 + out3_6 + out4_0 + out4_6 + out4_5 + out4_4 + out1_6 + out2_0 + -1'out1_1 + out2_5 + out2_6 + out2_4 + 2'aux8_7 + 2'aux8_3 + 3'aux8_6 + 2'aux8_2 + -1'aux6_1 + aux12_6 + -1'aux12_1 + 2'c13 + -1'aux11_3 + -1'aux11_2 + -1'aux11_1 + -3'c11 + aux7_6 + -1'aux10_1 + -1'aux11_7 + -4'aux5_1 + -3'aux5_0 + -3'aux5_5 + -3'aux5_4 + -1'aux9_7 + -1'in4_7 + aux10_6 + 2'c9 + -1'aux9_1 + -1'aux9_2 + -1'aux9_3 + 8'c7 + 7'c8 + -14'c5 + 7'in1_1 + 8'in1_0 = 0
invariant :c19 + out6_1 + out6_2 + out6_0 + out6_6 + out6_5 + out6_4 + out6_3 + out6_7 + -1'out4_0 + -1'out4_1 + -1'out4_7 + -1'out4_6 + -1'out4_3 + -1'out4_2 + -1'out4_5 + -1'out4_4 = 0
invariant :-1'aux16_1 + aux16_6 + -1'aux14_1 + -1'aux14_2 + -1'aux14_3 + -1'aux14_7 + -1'out7_1 + out7_6 + -1'out8_1 + -1'out8_3 + -1'out8_2 + -1'out8_7 + out5_2 + out5_0 + out5_5 + 2'out5_6 + out5_3 + out5_4 + -2'out6_1 + -2'out6_2 + out5_7 + -1'out6_0 + -1'out6_6 + -1'out6_5 + -1'out6_4 + -2'out6_3 + -1'aux15_1 + -2'out6_7 + aux15_6 + aux13_0 + -1'out3_1 + aux13_4 + aux13_5 + aux13_6 + out3_6 + out4_0 + out4_6 + out4_5 + out4_4 + out1_6 + out2_0 + -1'out1_1 + out2_5 + out2_6 + out2_4 + aux8_6 + -1'aux6_1 + aux12_6 + -1'aux12_1 + -1'aux11_3 + -1'aux11_2 + -1'aux11_1 + -1'c11 + aux7_6 + -1'aux10_1 + -1'aux11_7 + -2'aux5_1 + -1'aux5_0 + -1'aux5_5 + -1'aux5_4 + aux9_4 + aux9_5 + aux9_6 + -1'in4_7 + aux10_6 + 2'c9 + aux9_0 + -1'c14 + 4'c7 + 3'c8 + -6'c5 + 3'in1_1 + 4'in1_0 = 0
invariant :c20 + out8_1 + out8_0 + out8_3 + out8_2 + out8_6 + out8_7 + out8_4 + out8_5 + -1'out6_1 + -1'out6_2 + -1'out6_0 + -1'out6_6 + -1'out6_5 + -1'out6_4 + -1'out6_3 + -1'out6_7 = 0
invariant :-1'aux16_0 + aux16_1 + -1'aux16_6 + 2'aux14_1 + 2'aux14_2 + 2'aux14_3 + aux14_4 + aux14_6 + aux14_5 + 2'aux14_7 + out7_1 + -1'out7_0 + -1'out7_6 + 2'out8_1 + 2'out8_3 + 2'out8_2 + out8_6 + 2'out8_7 + out8_4 + out8_5 + -1'out5_2 + -2'out5_0 + -1'out5_5 + -2'out5_6 + -1'out5_3 + -1'out5_4 + 3'out6_1 + 3'out6_2 + -1'out5_7 + out6_0 + 2'out6_6 + 2'out6_5 + 2'out6_4 + 3'out6_3 + aux15_1 + -1'aux15_0 + 3'out6_7 + -1'aux15_6 + -2'aux13_0 + 2'out3_1 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + out3_7 + -3'out4_0 + -1'out4_1 + out3_2 + out3_3 + out3_4 + out3_5 + -1'out4_7 + -2'out4_6 + -1'out1_0 + -1'out4_3 + -1'out4_2 + -2'out4_5 + -2'out4_4 + -1'out1_6 + -2'out2_0 + out1_1 + -1'out2_5 + -1'out2_6 + -1'out2_4 + -1'aux8_7 + -1'aux8_3 + -2'aux8_6 + aux6_5 + -1'aux8_2 + 2'aux6_1 + aux6_4 + -1'aux12_6 + aux12_1 + -1'aux12_0 + aux11_3 + aux11_2 + aux11_1 + -1'aux11_0 + c11 + -1'aux7_6 + -1'aux10_0 + aux10_1 + aux11_7 + 2'aux5_1 + aux5_5 + aux5_4 + aux9_7 + in4_7 + -1'aux10_6 + -1'aux9_0 + aux9_1 + aux9_2 + aux9_3 + 2'c14 + -4'c7 + -3'c8 + 4'c5 + -1'in1_1 + -3'in1_0 = 10
invariant :-2'aux16_1 + aux16_6 + -2'aux14_1 + -2'aux14_2 + -2'aux14_3 + -1'aux14_6 + -2'aux14_7 + -2'out7_1 + out7_6 + -2'out8_1 + -2'out8_3 + -2'out8_2 + -1'out8_6 + -2'out8_7 + 2'out5_2 + 2'out5_0 + 2'out5_5 + 3'out5_6 + 2'out5_3 + 2'out5_4 + -4'out6_1 + -4'out6_2 + 2'out5_7 + -2'out6_0 + -3'out6_6 + -2'out6_5 + -2'out6_4 + -4'out6_3 + -2'aux15_1 + -4'out6_7 + aux15_6 + 2'aux13_0 + -2'out3_1 + 2'aux13_4 + 2'aux13_5 + aux13_6 + out3_6 + 2'out4_0 + out4_6 + 2'out4_5 + 2'out4_4 + out1_6 + 2'out2_0 + -2'out1_1 + 2'out2_5 + out2_6 + 2'out2_4 + aux8_6 + -2'aux6_1 + aux12_6 + -2'aux12_1 + aux11_5 + aux11_4 + -1'aux11_3 + -1'aux11_2 + -1'aux11_1 + aux11_0 + aux7_6 + -2'aux10_1 + -1'aux11_7 + -2'aux5_1 + aux9_4 + aux9_5 + -1'aux9_7 + -1'in4_7 + aux10_6 + aux9_0 + -1'aux9_1 + -1'aux9_2 + -1'aux9_3 + -2'c14 + 2'c7 + c8 + -2'c5 + 2'in1_0 = -10
invariant :aux16_1 + -1'aux16_6 + aux14_1 + aux14_2 + aux14_3 + aux14_7 + out7_1 + -1'out7_6 + out8_1 + out8_3 + out8_2 + out8_7 + -1'out5_2 + -1'out5_0 + -1'out5_5 + -2'out5_6 + -1'out5_3 + -1'out5_4 + 2'out6_1 + 2'out6_2 + -1'out5_7 + out6_0 + out6_6 + out6_5 + out6_4 + 2'out6_3 + aux15_1 + 2'out6_7 + -1'aux15_6 + -1'aux13_0 + out3_1 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'out3_6 + -1'out4_0 + -1'out4_6 + 2'c17 + -1'out4_5 + -1'out4_4 + -1'out1_6 + out2_0 + out1_1 + 2'out2_7 + out2_5 + out2_6 + 2'out2_3 + out2_4 + 2'out2_1 + 2'out2_2 + -1'aux8_6 + aux6_1 + -1'aux12_6 + aux12_1 + aux11_3 + aux11_2 + aux11_1 + c11 + -1'aux7_6 + aux10_1 + aux11_7 + 2'aux5_1 + aux5_0 + aux5_5 + aux5_4 + aux9_7 + in4_7 + -1'aux10_6 + aux9_1 + aux9_2 + aux9_3 + 2'c16 + 2'c15 + 2'c14 + -2'c7 + -1'c8 + 4'c5 + -1'in1_1 + -2'in1_0 = 20
invariant :-1'aux16_1 + aux16_6 + aux16_7 + -1'aux14_1 + -1'aux14_2 + -1'aux14_3 + -1'out7_1 + out7_7 + out7_6 + -1'out8_1 + -1'out8_3 + -1'out8_2 + out5_2 + out5_0 + out5_5 + 2'out5_6 + out5_3 + out5_4 + -2'out6_1 + -2'out6_2 + 2'out5_7 + -1'out6_0 + -1'out6_6 + -1'out6_5 + -1'out6_4 + -2'out6_3 + -1'aux15_2 + -2'aux15_1 + -1'aux15_0 + -1'out6_7 + -1'aux15_5 + -1'aux15_4 + -1'aux15_3 + aux13_0 + aux13_7 + -1'out3_1 + aux13_4 + aux13_5 + aux13_6 + out3_6 + out3_7 + -1'out4_1 + -1'out4_3 + -1'out4_2 + out1_6 + out1_7 + -1'out1_1 + -1'out2_3 + -1'out2_1 + -1'out2_2 + aux8_7 + aux8_6 + -1'aux6_1 + aux12_6 + -1'aux12_1 + -1'aux11_3 + -1'aux11_2 + -1'aux11_1 + -1'c11 + aux12_7 + -1'aux10_1 + -1'aux5_1 + -1'aux7_3 + -1'aux7_2 + aux10_6 + aux10_7 + -1'aux9_1 + -1'aux9_2 + -1'aux9_3 + -2'c15 + -2'c14 + c8 + -1'in1_1 = -10
invariant :aux16_0 + aux16_1 + aux16_4 + -1'aux14_5 + out7_1 + out7_0 + out7_4 + -1'out8_5 + -1'out5_2 + -1'out5_5 + -1'out5_6 + -1'out5_3 + out6_1 + out6_2 + -1'out5_7 + out6_0 + out6_6 + out6_4 + out6_3 + aux15_1 + aux15_0 + out6_7 + aux15_4 + -1'aux13_5 + -1'out3_6 + -1'out3_7 + out4_0 + out4_1 + -1'out3_2 + -1'out3_3 + -1'out3_5 + out4_7 + out4_6 + out1_0 + out4_3 + out4_2 + out4_4 + out1_1 + out1_4 + -1'out2_5 + aux8_7 + aux8_3 + aux8_6 + -1'aux6_5 + aux8_2 + aux12_4 + aux12_1 + aux12_0 + -1'aux11_5 + -1'c11 + aux10_0 + aux10_1 + aux10_4 + -1'aux5_5 + -1'aux9_5 + in3_4 + 2'c7 + 2'c8 + -2'c5 + in1_1 + in1_0 = 10
invariant :aux16_1 + -1'aux16_6 + -2'aux16_7 + aux14_1 + aux14_2 + aux14_3 + -1'aux14_7 + out7_1 + -2'out7_7 + -1'out7_6 + out8_1 + out8_3 + out8_2 + -1'out8_7 + -1'out5_2 + -1'out5_0 + -1'out5_5 + -2'out5_6 + -1'out5_3 + -1'out5_4 + 2'out6_1 + 2'out6_2 + -3'out5_7 + out6_0 + out6_6 + out6_5 + out6_4 + 2'out6_3 + 2'aux15_2 + 3'aux15_1 + 2'aux15_0 + aux15_6 + 2'aux15_5 + 2'aux15_4 + 2'aux15_3 + -1'aux13_0 + -2'aux13_7 + out3_1 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'out3_6 + -2'out3_7 + out4_0 + 2'out4_1 + out4_6 + 2'c17 + 2'out4_3 + 2'out4_2 + out4_5 + out4_4 + -1'out1_6 + 3'out2_0 + -2'out1_7 + out1_1 + 2'out2_7 + 3'out2_5 + 3'out2_6 + 4'out2_3 + 3'out2_4 + 4'out2_1 + 4'out2_2 + -2'aux8_7 + -1'aux8_6 + aux6_1 + -1'aux12_6 + aux12_1 + aux11_3 + aux11_2 + aux11_1 + c11 + -2'aux12_7 + aux7_6 + 2'aux10_0 + 2'aux10_2 + 3'aux10_1 + 2'aux10_4 + 2'aux10_3 + -1'aux11_7 + 4'aux5_1 + 3'aux5_0 + 3'aux5_5 + 3'aux5_4 + 2'aux7_3 + 2'aux7_2 + -1'aux9_7 + -1'in4_7 + 2'aux10_5 + aux10_6 + -4'c9 + aux9_1 + aux9_2 + aux9_3 + 2'c15 + 2'c14 + -2'c7 + -5'c8 + 8'c5 + -1'in1_1 + -2'in1_0 = 40
invariant :out5_1 + out5_2 + out5_0 + out5_5 + out5_6 + out5_3 + out5_4 + -1'out6_1 + -1'out6_2 + out5_7 + -1'out6_0 + -1'out6_6 + -1'out6_5 + -1'out6_4 + -1'out6_3 + -1'out6_7 = 0
invariant :aux16_1 + aux14_1 + out7_1 + out8_1 + -1'out5_2 + -1'out5_0 + -1'out5_5 + -1'out5_6 + -1'out5_3 + -1'out5_4 + 2'out6_1 + out6_2 + -1'out5_7 + out6_0 + out6_6 + out6_5 + out6_4 + out6_3 + aux15_1 + out6_7 + aux13_1 + out3_1 + out4_1 + out1_1 + out2_1 + aux6_1 + aux12_1 + aux11_1 + aux10_1 + aux5_1 + aux9_1 + in1_1 = 10
invariant :aux16_0 + aux14_0 + out7_0 + out8_0 + out5_0 + out6_0 + aux15_0 + aux13_0 + -1'out3_1 + -1'out3_6 + -1'out3_7 + 2'out4_0 + out4_1 + -1'out3_2 + -1'out3_3 + -1'out3_4 + -1'out3_5 + out4_7 + out4_6 + out1_0 + out4_3 + out4_2 + out4_5 + out4_4 + out2_0 + aux8_7 + aux8_3 + aux8_6 + -1'aux6_5 + aux8_2 + -1'aux6_1 + -1'aux6_4 + aux12_0 + aux11_0 + aux10_0 + aux5_0 + aux9_0 + 2'c7 + 2'c8 + in1_0 = 10
invariant :c110 + -1'aux5_1 + -1'aux5_0 + -1'aux5_5 + -1'aux5_4 + 2'c9 + 2'c7 + 2'c8 + -4'c5 + 2'in1_1 + 2'in1_0 = 0
invariant :out3_0 + out3_1 + out3_6 + out3_7 + -1'out4_0 + -1'out4_1 + out3_2 + out3_3 + out3_4 + out3_5 + -1'out4_7 + -1'out4_6 + -1'out4_3 + -1'out4_2 + -1'out4_5 + -1'out4_4 = 0
invariant :aux16_1 + aux14_1 + aux14_2 + aux14_3 + aux14_6 + aux14_7 + out7_1 + out8_1 + out8_3 + out8_2 + out8_6 + out8_7 + -1'out5_2 + -1'out5_0 + -1'out5_5 + -1'out5_6 + -1'out5_3 + -1'out5_4 + 2'out6_1 + 2'out6_2 + -1'out5_7 + out6_0 + 2'out6_6 + out6_5 + out6_4 + 2'out6_3 + aux15_1 + 2'out6_7 + -1'aux13_0 + out3_1 + -1'aux13_4 + -1'aux13_5 + -1'out4_0 + -1'out4_5 + -1'out4_4 + -1'out2_0 + out1_1 + -1'out2_5 + -1'out2_4 + aux6_1 + aux12_1 + aux11_3 + aux11_2 + aux11_1 + c11 + aux10_1 + aux11_7 + aux11_6 + 2'aux5_1 + aux5_0 + aux5_5 + aux5_4 + -1'aux9_4 + -1'aux9_5 + -2'c9 + -1'aux9_0 + c14 + -2'c7 + -2'c8 + 4'c5 + -1'in1_1 + -2'in1_0 = 10
invariant :aux16_2 + aux16_3 + aux16_6 + aux16_7 + out7_3 + out7_2 + out7_7 + out7_6 + out5_2 + out5_6 + out5_3 + out5_7 + -1'aux15_1 + -1'aux15_0 + -1'aux15_5 + -1'aux15_4 + out3_6 + out3_7 + -1'out4_0 + -1'out4_1 + out3_2 + out3_3 + -1'out4_7 + -1'out4_6 + -2'c17 + -1'out4_3 + -1'out4_2 + -1'out4_5 + -1'out4_4 + out1_6 + -3'out2_0 + out1_7 + out1_2 + out1_3 + -3'out2_7 + -3'out2_5 + -3'out2_6 + -3'out2_3 + -3'out2_4 + -3'out2_1 + -3'out2_2 + -1'aux8_7 + -1'aux8_3 + -1'aux8_6 + -1'aux8_2 + -1'aux12_5 + -1'aux12_4 + -1'aux12_1 + -1'aux12_0 + c11 + -1'aux10_0 + -1'aux10_1 + -1'aux10_4 + -1'aux10_5 + -2'c7 + -2'c8 + 2'c5 + -2'in1_1 + -2'in1_0 = -20
invariant :aux16_1 + -1'aux16_6 + aux14_1 + aux14_2 + aux14_3 + aux14_7 + out7_1 + -1'out7_6 + out8_1 + out8_3 + out8_2 + out8_7 + -1'out5_2 + -1'out5_0 + -1'out5_5 + -2'out5_6 + -1'out5_3 + -1'out5_4 + 2'out6_1 + 2'out6_2 + -1'out5_7 + out6_0 + out6_6 + out6_5 + out6_4 + 2'out6_3 + aux15_2 + 2'aux15_1 + aux15_0 + 2'out6_7 + aux15_5 + aux15_4 + aux15_3 + -1'aux13_0 + aux15_7 + out3_1 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'out3_6 + out4_1 + out4_7 + out4_3 + out4_2 + -1'out1_6 + out1_1 + out2_7 + out2_3 + out2_1 + out2_2 + -1'aux8_6 + aux6_1 + -1'aux12_6 + aux12_1 + aux11_3 + aux11_2 + aux11_1 + c11 + -1'aux7_6 + aux10_1 + aux11_7 + 2'aux5_1 + aux5_0 + aux5_5 + aux5_4 + aux9_7 + in4_7 + -1'aux10_6 + aux9_1 + aux9_2 + aux9_3 + 2'c15 + 2'c14 + -2'c7 + -1'c8 + 4'c5 + -1'in1_1 + -2'in1_0 = 20
invariant :in3_5 + in3_4 + -1'in1_1 + -1'in1_0 = 0
invariant :aux16_5 + aux14_5 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_4 + -1'out7_7 + -1'out7_6 + out8_1 + out8_0 + out8_3 + out8_2 + out8_6 + out8_7 + out8_4 + 2'out8_5 + out5_5 + out6_5 + aux15_5 + aux13_5 + out3_5 + -1'out1_0 + out4_5 + -1'out1_6 + out2_0 + -1'out1_7 + -1'out1_2 + -1'out1_1 + -1'out1_4 + -1'out1_3 + out2_7 + 2'out2_5 + out2_6 + out2_3 + out2_4 + out2_1 + out2_2 + aux6_5 + aux12_5 + aux11_5 + aux5_5 + aux9_5 + aux10_5 + -1'in3_4 + in1_1 + in1_0 = 10
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O2, model.c], workingDir=/home/mcc/execution]
Compilation finished in 16191 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 183 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, (X(<>([]((LTLAP0==true)))))U(X(((LTLAP1==true))U((LTLAP2==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 4471 ms.
FORMULA PermAdmissibility-PT-10-LTLFireability-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, [](<>((LTLAP3==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, [](<>((LTLAP3==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X(X((LTLAP4==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 31515 ms.
FORMULA PermAdmissibility-PT-10-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X((LTLAP5==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X((LTLAP5==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, (LTLAP6==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 10629 ms.
FORMULA PermAdmissibility-PT-10-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, <>((X([]((LTLAP7==true))))U([](X((LTLAP8==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1561 ms.
FORMULA PermAdmissibility-PT-10-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, <>((X((LTLAP2==true)))U(((LTLAP9==true))U((LTLAP9==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, <>((X((LTLAP2==true)))U(((LTLAP9==true))U((LTLAP9==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, ((<>((LTLAP10==true)))U(X((LTLAP1==true))))U(<>(((LTLAP11==true))U((LTLAP3==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, ((<>((LTLAP10==true)))U(X((LTLAP1==true))))U(<>(((LTLAP11==true))U((LTLAP3==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, (LTLAP12==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 10693 ms.
FORMULA PermAdmissibility-PT-10-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, (LTLAP13==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 11564 ms.
FORMULA PermAdmissibility-PT-10-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, <>(X(([]((LTLAP14==true)))U(<>((LTLAP15==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 2462 ms.
FORMULA PermAdmissibility-PT-10-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, <>((LTLAP16==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 10830 ms.
FORMULA PermAdmissibility-PT-10-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X(((LTLAP17==true))U([]([]((LTLAP18==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1699 ms.
FORMULA PermAdmissibility-PT-10-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, [](<>([]((LTLAP19==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 11848 ms.
FORMULA PermAdmissibility-PT-10-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, (((LTLAP20==true))U((LTLAP21==true)))U((LTLAP22==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 11819 ms.
FORMULA PermAdmissibility-PT-10-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X([]((X((LTLAP23==true)))U((LTLAP24==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X([]((X((LTLAP23==true)))U((LTLAP24==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Retrying LTSmin with larger timeout 1800 s
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, [](<>((LTLAP3==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>1800 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, [](<>((LTLAP3==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X((LTLAP5==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 144515 ms.
FORMULA PermAdmissibility-PT-10-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, <>((X((LTLAP2==true)))U(((LTLAP9==true))U((LTLAP9==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ LTLFireability = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Mar 18, 2019 5:48:40 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Mar 18, 2019 5:48:40 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Mar 18, 2019 5:48:41 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 414 ms
Mar 18, 2019 5:48:41 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 168 places.
Mar 18, 2019 5:48:42 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 592 transitions.
Mar 18, 2019 5:48:42 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 72 ms
Mar 18, 2019 5:48:43 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 630 ms
Mar 18, 2019 5:48:43 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 153 ms
Mar 18, 2019 5:48:43 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 4 ms
Mar 18, 2019 5:48:45 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 592 transitions.
Mar 18, 2019 5:48:47 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 32 place invariants in 355 ms
Mar 18, 2019 5:48:53 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 168 variables to be positive in 7079 ms
Mar 18, 2019 5:48:53 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 592 transitions.
Mar 18, 2019 5:48:53 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/592 took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 18, 2019 5:48:53 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 142 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 18, 2019 5:48:53 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 592 transitions.
Mar 18, 2019 5:48:53 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 57 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 18, 2019 5:52:38 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 592 transitions.
Mar 18, 2019 5:52:53 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/592) took 14828 ms. Total solver calls (SAT/UNSAT): 523(523/0)
Mar 18, 2019 5:53:04 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(1/592) took 25600 ms. Total solver calls (SAT/UNSAT): 885(885/0)
Mar 18, 2019 5:53:20 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(2/592) took 41998 ms. Total solver calls (SAT/UNSAT): 1414(1414/0)
Mar 18, 2019 5:53:31 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(3/592) took 52972 ms. Total solver calls (SAT/UNSAT): 1799(1799/0)
SMT solver raised 'unknown', retrying with same input.
Mar 18, 2019 5:54:28 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(4/592) took 109927 ms. Total solver calls (SAT/UNSAT): 2386(2386/0)
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown' twice, overapproximating result to 1.
Mar 18, 2019 5:54:55 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(5/592) took 136608 ms. Total solver calls (SAT/UNSAT): 2721(2721/0)
Mar 18, 2019 5:54:55 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 136677 ms. Total solver calls (SAT/UNSAT): 2721(2721/0)
Mar 18, 2019 5:54:55 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 592 transitions.
Mar 18, 2019 5:55:06 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Mar 18, 2019 5:55:07 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Mar 18, 2019 5:55:07 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Mar 18, 2019 5:55:08 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Mar 18, 2019 5:55:09 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Mar 18, 2019 5:55:09 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Mar 18, 2019 5:55:10 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Mar 18, 2019 5:55:11 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Mar 18, 2019 5:55:11 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Mar 18, 2019 5:55:12 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Mar 18, 2019 5:55:12 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Mar 18, 2019 5:55:13 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Mar 18, 2019 5:55:14 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Mar 18, 2019 5:55:14 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Mar 18, 2019 5:55:15 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Mar 18, 2019 5:55:15 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Mar 18, 2019 5:55:16 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Skipping mayMatrices nes/nds SMT solver raised an error :unknown
java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.computeDoNotAccord(NecessaryEnablingsolver.java:628)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:538)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
Mar 18, 2019 5:55:16 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 392403ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-PT-10"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3954"
echo " Executing tool itstools"
echo " Input is PermAdmissibility-PT-10, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r107-oct2-155272231000448"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-PT-10.tgz
mv PermAdmissibility-PT-10 execution
cd execution
if [ "LTLFireability" = "GlobalProperties" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
if [ "LTLFireability" = "UpperBounds" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;