Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2019-input.r096-smll-155246587200152.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2019-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
...................
=====================================================================
Generated by BenchKit 2-3957
Executing tool itstools
Input is LamportFastMutEx-COL-5, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r096-smll-155246587200152
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 208K
-rw-r--r-- 1 mcc users 4.0K Feb 11 22:45 CTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Feb 11 22:45 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Feb 7 23:34 CTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 7 23:34 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 10 17:31 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Mar 10 17:31 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 109 Feb 24 15:05 GlobalProperties.txt
-rw-r--r-- 1 mcc users 347 Feb 24 15:05 GlobalProperties.xml
-rw-r--r-- 1 mcc users 2.6K Feb 5 00:11 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K Feb 5 00:10 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Feb 4 22:36 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.7K Feb 4 22:36 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K Feb 4 06:23 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K Feb 4 06:23 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Jan 31 23:53 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 16K Jan 31 23:53 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 4 22:21 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 4 22:21 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Jan 29 09:34 equiv_pt
-rw-r--r-- 1 mcc users 2 Jan 29 09:34 instance
-rw-r--r-- 1 mcc users 5 Jan 29 09:34 iscolored
-rw-r--r-- 1 mcc users 41K Mar 10 17:31 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-00
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-01
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-02
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-03
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-04
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-05
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-06
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-07
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-08
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-09
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-10
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-11
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-12
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-13
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-14
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1552758486745

17:48:09.986 [main] ERROR PNML validation - The rng grammar file can't be accessed : www.pnml.org
17:48:09.990 [main] ERROR import - Grammar file errors have been raised, the validation can't be done, process will continue without Grammar validation
Working with output stream class java.io.PrintStream
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903111103/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903111103/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-00 with value :((!((((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)+P_setx_3_5)>=3))||(!(((((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)+P_setbi_24_5)>=2)&&((((((((((((((((((((((((((((((((((((wait_0+wait_1)+wait_2)+wait_3)+wait_4)+wait_5)+wait_6)+wait_7)+wait_8)+wait_9)+wait_10)+wait_11)+wait_12)+wait_13)+wait_14)+wait_15)+wait_16)+wait_17)+wait_18)+wait_19)+wait_20)+wait_21)+wait_22)+wait_23)+wait_24)+wait_25)+wait_26)+wait_27)+wait_28)+wait_29)+wait_30)+wait_31)+wait_32)+wait_33)+wait_34)+wait_35)<=(((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)))))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-01 with value :(true)
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-02 with value :((((((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)+P_awaity_5)>=3)&&(((((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)>=3)&&((((((P_await_13_0+P_await_13_1)+P_await_13_2)+P_await_13_3)+P_await_13_4)+P_await_13_5)>=1)))&&(((((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)+P_ify0_4_5)<=(((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)+P_setx_3_5))||((((((((((((((((((((((((((((((((((((wait_0+wait_1)+wait_2)+wait_3)+wait_4)+wait_5)+wait_6)+wait_7)+wait_8)+wait_9)+wait_10)+wait_11)+wait_12)+wait_13)+wait_14)+wait_15)+wait_16)+wait_17)+wait_18)+wait_19)+wait_20)+wait_21)+wait_22)+wait_23)+wait_24)+wait_25)+wait_26)+wait_27)+wait_28)+wait_29)+wait_30)+wait_31)+wait_32)+wait_33)+wait_34)+wait_35)<=(((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5))))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-03 with value :((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)<=(((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)+P_setbi_24_5))
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-04 with value :(((((((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)+P_ify0_4_5)>=2)||((((((P_CS_21_0+P_CS_21_1)+P_CS_21_2)+P_CS_21_3)+P_CS_21_4)+P_CS_21_5)>=2))&&(((((((((((((((((((((((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)+done_16)+done_17)+done_18)+done_19)+done_20)+done_21)+done_22)+done_23)+done_24)+done_25)+done_26)+done_27)+done_28)+done_29)+done_30)+done_31)+done_32)+done_33)+done_34)+done_35)<=(((((P_CS_21_0+P_CS_21_1)+P_CS_21_2)+P_CS_21_3)+P_CS_21_4)+P_CS_21_5))||((((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)>=1)))&&(((((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)<=(((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5))&&(!((((((((((((((((((((((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)+done_16)+done_17)+done_18)+done_19)+done_20)+done_21)+done_22)+done_23)+done_24)+done_25)+done_26)+done_27)+done_28)+done_29)+done_30)+done_31)+done_32)+done_33)+done_34)+done_35)>=3))))
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-05 with value :((((((((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7)+b_8)+b_9)+b_10)+b_11)<=(((((((((((((((((((((((((((((((((((wait_0+wait_1)+wait_2)+wait_3)+wait_4)+wait_5)+wait_6)+wait_7)+wait_8)+wait_9)+wait_10)+wait_11)+wait_12)+wait_13)+wait_14)+wait_15)+wait_16)+wait_17)+wait_18)+wait_19)+wait_20)+wait_21)+wait_22)+wait_23)+wait_24)+wait_25)+wait_26)+wait_27)+wait_28)+wait_29)+wait_30)+wait_31)+wait_32)+wait_33)+wait_34)+wait_35))
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-06 with value :((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)>=3)
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-07 with value :((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)>=2)
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-08 with value :(!((((((((((((((((((((((((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)+done_16)+done_17)+done_18)+done_19)+done_20)+done_21)+done_22)+done_23)+done_24)+done_25)+done_26)+done_27)+done_28)+done_29)+done_30)+done_31)+done_32)+done_33)+done_34)+done_35)<=(((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5))||((((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)+P_ify0_4_5)<=(((((((((((((((((((((((((((((((((((wait_0+wait_1)+wait_2)+wait_3)+wait_4)+wait_5)+wait_6)+wait_7)+wait_8)+wait_9)+wait_10)+wait_11)+wait_12)+wait_13)+wait_14)+wait_15)+wait_16)+wait_17)+wait_18)+wait_19)+wait_20)+wait_21)+wait_22)+wait_23)+wait_24)+wait_25)+wait_26)+wait_27)+wait_28)+wait_29)+wait_30)+wait_31)+wait_32)+wait_33)+wait_34)+wait_35)))||(((((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)+P_ify0_4_5)<=(((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)+P_setbi_24_5))&&((((((((((((((((((((((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)+done_16)+done_17)+done_18)+done_19)+done_20)+done_21)+done_22)+done_23)+done_24)+done_25)+done_26)+done_27)+done_28)+done_29)+done_30)+done_31)+done_32)+done_33)+done_34)+done_35)>=2))))
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-09 with value :(((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5)>=3)||((((((P_setbi_11_0+P_setbi_11_1)+P_setbi_11_2)+P_setbi_11_3)+P_setbi_11_4)+P_setbi_11_5)>=2))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-10 with value :(!((((((((((((((((((((((((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)+done_16)+done_17)+done_18)+done_19)+done_20)+done_21)+done_22)+done_23)+done_24)+done_25)+done_26)+done_27)+done_28)+done_29)+done_30)+done_31)+done_32)+done_33)+done_34)+done_35)<=(((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5))&&((((((y_0+y_1)+y_2)+y_3)+y_4)+y_5)>=3))&&(!((((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)+P_setx_3_5)>=3))))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-11 with value :(((!((((((P_await_13_0+P_await_13_1)+P_await_13_2)+P_await_13_3)+P_await_13_4)+P_await_13_5)<=(((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)+P_setx_3_5)))||(((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)<=(((((P_await_13_0+P_await_13_1)+P_await_13_2)+P_await_13_3)+P_await_13_4)+P_await_13_5))||((((((((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7)+b_8)+b_9)+b_10)+b_11)>=2)))||(!((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)<=(((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)+P_awaity_5))))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-12 with value :(!((((((((((((((((((((((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)+done_16)+done_17)+done_18)+done_19)+done_20)+done_21)+done_22)+done_23)+done_24)+done_25)+done_26)+done_27)+done_28)+done_29)+done_30)+done_31)+done_32)+done_33)+done_34)+done_35)>=1))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-13 with value :((((((((((((((((((((((((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)+done_16)+done_17)+done_18)+done_19)+done_20)+done_21)+done_22)+done_23)+done_24)+done_25)+done_26)+done_27)+done_28)+done_29)+done_30)+done_31)+done_32)+done_33)+done_34)+done_35)<=(((((P_ifxi_10_0+P_ifxi_10_1)+P_ifxi_10_2)+P_ifxi_10_3)+P_ifxi_10_4)+P_ifxi_10_5))||((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)>=2))||(((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)>=2)&&((((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)+P_ify0_4_5)<=(((((P_start_1_0+P_start_1_1)+P_start_1_2)+P_start_1_3)+P_start_1_4)+P_start_1_5))))
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-14 with value :(((((((((P_CS_21_0+P_CS_21_1)+P_CS_21_2)+P_CS_21_3)+P_CS_21_4)+P_CS_21_5)<=(((((P_sety_9_0+P_sety_9_1)+P_sety_9_2)+P_sety_9_3)+P_sety_9_4)+P_sety_9_5))&&((((((P_await_13_0+P_await_13_1)+P_await_13_2)+P_await_13_3)+P_await_13_4)+P_await_13_5)>=1))||(!((((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)+P_awaity_5)<=(((((P_start_1_0+P_start_1_1)+P_start_1_2)+P_start_1_3)+P_start_1_4)+P_start_1_5))))||(!(((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5)<=(((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)+P_setx_3_5))||((((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)+P_ify0_4_5)<=(((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)))))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-15 with value :((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5)<=(((((y_0+y_1)+y_2)+y_3)+y_4)+y_5))
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 246
// Phase 1: matrix 246 rows 174 cols
invariant :P_start_1_1 + P_setx_3_1 + P_setbi_5_1 + P_ify0_4_1 + P_sety_9_1 + P_ifxi_10_1 + P_setbi_11_1 + P_fordo_12_1 + P_await_13_1 + P_ifyi_15_1 + P_awaity_1 + P_CS_21_1 + P_setbi_24_1 = 1
invariant :wait_11 + -1'P_await_13_1 + done_11 = 0
invariant :wait_6 + done_6 = 0
invariant :wait_9 + -1'P_await_13_1 + done_9 = 0
invariant :wait_13 + -1'P_await_13_2 + done_13 = 0
invariant :wait_35 + -1'P_await_13_5 + done_35 = 0
invariant :wait_23 + -1'P_await_13_3 + done_23 = 0
invariant :wait_5 + -1'P_await_13_0 + done_5 = 0
invariant :wait_25 + -1'P_await_13_4 + done_25 = 0
invariant :wait_31 + -1'P_await_13_5 + done_31 = 0
invariant :wait_10 + -1'P_await_13_1 + done_10 = 0
invariant :y_0 + y_1 + y_2 + y_3 + y_4 + y_5 = 1
invariant :b_2 + b_3 = 1
invariant :wait_16 + -1'P_await_13_2 + done_16 = 0
invariant :wait_20 + -1'P_await_13_3 + done_20 = 0
invariant :wait_26 + -1'P_await_13_4 + done_26 = 0
invariant :wait_29 + -1'P_await_13_4 + done_29 = 0
invariant :P_start_1_5 + P_setx_3_5 + P_setbi_5_5 + P_ify0_4_5 + P_sety_9_5 + P_ifxi_10_5 + P_setbi_11_5 + P_fordo_12_5 + P_await_13_5 + P_ifyi_15_5 + P_awaity_5 + P_CS_21_5 + P_setbi_24_5 = 1
invariant :wait_30 + done_30 = 0
invariant :wait_22 + -1'P_await_13_3 + done_22 = 0
invariant :P_start_1_4 + P_setx_3_4 + P_setbi_5_4 + P_ify0_4_4 + P_sety_9_4 + P_ifxi_10_4 + P_setbi_11_4 + P_fordo_12_4 + P_await_13_4 + P_ifyi_15_4 + P_awaity_4 + P_CS_21_4 + P_setbi_24_4 = 1
invariant :wait_27 + -1'P_await_13_4 + done_27 = 0
invariant :wait_21 + -1'P_await_13_3 + done_21 = 0
invariant :wait_33 + -1'P_await_13_5 + done_33 = 0
invariant :x_0 + x_1 + x_2 + x_3 + x_4 + x_5 = 1
invariant :wait_1 + -1'P_await_13_0 + done_1 = 0
invariant :P_start_1_2 + P_setx_3_2 + P_setbi_5_2 + P_ify0_4_2 + P_sety_9_2 + P_ifxi_10_2 + P_setbi_11_2 + P_fordo_12_2 + P_await_13_2 + P_ifyi_15_2 + P_awaity_2 + P_CS_21_2 + P_setbi_24_2 = 1
invariant :wait_17 + -1'P_await_13_2 + done_17 = 0
invariant :wait_18 + done_18 = 0
invariant :P_start_1_3 + P_setx_3_3 + P_setbi_5_3 + P_ify0_4_3 + P_sety_9_3 + P_ifxi_10_3 + P_setbi_11_3 + P_fordo_12_3 + P_await_13_3 + P_ifyi_15_3 + P_awaity_3 + P_CS_21_3 + P_setbi_24_3 = 1
invariant :b_4 + b_5 = 1
invariant :wait_0 + done_0 = 0
invariant :b_10 + b_11 = 1
invariant :wait_8 + -1'P_await_13_1 + done_8 = 0
invariant :wait_7 + -1'P_await_13_1 + done_7 = 0
invariant :P_start_1_0 + P_setx_3_0 + P_setbi_5_0 + P_ify0_4_0 + P_sety_9_0 + P_ifxi_10_0 + P_setbi_11_0 + P_fordo_12_0 + P_await_13_0 + P_ifyi_15_0 + P_awaity_0 + P_CS_21_0 + P_setbi_24_0 = 0
invariant :wait_3 + -1'P_await_13_0 + done_3 = 0
invariant :wait_28 + -1'P_await_13_4 + done_28 = 0
invariant :wait_34 + -1'P_await_13_5 + done_34 = 0
invariant :b_8 + b_9 = 1
invariant :wait_19 + -1'P_await_13_3 + done_19 = 0
invariant :wait_14 + -1'P_await_13_2 + done_14 = 0
invariant :wait_24 + done_24 = 0
invariant :wait_4 + -1'P_await_13_0 + done_4 = 0
invariant :wait_32 + -1'P_await_13_5 + done_32 = 0
invariant :wait_12 + done_12 = 0
invariant :b_6 + b_7 = 1
invariant :b_0 + b_1 = 0
invariant :wait_2 + -1'P_await_13_0 + done_2 = 0
invariant :wait_15 + -1'P_await_13_2 + done_15 = 0
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-01 TRUE TECHNIQUES SAT_SMT TAUTOLOGY
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 246
// Phase 1: matrix 246 rows 174 cols
invariant :P_start_1_1 + P_setx_3_1 + P_setbi_5_1 + P_ify0_4_1 + P_sety_9_1 + P_ifxi_10_1 + P_setbi_11_1 + P_fordo_12_1 + P_await_13_1 + P_ifyi_15_1 + P_awaity_1 + P_CS_21_1 + P_setbi_24_1 = 1
invariant :wait_11 + -1'P_await_13_1 + done_11 = 0
invariant :wait_6 + done_6 = 0
invariant :wait_9 + -1'P_await_13_1 + done_9 = 0
invariant :wait_13 + -1'P_await_13_2 + done_13 = 0
invariant :wait_35 + -1'P_await_13_5 + done_35 = 0
invariant :wait_23 + -1'P_await_13_3 + done_23 = 0
invariant :wait_5 + -1'P_await_13_0 + done_5 = 0
invariant :wait_25 + -1'P_await_13_4 + done_25 = 0
invariant :wait_31 + -1'P_await_13_5 + done_31 = 0
invariant :wait_10 + -1'P_await_13_1 + done_10 = 0
invariant :y_0 + y_1 + y_2 + y_3 + y_4 + y_5 = 1
invariant :b_2 + b_3 = 1
invariant :wait_16 + -1'P_await_13_2 + done_16 = 0
invariant :wait_20 + -1'P_await_13_3 + done_20 = 0
invariant :wait_26 + -1'P_await_13_4 + done_26 = 0
invariant :wait_29 + -1'P_await_13_4 + done_29 = 0
invariant :P_start_1_5 + P_setx_3_5 + P_setbi_5_5 + P_ify0_4_5 + P_sety_9_5 + P_ifxi_10_5 + P_setbi_11_5 + P_fordo_12_5 + P_await_13_5 + P_ifyi_15_5 + P_awaity_5 + P_CS_21_5 + P_setbi_24_5 = 1
invariant :wait_30 + done_30 = 0
invariant :wait_22 + -1'P_await_13_3 + done_22 = 0
invariant :P_start_1_4 + P_setx_3_4 + P_setbi_5_4 + P_ify0_4_4 + P_sety_9_4 + P_ifxi_10_4 + P_setbi_11_4 + P_fordo_12_4 + P_await_13_4 + P_ifyi_15_4 + P_awaity_4 + P_CS_21_4 + P_setbi_24_4 = 1
invariant :wait_27 + -1'P_await_13_4 + done_27 = 0
invariant :wait_21 + -1'P_await_13_3 + done_21 = 0
invariant :wait_33 + -1'P_await_13_5 + done_33 = 0
invariant :x_0 + x_1 + x_2 + x_3 + x_4 + x_5 = 1
invariant :wait_1 + -1'P_await_13_0 + done_1 = 0
invariant :P_start_1_2 + P_setx_3_2 + P_setbi_5_2 + P_ify0_4_2 + P_sety_9_2 + P_ifxi_10_2 + P_setbi_11_2 + P_fordo_12_2 + P_await_13_2 + P_ifyi_15_2 + P_awaity_2 + P_CS_21_2 + P_setbi_24_2 = 1
invariant :wait_17 + -1'P_await_13_2 + done_17 = 0
invariant :wait_18 + done_18 = 0
invariant :P_start_1_3 + P_setx_3_3 + P_setbi_5_3 + P_ify0_4_3 + P_sety_9_3 + P_ifxi_10_3 + P_setbi_11_3 + P_fordo_12_3 + P_await_13_3 + P_ifyi_15_3 + P_awaity_3 + P_CS_21_3 + P_setbi_24_3 = 1
invariant :b_4 + b_5 = 1
invariant :wait_0 + done_0 = 0
invariant :b_10 + b_11 = 1
invariant :wait_8 + -1'P_await_13_1 + done_8 = 0
invariant :wait_7 + -1'P_await_13_1 + done_7 = 0
invariant :P_start_1_0 + P_setx_3_0 + P_setbi_5_0 + P_ify0_4_0 + P_sety_9_0 + P_ifxi_10_0 + P_setbi_11_0 + P_fordo_12_0 + P_await_13_0 + P_ifyi_15_0 + P_awaity_0 + P_CS_21_0 + P_setbi_24_0 = 0
invariant :wait_3 + -1'P_await_13_0 + done_3 = 0
invariant :wait_28 + -1'P_await_13_4 + done_28 = 0
invariant :wait_34 + -1'P_await_13_5 + done_34 = 0
invariant :b_8 + b_9 = 1
invariant :wait_19 + -1'P_await_13_3 + done_19 = 0
invariant :wait_14 + -1'P_await_13_2 + done_14 = 0
invariant :wait_24 + done_24 = 0
invariant :wait_4 + -1'P_await_13_0 + done_4 = 0
invariant :wait_32 + -1'P_await_13_5 + done_32 = 0
invariant :wait_12 + done_12 = 0
invariant :b_6 + b_7 = 1
invariant :b_0 + b_1 = 0
invariant :wait_2 + -1'P_await_13_0 + done_2 = 0
invariant :wait_15 + -1'P_await_13_2 + done_15 = 0
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-02 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-10 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-11 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O2, model.c], workingDir=/home/mcc/execution]
Compilation finished in 5531 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 55 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality00==true], workingDir=/home/mcc/execution]
LTSmin run took 7382 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality03==true], workingDir=/home/mcc/execution]
LTSmin run took 17607 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality04==true], workingDir=/home/mcc/execution]
LTSmin run took 856 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-04 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality05==true], workingDir=/home/mcc/execution]
LTSmin run took 963 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-05 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality06==true], workingDir=/home/mcc/execution]
LTSmin run took 1744 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-06 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality07==true], workingDir=/home/mcc/execution]
LTSmin run took 765 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-07 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality08==true], workingDir=/home/mcc/execution]
LTSmin run took 1351 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-08 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality09==true], workingDir=/home/mcc/execution]
LTSmin run took 1258 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-09 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality12==true], workingDir=/home/mcc/execution]
LTSmin run took 1135 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality13==true], workingDir=/home/mcc/execution]
LTSmin run took 875 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality14==true], workingDir=/home/mcc/execution]
LTSmin run took 708 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-14 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality15==true], workingDir=/home/mcc/execution]
LTSmin run took 2829 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1552758773630

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ ReachabilityCardinality = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Mar 16, 2019 5:48:09 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Mar 16, 2019 5:48:09 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Mar 16, 2019 5:48:09 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
Mar 16, 2019 5:48:10 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Load time of PNML (colored model parsed with PNMLFW) : 984 ms
Mar 16, 2019 5:48:10 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 18 places.
Mar 16, 2019 5:48:10 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Computed order using colors.
Mar 16, 2019 5:48:10 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: sort/places :pid * pid->wait,done,
pid * bool->b,
pid->P-start_1,x,y,P-setx_3,P-setbi_5,P-ify0_4,P-sety_9,P-ifxi_10,P-setbi_11,P-fordo_12,P-await_13,P-ifyi_15,P-awaity,P-CS_21,P-setbi_24,

Mar 16, 2019 5:48:10 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 17 transitions.
Mar 16, 2019 5:48:10 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Computed order based on color domains.
Mar 16, 2019 5:48:10 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 10 ms
Mar 16, 2019 5:48:10 PM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $i and $y of transition T_yeqi_15
Mar 16, 2019 5:48:10 PM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $i and $x of transition T_xeqi_10
Mar 16, 2019 5:48:10 PM fr.lip6.move.gal.instantiate.Instantiator instantiateParameters
INFO: On-the-fly reduction of False transitions avoided exploring 13.0 instantiations of transitions. Total transitions/syncs built is 333
Mar 16, 2019 5:48:10 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 181 ms
Mar 16, 2019 5:48:11 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 79 ms
Mar 16, 2019 5:48:11 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 15 ms
Mar 16, 2019 5:48:11 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 68 ms
Mar 16, 2019 5:48:11 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 8 ms
Mar 16, 2019 5:48:12 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 82 transitions. Expanding to a total of 399 deterministic transitions.
Mar 16, 2019 5:48:12 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 82 transitions. Expanding to a total of 399 deterministic transitions.
Mar 16, 2019 5:48:12 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 22 ms.
Mar 16, 2019 5:48:12 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 21 ms.
Mar 16, 2019 5:48:12 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 50 place invariants in 85 ms
Mar 16, 2019 5:48:12 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 1 / 16 in 908 ms.
Mar 16, 2019 5:48:12 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(UNSAT) depth K=0 took 57 ms
Mar 16, 2019 5:48:12 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(UNSAT) depth K=0 took 20 ms
Mar 16, 2019 5:48:12 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 82 transitions. Expanding to a total of 399 deterministic transitions.
Mar 16, 2019 5:48:12 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(UNSAT) depth K=0 took 15 ms
Mar 16, 2019 5:48:12 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 10 ms.
Mar 16, 2019 5:48:12 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(UNSAT) depth K=0 took 11 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(UNSAT) depth K=0 took 15 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(UNSAT) depth K=0 took 11 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(UNSAT) depth K=0 took 3 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(UNSAT) depth K=0 took 3 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(UNSAT) depth K=0 took 12 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(UNSAT) depth K=0 took 11 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(UNSAT) depth K=0 took 7 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(UNSAT) depth K=0 took 11 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(UNSAT) depth K=0 took 15 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-14(UNSAT) depth K=0 took 11 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-15(UNSAT) depth K=0 took 13 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(UNSAT) depth K=1 took 16 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(UNSAT) depth K=1 took 12 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(UNSAT) depth K=1 took 11 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(UNSAT) depth K=1 took 14 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(UNSAT) depth K=1 took 16 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(UNSAT) depth K=1 took 13 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(UNSAT) depth K=1 took 18 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(UNSAT) depth K=1 took 26 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(UNSAT) depth K=1 took 20 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(UNSAT) depth K=1 took 22 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(UNSAT) depth K=1 took 13 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(UNSAT) depth K=1 took 14 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(UNSAT) depth K=1 took 10 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 50 place invariants in 64 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-14(UNSAT) depth K=1 took 31 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-15(UNSAT) depth K=1 took 22 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(UNSAT) depth K=2 took 213 ms
Mar 16, 2019 5:48:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(UNSAT) depth K=2 took 298 ms
Mar 16, 2019 5:48:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(UNSAT) depth K=2 took 343 ms
Mar 16, 2019 5:48:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(UNSAT) depth K=2 took 121 ms
Mar 16, 2019 5:48:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(UNSAT) depth K=2 took 133 ms
Mar 16, 2019 5:48:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(UNSAT) depth K=2 took 95 ms
Mar 16, 2019 5:48:14 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 174 variables to be positive in 2065 ms
Mar 16, 2019 5:48:14 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 318 transitions.
Mar 16, 2019 5:48:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(UNSAT) depth K=2 took 35 ms
Mar 16, 2019 5:48:14 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/318 took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 16, 2019 5:48:14 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 119 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 16, 2019 5:48:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(UNSAT) depth K=2 took 120 ms
Mar 16, 2019 5:48:14 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 318 transitions.
Mar 16, 2019 5:48:14 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 24 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 16, 2019 5:48:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(UNSAT) depth K=2 took 188 ms
Mar 16, 2019 5:48:15 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(UNSAT) depth K=2 took 103 ms
Mar 16, 2019 5:48:15 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(UNSAT) depth K=2 took 116 ms
Mar 16, 2019 5:48:15 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(UNSAT) depth K=2 took 100 ms
Mar 16, 2019 5:48:15 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(UNSAT) depth K=2 took 65 ms
Mar 16, 2019 5:48:15 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 174 variables to be positive in 2221 ms
Mar 16, 2019 5:48:15 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-14(UNSAT) depth K=2 took 214 ms
Mar 16, 2019 5:48:15 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-15(UNSAT) depth K=2 took 69 ms
Mar 16, 2019 5:48:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-00
Mar 16, 2019 5:48:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(SAT) depth K=0 took 803 ms
Mar 16, 2019 5:48:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(UNSAT) depth K=3 took 1185 ms
Mar 16, 2019 5:48:17 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(UNSAT) depth K=3 took 406 ms
Mar 16, 2019 5:48:17 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate LamportFastMutEx-COL-5-ReachabilityCardinality-02
Mar 16, 2019 5:48:17 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-COL-5-ReachabilityCardinality-02
Mar 16, 2019 5:48:17 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(FALSE) depth K=0 took 960 ms
Mar 16, 2019 5:48:17 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-03
Mar 16, 2019 5:48:17 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(SAT) depth K=0 took 257 ms
Mar 16, 2019 5:48:18 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-04
Mar 16, 2019 5:48:18 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(SAT) depth K=0 took 1214 ms
Mar 16, 2019 5:48:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(UNSAT) depth K=3 took 2164 ms
Mar 16, 2019 5:48:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-05
Mar 16, 2019 5:48:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(SAT) depth K=0 took 1209 ms
Mar 16, 2019 5:48:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(UNSAT) depth K=3 took 1002 ms
Mar 16, 2019 5:48:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-06
Mar 16, 2019 5:48:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(SAT) depth K=0 took 529 ms
Mar 16, 2019 5:48:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-07
Mar 16, 2019 5:48:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(SAT) depth K=0 took 250 ms
Mar 16, 2019 5:48:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(UNSAT) depth K=3 took 3189 ms
Mar 16, 2019 5:48:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-08
Mar 16, 2019 5:48:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(SAT) depth K=0 took 3157 ms
Mar 16, 2019 5:48:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(UNSAT) depth K=3 took 551 ms
Mar 16, 2019 5:48:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-09
Mar 16, 2019 5:48:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(SAT) depth K=0 took 908 ms
Mar 16, 2019 5:48:25 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(UNSAT) depth K=3 took 1108 ms
Mar 16, 2019 5:48:25 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant LamportFastMutEx-COL-5-ReachabilityCardinality-10
Mar 16, 2019 5:48:25 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-COL-5-ReachabilityCardinality-10
Mar 16, 2019 5:48:25 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(TRUE) depth K=0 took 646 ms
Mar 16, 2019 5:48:25 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(UNSAT) depth K=3 took 635 ms
Mar 16, 2019 5:48:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant LamportFastMutEx-COL-5-ReachabilityCardinality-11
Mar 16, 2019 5:48:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-COL-5-ReachabilityCardinality-11
Mar 16, 2019 5:48:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(TRUE) depth K=0 took 552 ms
Mar 16, 2019 5:48:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-12
Mar 16, 2019 5:48:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(SAT) depth K=0 took 460 ms
Mar 16, 2019 5:48:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-13
Mar 16, 2019 5:48:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(SAT) depth K=0 took 271 ms
Mar 16, 2019 5:48:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-14
Mar 16, 2019 5:48:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-14(SAT) depth K=0 took 338 ms
Mar 16, 2019 5:48:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-15
Mar 16, 2019 5:48:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-15(SAT) depth K=0 took 655 ms
Mar 16, 2019 5:48:29 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(UNSAT) depth K=3 took 4028 ms
Mar 16, 2019 5:48:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-00
Mar 16, 2019 5:48:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(SAT) depth K=1 took 4863 ms
Mar 16, 2019 5:48:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(UNSAT) depth K=3 took 2943 ms
Mar 16, 2019 5:48:33 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(UNSAT) depth K=3 took 1071 ms
Mar 16, 2019 5:48:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-03
Mar 16, 2019 5:48:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(SAT) depth K=1 took 3889 ms
Mar 16, 2019 5:48:37 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(UNSAT) depth K=3 took 3148 ms
Mar 16, 2019 5:48:37 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(UNSAT) depth K=3 took 493 ms
Mar 16, 2019 5:48:41 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-14(UNSAT) depth K=3 took 3994 ms
Mar 16, 2019 5:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-15(UNSAT) depth K=3 took 1242 ms
Mar 16, 2019 5:48:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-04
Mar 16, 2019 5:48:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(SAT) depth K=1 took 7252 ms
Mar 16, 2019 5:48:56 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 318 transitions.
Mar 16, 2019 5:48:57 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/318) took 574 ms. Total solver calls (SAT/UNSAT): 57(0/57)
Mar 16, 2019 5:48:57 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(UNSAT) depth K=4 took 14982 ms
Mar 16, 2019 5:48:58 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-05
Mar 16, 2019 5:48:58 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(SAT) depth K=1 took 15151 ms
Mar 16, 2019 5:48:59 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-06
Mar 16, 2019 5:48:59 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(SAT) depth K=1 took 847 ms
Mar 16, 2019 5:49:00 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(6/318) took 3607 ms. Total solver calls (SAT/UNSAT): 396(15/381)
Mar 16, 2019 5:49:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-07
Mar 16, 2019 5:49:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(SAT) depth K=1 took 744 ms
Mar 16, 2019 5:49:03 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(12/318) took 7079 ms. Total solver calls (SAT/UNSAT): 788(25/763)
Mar 16, 2019 5:49:07 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(16/318) took 10821 ms. Total solver calls (SAT/UNSAT): 1218(25/1193)
Mar 16, 2019 5:49:11 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(20/318) took 14422 ms. Total solver calls (SAT/UNSAT): 1632(52/1580)
Mar 16, 2019 5:49:14 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(24/318) took 18033 ms. Total solver calls (SAT/UNSAT): 2030(87/1943)
Mar 16, 2019 5:49:18 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(28/318) took 21483 ms. Total solver calls (SAT/UNSAT): 2412(119/2293)
Mar 16, 2019 5:49:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(UNSAT) depth K=4 took 22800 ms
Mar 16, 2019 5:49:21 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(32/318) took 24719 ms. Total solver calls (SAT/UNSAT): 2778(148/2630)
Mar 16, 2019 5:49:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-08
Mar 16, 2019 5:49:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(SAT) depth K=1 took 23709 ms
Mar 16, 2019 5:49:24 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(36/318) took 27795 ms. Total solver calls (SAT/UNSAT): 3128(175/2953)
Mar 16, 2019 5:49:27 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(40/318) took 30798 ms. Total solver calls (SAT/UNSAT): 3462(199/3263)
Mar 16, 2019 5:49:29 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-09
Mar 16, 2019 5:49:29 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(SAT) depth K=1 took 5357 ms
Mar 16, 2019 5:49:31 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(45/318) took 34431 ms. Total solver calls (SAT/UNSAT): 3857(225/3632)
Mar 16, 2019 5:49:35 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(49/318) took 38803 ms. Total solver calls (SAT/UNSAT): 4345(235/4110)
Mar 16, 2019 5:49:37 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-12
Mar 16, 2019 5:49:37 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(SAT) depth K=1 took 8171 ms
Mar 16, 2019 5:49:38 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-13
Mar 16, 2019 5:49:38 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(SAT) depth K=1 took 786 ms
Mar 16, 2019 5:49:39 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(52/318) took 43239 ms. Total solver calls (SAT/UNSAT): 4843(235/4608)
Mar 16, 2019 5:49:44 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(55/318) took 47425 ms. Total solver calls (SAT/UNSAT): 5332(292/5040)
Mar 16, 2019 5:49:48 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(58/318) took 51605 ms. Total solver calls (SAT/UNSAT): 5812(348/5464)
Mar 16, 2019 5:49:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-14
Mar 16, 2019 5:49:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-14(SAT) depth K=1 took 13664 ms
Mar 16, 2019 5:49:52 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(61/318) took 55727 ms. Total solver calls (SAT/UNSAT): 6283(402/5881)
Mar 16, 2019 5:49:56 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-15
Mar 16, 2019 5:49:56 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-15(SAT) depth K=1 took 3857 ms
Mar 16, 2019 5:49:56 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(64/318) took 59986 ms. Total solver calls (SAT/UNSAT): 6745(454/6291)
Mar 16, 2019 5:50:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(UNSAT) depth K=4 took 39741 ms
Mar 16, 2019 5:50:00 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(67/318) took 63975 ms. Total solver calls (SAT/UNSAT): 7198(505/6693)
Mar 16, 2019 5:50:04 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(70/318) took 67911 ms. Total solver calls (SAT/UNSAT): 7642(553/7089)
Mar 16, 2019 5:50:08 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(73/318) took 71843 ms. Total solver calls (SAT/UNSAT): 8077(600/7477)
Mar 16, 2019 5:50:12 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-00
Mar 16, 2019 5:50:12 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(SAT) depth K=2 took 16305 ms
Mar 16, 2019 5:50:12 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(76/318) took 75790 ms. Total solver calls (SAT/UNSAT): 8503(645/7858)
Mar 16, 2019 5:50:15 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(82/318) took 79115 ms. Total solver calls (SAT/UNSAT): 8861(670/8191)
Mar 16, 2019 5:50:18 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(89/318) took 82154 ms. Total solver calls (SAT/UNSAT): 9165(685/8480)
Mar 16, 2019 5:50:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-03
Mar 16, 2019 5:50:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(SAT) depth K=2 took 7184 ms
Mar 16, 2019 5:50:22 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(92/318) took 86004 ms. Total solver calls (SAT/UNSAT): 9573(732/8841)
Mar 16, 2019 5:50:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(UNSAT) depth K=4 took 24540 ms
Mar 16, 2019 5:50:26 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(95/318) took 89695 ms. Total solver calls (SAT/UNSAT): 9972(795/9177)
Mar 16, 2019 5:50:29 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(98/318) took 93274 ms. Total solver calls (SAT/UNSAT): 10362(832/9530)
Mar 16, 2019 5:50:33 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(101/318) took 96850 ms. Total solver calls (SAT/UNSAT): 10743(880/9863)
Mar 16, 2019 5:50:37 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(104/318) took 100379 ms. Total solver calls (SAT/UNSAT): 11115(880/10235)
Mar 16, 2019 5:50:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(107/318) took 103670 ms. Total solver calls (SAT/UNSAT): 11478(880/10598)
Mar 16, 2019 5:50:43 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(110/318) took 106930 ms. Total solver calls (SAT/UNSAT): 11832(922/10910)
Mar 16, 2019 5:50:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(UNSAT) depth K=4 took 18859 ms
Mar 16, 2019 5:50:46 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(113/318) took 110183 ms. Total solver calls (SAT/UNSAT): 12177(964/11213)
Mar 16, 2019 5:50:49 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(116/318) took 113330 ms. Total solver calls (SAT/UNSAT): 12513(1003/11510)
Mar 16, 2019 5:50:51 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-04
Mar 16, 2019 5:50:51 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(SAT) depth K=2 took 31688 ms
Mar 16, 2019 5:50:53 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(119/318) took 116471 ms. Total solver calls (SAT/UNSAT): 12840(1042/11798)
Mar 16, 2019 5:50:55 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-05
Mar 16, 2019 5:50:55 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(SAT) depth K=2 took 4101 ms
Mar 16, 2019 5:50:57 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(123/318) took 120471 ms. Total solver calls (SAT/UNSAT): 13262(1090/12172)
Mar 16, 2019 5:51:00 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(127/318) took 124255 ms. Total solver calls (SAT/UNSAT): 13668(1136/12532)
Mar 16, 2019 5:51:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(UNSAT) depth K=4 took 20497 ms
Mar 16, 2019 5:51:04 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(131/318) took 127971 ms. Total solver calls (SAT/UNSAT): 14058(1180/12878)
Mar 16, 2019 5:51:08 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(135/318) took 131467 ms. Total solver calls (SAT/UNSAT): 14432(1220/13212)
Mar 16, 2019 5:51:11 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(140/318) took 134894 ms. Total solver calls (SAT/UNSAT): 14787(1240/13547)
Mar 16, 2019 5:51:14 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(147/318) took 138227 ms. Total solver calls (SAT/UNSAT): 15158(1261/13897)
Mar 16, 2019 5:51:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-06
Mar 16, 2019 5:51:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(SAT) depth K=2 took 20958 ms
Mar 16, 2019 5:51:17 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(UNSAT) depth K=4 took 13518 ms
Mar 16, 2019 5:51:17 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-07
Mar 16, 2019 5:51:17 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(SAT) depth K=2 took 1635 ms
Mar 16, 2019 5:51:18 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(154/318) took 141673 ms. Total solver calls (SAT/UNSAT): 15480(1284/14196)
Mar 16, 2019 5:51:21 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(162/318) took 144690 ms. Total solver calls (SAT/UNSAT): 15788(1300/14488)
Mar 16, 2019 5:51:24 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(172/318) took 147974 ms. Total solver calls (SAT/UNSAT): 16091(1315/14776)
Mar 16, 2019 5:51:27 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(183/318) took 150975 ms. Total solver calls (SAT/UNSAT): 16378(1330/15048)
Mar 16, 2019 5:51:30 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(195/318) took 154135 ms. Total solver calls (SAT/UNSAT): 16673(1353/15320)
Mar 16, 2019 5:51:33 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(209/318) took 157235 ms. Total solver calls (SAT/UNSAT): 16990(1417/15573)
Mar 16, 2019 5:51:37 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(225/318) took 160399 ms. Total solver calls (SAT/UNSAT): 17298(1450/15848)
Mar 16, 2019 5:51:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(231/318) took 163406 ms. Total solver calls (SAT/UNSAT): 17618(1450/16168)
Mar 16, 2019 5:51:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(UNSAT) depth K=4 took 24467 ms
Mar 16, 2019 5:51:43 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(236/318) took 166690 ms. Total solver calls (SAT/UNSAT): 17958(1487/16471)
Mar 16, 2019 5:51:46 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(242/318) took 170247 ms. Total solver calls (SAT/UNSAT): 18333(1538/16795)
Mar 16, 2019 5:51:50 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(248/318) took 173547 ms. Total solver calls (SAT/UNSAT): 18672(1583/17089)
Mar 16, 2019 5:51:50 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-08
Mar 16, 2019 5:51:50 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(SAT) depth K=2 took 32802 ms
Mar 16, 2019 5:51:53 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(255/318) took 176954 ms. Total solver calls (SAT/UNSAT): 19022(1628/17394)
Mar 16, 2019 5:51:56 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(263/318) took 180258 ms. Total solver calls (SAT/UNSAT): 19362(1665/17697)
Mar 16, 2019 5:52:00 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(277/318) took 183475 ms. Total solver calls (SAT/UNSAT): 19693(1673/18020)
Mar 16, 2019 5:52:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(UNSAT) depth K=4 took 18363 ms
Mar 16, 2019 5:52:03 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(291/318) took 186527 ms. Total solver calls (SAT/UNSAT): 20008(1715/18293)
Mar 16, 2019 5:52:03 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-09
Mar 16, 2019 5:52:03 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(SAT) depth K=2 took 13071 ms
Mar 16, 2019 5:52:04 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 187954 ms. Total solver calls (SAT/UNSAT): 20133(1725/18408)
Mar 16, 2019 5:52:04 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 318 transitions.
Mar 16, 2019 5:52:09 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 4414 ms. Total solver calls (SAT/UNSAT): 235(0/235)
Mar 16, 2019 5:52:09 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 237026ms conformant to PINS in folder :/home/mcc/execution
Mar 16, 2019 5:52:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-12
Mar 16, 2019 5:52:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(SAT) depth K=2 took 17041 ms
Mar 16, 2019 5:52:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(UNSAT) depth K=4 took 22433 ms
Mar 16, 2019 5:52:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-13
Mar 16, 2019 5:52:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(SAT) depth K=2 took 3164 ms
Mar 16, 2019 5:52:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
Mar 16, 2019 5:52:52 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Mar 16, 2019 5:52:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
WARNING: Unexpected error occurred while running SMT. Was verifying LamportFastMutEx-COL-5-ReachabilityCardinality-14 SMT depth 4
java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:404)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
... 3 more
Mar 16, 2019 5:52:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: During BMC, SMT solver timed out at depth 4
Mar 16, 2019 5:52:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solving timed out (3600000 secs) at depth 4
Mar 16, 2019 5:52:52 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
Mar 16, 2019 5:52:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
WARNING: Unexpected error occurred while running SMT. Was verifying LamportFastMutEx-COL-5-ReachabilityCardinality-14 K-induction depth 2
Exception in thread "Thread-8" java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:336)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
... 3 more
Mar 16, 2019 5:52:52 PM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 4/ 16 properties. Interrupting other analysis methods.

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-COL-5"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3957"
echo " Executing tool itstools"
echo " Input is LamportFastMutEx-COL-5, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r096-smll-155246587200152"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-COL-5.tgz
mv LamportFastMutEx-COL-5 execution
cd execution
if [ "ReachabilityCardinality" = "GlobalProperties" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;