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Model Checking Contest 2019
9th edition, Prague, Czech Republic, April 7, 2019 (TOOLympics)
Execution of r191-smll-155229651700160
Last Updated
Apr 15, 2019

About the Execution of ITS-Tools.M for CloudReconfiguration-PT-306

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
9079.510 3600000.00 14287054.00 409.00 FFFFFFFFFFF?FFFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2019-input.r191-smll-155229651700160.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2019-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
.......................
=====================================================================
Generated by BenchKit 2-3957
Executing tool itstoolsm
Input is CloudReconfiguration-PT-306, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r191-smll-155229651700160
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 824K
-rw-r--r-- 1 mcc users 3.7K Feb 9 09:23 CTLCardinality.txt
-rw-r--r-- 1 mcc users 20K Feb 9 09:23 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 5 08:19 CTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 5 08:19 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 10 17:31 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K Mar 10 17:31 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 114 Feb 24 15:05 GlobalProperties.txt
-rw-r--r-- 1 mcc users 352 Feb 24 15:05 GlobalProperties.xml
-rw-r--r-- 1 mcc users 2.5K Feb 4 23:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K Feb 4 23:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Feb 4 22:33 LTLFireability.txt
-rw-r--r-- 1 mcc users 9.3K Feb 4 22:33 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.3K Feb 2 02:18 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 15K Feb 2 02:18 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.0K Jan 29 16:04 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 17K Jan 29 16:04 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 4 22:18 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 4 22:18 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jan 29 09:34 equiv_col
-rw-r--r-- 1 mcc users 4 Jan 29 09:34 instance
-rw-r--r-- 1 mcc users 6 Jan 29 09:34 iscolored
-rw-r--r-- 1 mcc users 660K Mar 10 17:31 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME CloudReconfiguration-PT-306-LTLFireability-00
FORMULA_NAME CloudReconfiguration-PT-306-LTLFireability-01
FORMULA_NAME CloudReconfiguration-PT-306-LTLFireability-02
FORMULA_NAME CloudReconfiguration-PT-306-LTLFireability-03
FORMULA_NAME CloudReconfiguration-PT-306-LTLFireability-04
FORMULA_NAME CloudReconfiguration-PT-306-LTLFireability-05
FORMULA_NAME CloudReconfiguration-PT-306-LTLFireability-06
FORMULA_NAME CloudReconfiguration-PT-306-LTLFireability-07
FORMULA_NAME CloudReconfiguration-PT-306-LTLFireability-08
FORMULA_NAME CloudReconfiguration-PT-306-LTLFireability-09
FORMULA_NAME CloudReconfiguration-PT-306-LTLFireability-10
FORMULA_NAME CloudReconfiguration-PT-306-LTLFireability-11
FORMULA_NAME CloudReconfiguration-PT-306-LTLFireability-12
FORMULA_NAME CloudReconfiguration-PT-306-LTLFireability-13
FORMULA_NAME CloudReconfiguration-PT-306-LTLFireability-14
FORMULA_NAME CloudReconfiguration-PT-306-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1553677606077

Working with output stream class java.io.PrintStream
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Running greatSPN : CommandLine [args=[/home/mcc/BenchKit//greatspn//bin/pinvar, /home/mcc/execution/gspn], workingDir=/home/mcc/execution]
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O2, model.c], workingDir=/home/mcc/execution]
Run of greatSPN captured in /home/mcc/execution/outPut.txt
Running greatSPN : CommandLine [args=[/home/mcc/BenchKit//greatspn//bin/RGMEDD2, /home/mcc/execution/gspn, -META, -varord-only], workingDir=/home/mcc/execution]
Run of greatSPN captured in /home/mcc/execution/outPut.txt
Using order generated by GreatSPN with heuristic : META
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903251645/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock, --load-order, /home/mcc/execution/model.ord], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903251645/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock --load-order /home/mcc/execution/model.ord
Read 16 LTL properties
Successfully loaded order from file /home/mcc/execution/model.ord
Checking formula 0 : !((G(F(("(p298>=1)")U(X("(p1534>=1)"))))))
Formula 0 simplified : !GF("(p298>=1)" U X"(p1534>=1)")
Compilation finished in 45036 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 81 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, [](<>(((LTLAP0==true))U(X((LTLAP1==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 5225 ms.
FORMULA CloudReconfiguration-PT-306-LTLFireability-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, <>(X((LTLAP2==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 3241 ms.
FORMULA CloudReconfiguration-PT-306-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, []([]((<>((LTLAP3==true)))U((LTLAP4==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, []([]((<>((LTLAP3==true)))U((LTLAP4==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, <>(<>(X(X((LTLAP5==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 2380 ms.
FORMULA CloudReconfiguration-PT-306-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, false, --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, false, --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, []([](((LTLAP6==true))U([]((LTLAP7==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, []([](((LTLAP6==true))U([]((LTLAP7==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, <>(<>(([]((LTLAP8==true)))U([]((LTLAP9==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, <>(<>(([]((LTLAP8==true)))U([]((LTLAP9==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, (X((LTLAP10==true)))U((LTLAP11==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 2663 ms.
FORMULA CloudReconfiguration-PT-306-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, (([]((LTLAP12==true)))U(X((LTLAP13==true))))U(([]((LTLAP14==true)))U((LTLAP15==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 2459 ms.
FORMULA CloudReconfiguration-PT-306-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, false, --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, false, --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X([](([]((LTLAP16==true)))U((LTLAP13==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 3437 ms.
FORMULA CloudReconfiguration-PT-306-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, []((LTLAP17==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
Detected timeout of ITS tools.
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903251645/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903251645/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 10 LTL properties
Checking formula 0 : !((G(G((F("(i0.i1.i0.u6.p1532>=1)"))U("(i0.u2.p432>=1)")))))
Formula 0 simplified : !G(F"(i0.i1.i0.u6.p1532>=1)" U "(i0.u2.p432>=1)")
built 2 ordering constraints for composite.
built 11 ordering constraints for composite.
built 16 ordering constraints for composite.
built 12 ordering constraints for composite.
Reverse transition relation is NOT exact ! Due to transitions t2868, i0.u2.t3, i0.u2.t4, i0.u2.t5, i0.u2.t2181, i0.u2.t2197, i0.u2.t2202, i0.u2.t2207, i0.u2.t2238, i0.u2.t2367, i0.u2.t2395, i0.u2.t2401, i0.u2.t2406, i0.u2.t2408, i0.u2.t2417, i0.u2.t2422, i0.u2.t2427, i0.u2.t2458, i0.u2.t2587, i0.u2.t2615, i0.u2.t2621, i0.u2.t2626, i0.u2.t2628, i0.u2.t2637, i0.u2.t2642, i0.u2.t2647, i0.u2.t2678, i0.u2.t2807, i0.u2.t2835, i0.u2.t2841, i0.u2.t2846, i0.u2.t2848, i0.u2.t2854, i0.u2.t2860, i0.u2.t2866, i0.i1.u7.t29, i0.i1.u7.t32, i0.i1.u7.t36, i0.i1.u7.t58, i0.i1.u7.t59, i0.i1.u7.t62, i0.i1.u7.t69, i0.i1.u7.t80, i0.i1.u7.t84, i0.i1.u7.t89, i0.i1.u7.t96, i0.i1.u7.t98, i0.i1.u7.t113, i0.i1.u7.t116, i0.i1.u7.t123, i0.i1.u7.t134, i0.i1.u7.t138, i0.i1.u7.t143, i0.i1.u7.t150, i0.i1.u7.t152, i0.i1.u7.t154, i0.i1.u7.t165, i0.i1.u7.t167, i0.i1.u7.t169, i0.i1.u7.t171, i0.i1.u7.t173, i0.i1.u7.t175, i0.i1.u7.t187, i0.i1.u7.t189, i0.i1.u7.t191, i0.i1.u7.t214, i0.i1.u7.t216, i0.i1.u7.t228, i0.i1.u7.t232, i0.i1.u7.t236, i0.i1.u7.t238, i0.i1.u7.t240, i0.i1.u7.t245, i0.i1.u7.t252, i0.i1.u7.t254, i0.i1.u7.t259, i0.i1.u7.t266, i0.i1.u7.t268, i0.i1.u7.t270, i0.i1.u7.t276, i0.i1.u7.t283, i0.i1.u7.t285, i0.i1.u7.t287, i0.i1.u7.t289, i0.i1.u7.t291, i0.i1.u7.t297, i0.i1.u7.t298, i0.i1.u7.t300, i0.i1.u7.t302, i0.i1.u7.t322, i0.i1.u7.t323, i0.i1.u7.t329, i0.i1.u7.t353, i0.i1.u7.t364, i0.i1.u7.t394, i0.i1.u7.t403, i0.i1.u7.t435, i0.i1.u7.t452, i0.i1.u7.t454, i0.i1.u7.t461, i0.i1.u7.t480, i0.i1.u7.t481, i0.i1.u7.t487, i0.i1.u7.t511, i0.i1.u7.t522, i0.i1.u7.t548, i0.i1.u7.t557, i0.i1.u7.t589, i0.i1.u7.t604, i0.i1.u7.t606, i0.i1.u7.t696, i0.i1.u7.t717, i0.i1.u7.t733, i0.i1.u7.t741, i0.i1.i0.u5.t1464, i0.i1.i0.u5.t1467, i0.i1.i0.u5.t1471, i0.i1.i0.u5.t1493, i0.i1.i0.u5.t1494, i0.i1.i0.u5.t1497, i0.i1.i0.u5.t1504, i0.i1.i0.u5.t1515, i0.i1.i0.u5.t1519, i0.i1.i0.u5.t1524, i0.i1.i0.u5.t1531, i0.i1.i0.u5.t1533, i0.i1.i0.u5.t1548, i0.i1.i0.u5.t1551, i0.i1.i0.u5.t1558, i0.i1.i0.u5.t1569, i0.i1.i0.u5.t1573, i0.i1.i0.u5.t1578, i0.i1.i0.u5.t1585, i0.i1.i0.u5.t1587, i0.i1.i0.u5.t1589, i0.i1.i0.u5.t1600, i0.i1.i0.u5.t1602, i0.i1.i0.u5.t1604, i0.i1.i0.u5.t1606, i0.i1.i0.u5.t1608, i0.i1.i0.u5.t1610, i0.i1.i0.u5.t1622, i0.i1.i0.u5.t1624, i0.i1.i0.u5.t1626, i0.i1.i0.u5.t1649, i0.i1.i0.u5.t1651, i0.i1.i0.u5.t1663, i0.i1.i0.u5.t1667, i0.i1.i0.u5.t1671, i0.i1.i0.u5.t1673, i0.i1.i0.u5.t1675, i0.i1.i0.u5.t1680, i0.i1.i0.u5.t1687, i0.i1.i0.u5.t1689, i0.i1.i0.u5.t1694, i0.i1.i0.u5.t1701, i0.i1.i0.u5.t1703, i0.i1.i0.u5.t1705, i0.i1.i0.u5.t1711, i0.i1.i0.u5.t1718, i0.i1.i0.u5.t1720, i0.i1.i0.u5.t1722, i0.i1.i0.u5.t1724, i0.i1.i0.u5.t1726, i0.i1.i0.u5.t1732, i0.i1.i0.u5.t1733, i0.i1.i0.u5.t1735, i0.i1.i0.u5.t1737, i0.i1.i0.u5.t1757, i0.i1.i0.u5.t1758, i0.i1.i0.u5.t1764, i0.i1.i0.u5.t1788, i0.i1.i0.u5.t1799, i0.i1.i0.u5.t1829, i0.i1.i0.u5.t1838, i0.i1.i0.u5.t1870, i0.i1.i0.u5.t1887, i0.i1.i0.u5.t1889, i0.i1.i0.u5.t1896, i0.i1.i0.u5.t1915, i0.i1.i0.u5.t1916, i0.i1.i0.u5.t1922, i0.i1.i0.u5.t1946, i0.i1.i0.u5.t1957, i0.i1.i0.u5.t1983, i0.i1.i0.u5.t1992, i0.i1.i0.u5.t2024, i0.i1.i0.u5.t2039, i0.i1.i0.u5.t2041, i0.i1.i0.u5.t2044, i0.i1.i0.u5.t2052, i0.i1.i0.u5.t2060, i0.i1.i0.u5.t2106, i0.i1.i0.u5.t2121, i0.i1.i0.u5.t2131, i0.i1.i0.u5.t2152, i0.i1.i0.u5.t2168, i0.i1.i0.u5.t2176, i0.i1.i0.u6.t747, i0.i1.i0.u6.t750, i0.i1.i0.u6.t754, i0.i1.i0.u6.t776, i0.i1.i0.u6.t777, i0.i1.i0.u6.t780, i0.i1.i0.u6.t787, i0.i1.i0.u6.t798, i0.i1.i0.u6.t802, i0.i1.i0.u6.t807, i0.i1.i0.u6.t814, i0.i1.i0.u6.t816, i0.i1.i0.u6.t831, i0.i1.i0.u6.t834, i0.i1.i0.u6.t841, i0.i1.i0.u6.t852, i0.i1.i0.u6.t856, i0.i1.i0.u6.t861, i0.i1.i0.u6.t868, i0.i1.i0.u6.t870, i0.i1.i0.u6.t872, i0.i1.i0.u6.t883, i0.i1.i0.u6.t885, i0.i1.i0.u6.t887, i0.i1.i0.u6.t889, i0.i1.i0.u6.t891, i0.i1.i0.u6.t893, i0.i1.i0.u6.t905, i0.i1.i0.u6.t907, i0.i1.i0.u6.t909, i0.i1.i0.u6.t932, i0.i1.i0.u6.t934, i0.i1.i0.u6.t946, i0.i1.i0.u6.t950, i0.i1.i0.u6.t954, i0.i1.i0.u6.t956, i0.i1.i0.u6.t958, i0.i1.i0.u6.t963, i0.i1.i0.u6.t970, i0.i1.i0.u6.t972, i0.i1.i0.u6.t977, i0.i1.i0.u6.t984, i0.i1.i0.u6.t986, i0.i1.i0.u6.t988, i0.i1.i0.u6.t994, i0.i1.i0.u6.t1001, i0.i1.i0.u6.t1003, i0.i1.i0.u6.t1005, i0.i1.i0.u6.t1007, i0.i1.i0.u6.t1009, i0.i1.i0.u6.t1015, i0.i1.i0.u6.t1016, i0.i1.i0.u6.t1018, i0.i1.i0.u6.t1020, i0.i1.i0.u6.t1040, i0.i1.i0.u6.t1041, i0.i1.i0.u6.t1047, i0.i1.i0.u6.t1071, i0.i1.i0.u6.t1082, i0.i1.i0.u6.t1112, i0.i1.i0.u6.t1121, i0.i1.i0.u6.t1153, i0.i1.i0.u6.t1170, i0.i1.i0.u6.t1172, i0.i1.i0.u6.t1179, i0.i1.i0.u6.t1198, i0.i1.i0.u6.t1199, i0.i1.i0.u6.t1205, i0.i1.i0.u6.t1229, i0.i1.i0.u6.t1240, i0.i1.i0.u6.t1266, i0.i1.i0.u6.t1275, i0.i1.i0.u6.t1307, i0.i1.i0.u6.t1322, i0.i1.i0.u6.t1324, i0.i1.i0.u6.t1414, i0.i1.i0.u6.t1435, i0.i1.i0.u6.t1451, i0.i1.i0.u6.t1459, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :162/2533/277/2972
Computing Next relation with stutter on 202760 deadlock states
42 unique states visited
42 strongly connected components in search stack
43 transitions explored
42 items max in DFS search stack
3254 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,32.8209,621756,1,0,91800,824615,32885,140386,30174,4.20424e+06,656908
an accepting run exists (use option '-e' to print it)
Formula 0 is FALSE accepting run found.
FORMULA CloudReconfiguration-PT-306-LTLFireability-02 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 1 : !((false))
Formula 1 simplified : 1
Computing Next relation with stutter on 202760 deadlock states
2 unique states visited
2 strongly connected components in search stack
2 transitions explored
2 items max in DFS search stack
0 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,32.8221,621756,1,0,91800,824615,32887,140386,30174,4.20424e+06,656911
an accepting run exists (use option '-e' to print it)
Formula 1 is FALSE accepting run found.
FORMULA CloudReconfiguration-PT-306-LTLFireability-04 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 2 : !((G(G(("(i0.u2.p485>=1)")U(G("(i0.i1.i0.u6.p1892>=1)"))))))
Formula 2 simplified : !G("(i0.u2.p485>=1)" U G"(i0.i1.i0.u6.p1892>=1)")
Computing Next relation with stutter on 202760 deadlock states
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
0 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,32.8259,622332,1,0,91801,824615,32930,140389,30176,4.20424e+06,656978
an accepting run exists (use option '-e' to print it)
Formula 2 is FALSE accepting run found.
FORMULA CloudReconfiguration-PT-306-LTLFireability-05 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 3 : !((F(F((G("(i0.u2.p547>=1)"))U(G("(i0.i1.u7.p2031>=1)"))))))
Formula 3 simplified : !F(G"(i0.u2.p547>=1)" U G"(i0.i1.u7.p2031>=1)")
Computing Next relation with stutter on 202760 deadlock states
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, []((LTLAP17==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X(X([]((LTLAP18==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1634 ms.
FORMULA CloudReconfiguration-PT-306-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, <>(X((LTLAP19==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 2357 ms.
FORMULA CloudReconfiguration-PT-306-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, [](X([](X([]((LTLAP20==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 2234 ms.
FORMULA CloudReconfiguration-PT-306-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X(([](<>((LTLAP21==true))))U(((LTLAP22==true))U((LTLAP23==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 2409 ms.
FORMULA CloudReconfiguration-PT-306-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Retrying LTSmin with larger timeout 1800 s
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, <>(<>(([]((LTLAP8==true)))U([]((LTLAP9==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Detected timeout of ITS tools.
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903251645/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903251645/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 3 LTL properties
Checking formula 0 : !((F(F((G("(i0.u2.p547>=1)"))U(G("(i0.i1.u7.p2031>=1)"))))))
Formula 0 simplified : !F(G"(i0.u2.p547>=1)" U G"(i0.i1.u7.p2031>=1)")
built 2 ordering constraints for composite.
built 11 ordering constraints for composite.
built 16 ordering constraints for composite.
built 12 ordering constraints for composite.
Reverse transition relation is NOT exact ! Due to transitions t2868, i0.u2.t3, i0.u2.t4, i0.u2.t5, i0.u2.t2181, i0.u2.t2197, i0.u2.t2202, i0.u2.t2207, i0.u2.t2238, i0.u2.t2367, i0.u2.t2395, i0.u2.t2401, i0.u2.t2406, i0.u2.t2408, i0.u2.t2417, i0.u2.t2422, i0.u2.t2427, i0.u2.t2458, i0.u2.t2587, i0.u2.t2615, i0.u2.t2621, i0.u2.t2626, i0.u2.t2628, i0.u2.t2637, i0.u2.t2642, i0.u2.t2647, i0.u2.t2678, i0.u2.t2807, i0.u2.t2835, i0.u2.t2841, i0.u2.t2846, i0.u2.t2848, i0.u2.t2854, i0.u2.t2860, i0.u2.t2866, i0.i1.u7.t29, i0.i1.u7.t32, i0.i1.u7.t36, i0.i1.u7.t58, i0.i1.u7.t59, i0.i1.u7.t62, i0.i1.u7.t69, i0.i1.u7.t80, i0.i1.u7.t84, i0.i1.u7.t89, i0.i1.u7.t96, i0.i1.u7.t98, i0.i1.u7.t113, i0.i1.u7.t116, i0.i1.u7.t123, i0.i1.u7.t134, i0.i1.u7.t138, i0.i1.u7.t143, i0.i1.u7.t150, i0.i1.u7.t152, i0.i1.u7.t154, i0.i1.u7.t165, i0.i1.u7.t167, i0.i1.u7.t169, i0.i1.u7.t171, i0.i1.u7.t173, i0.i1.u7.t175, i0.i1.u7.t187, i0.i1.u7.t189, i0.i1.u7.t191, i0.i1.u7.t214, i0.i1.u7.t216, i0.i1.u7.t228, i0.i1.u7.t232, i0.i1.u7.t236, i0.i1.u7.t238, i0.i1.u7.t240, i0.i1.u7.t245, i0.i1.u7.t252, i0.i1.u7.t254, i0.i1.u7.t259, i0.i1.u7.t266, i0.i1.u7.t268, i0.i1.u7.t270, i0.i1.u7.t276, i0.i1.u7.t283, i0.i1.u7.t285, i0.i1.u7.t287, i0.i1.u7.t289, i0.i1.u7.t291, i0.i1.u7.t297, i0.i1.u7.t298, i0.i1.u7.t300, i0.i1.u7.t302, i0.i1.u7.t322, i0.i1.u7.t323, i0.i1.u7.t329, i0.i1.u7.t353, i0.i1.u7.t364, i0.i1.u7.t394, i0.i1.u7.t403, i0.i1.u7.t435, i0.i1.u7.t452, i0.i1.u7.t454, i0.i1.u7.t461, i0.i1.u7.t480, i0.i1.u7.t481, i0.i1.u7.t487, i0.i1.u7.t511, i0.i1.u7.t522, i0.i1.u7.t548, i0.i1.u7.t557, i0.i1.u7.t589, i0.i1.u7.t604, i0.i1.u7.t606, i0.i1.u7.t696, i0.i1.u7.t717, i0.i1.u7.t733, i0.i1.u7.t741, i0.i1.i0.u5.t1464, i0.i1.i0.u5.t1467, i0.i1.i0.u5.t1471, i0.i1.i0.u5.t1493, i0.i1.i0.u5.t1494, i0.i1.i0.u5.t1497, i0.i1.i0.u5.t1504, i0.i1.i0.u5.t1515, i0.i1.i0.u5.t1519, i0.i1.i0.u5.t1524, i0.i1.i0.u5.t1531, i0.i1.i0.u5.t1533, i0.i1.i0.u5.t1548, i0.i1.i0.u5.t1551, i0.i1.i0.u5.t1558, i0.i1.i0.u5.t1569, i0.i1.i0.u5.t1573, i0.i1.i0.u5.t1578, i0.i1.i0.u5.t1585, i0.i1.i0.u5.t1587, i0.i1.i0.u5.t1589, i0.i1.i0.u5.t1600, i0.i1.i0.u5.t1602, i0.i1.i0.u5.t1604, i0.i1.i0.u5.t1606, i0.i1.i0.u5.t1608, i0.i1.i0.u5.t1610, i0.i1.i0.u5.t1622, i0.i1.i0.u5.t1624, i0.i1.i0.u5.t1626, i0.i1.i0.u5.t1649, i0.i1.i0.u5.t1651, i0.i1.i0.u5.t1663, i0.i1.i0.u5.t1667, i0.i1.i0.u5.t1671, i0.i1.i0.u5.t1673, i0.i1.i0.u5.t1675, i0.i1.i0.u5.t1680, i0.i1.i0.u5.t1687, i0.i1.i0.u5.t1689, i0.i1.i0.u5.t1694, i0.i1.i0.u5.t1701, i0.i1.i0.u5.t1703, i0.i1.i0.u5.t1705, i0.i1.i0.u5.t1711, i0.i1.i0.u5.t1718, i0.i1.i0.u5.t1720, i0.i1.i0.u5.t1722, i0.i1.i0.u5.t1724, i0.i1.i0.u5.t1726, i0.i1.i0.u5.t1732, i0.i1.i0.u5.t1733, i0.i1.i0.u5.t1735, i0.i1.i0.u5.t1737, i0.i1.i0.u5.t1757, i0.i1.i0.u5.t1758, i0.i1.i0.u5.t1764, i0.i1.i0.u5.t1788, i0.i1.i0.u5.t1799, i0.i1.i0.u5.t1829, i0.i1.i0.u5.t1838, i0.i1.i0.u5.t1870, i0.i1.i0.u5.t1887, i0.i1.i0.u5.t1889, i0.i1.i0.u5.t1896, i0.i1.i0.u5.t1915, i0.i1.i0.u5.t1916, i0.i1.i0.u5.t1922, i0.i1.i0.u5.t1946, i0.i1.i0.u5.t1957, i0.i1.i0.u5.t1983, i0.i1.i0.u5.t1992, i0.i1.i0.u5.t2024, i0.i1.i0.u5.t2039, i0.i1.i0.u5.t2041, i0.i1.i0.u5.t2044, i0.i1.i0.u5.t2052, i0.i1.i0.u5.t2060, i0.i1.i0.u5.t2106, i0.i1.i0.u5.t2121, i0.i1.i0.u5.t2131, i0.i1.i0.u5.t2152, i0.i1.i0.u5.t2168, i0.i1.i0.u5.t2176, i0.i1.i0.u6.t747, i0.i1.i0.u6.t750, i0.i1.i0.u6.t754, i0.i1.i0.u6.t776, i0.i1.i0.u6.t777, i0.i1.i0.u6.t780, i0.i1.i0.u6.t787, i0.i1.i0.u6.t798, i0.i1.i0.u6.t802, i0.i1.i0.u6.t807, i0.i1.i0.u6.t814, i0.i1.i0.u6.t816, i0.i1.i0.u6.t831, i0.i1.i0.u6.t834, i0.i1.i0.u6.t841, i0.i1.i0.u6.t852, i0.i1.i0.u6.t856, i0.i1.i0.u6.t861, i0.i1.i0.u6.t868, i0.i1.i0.u6.t870, i0.i1.i0.u6.t872, i0.i1.i0.u6.t883, i0.i1.i0.u6.t885, i0.i1.i0.u6.t887, i0.i1.i0.u6.t889, i0.i1.i0.u6.t891, i0.i1.i0.u6.t893, i0.i1.i0.u6.t905, i0.i1.i0.u6.t907, i0.i1.i0.u6.t909, i0.i1.i0.u6.t932, i0.i1.i0.u6.t934, i0.i1.i0.u6.t946, i0.i1.i0.u6.t950, i0.i1.i0.u6.t954, i0.i1.i0.u6.t956, i0.i1.i0.u6.t958, i0.i1.i0.u6.t963, i0.i1.i0.u6.t970, i0.i1.i0.u6.t972, i0.i1.i0.u6.t977, i0.i1.i0.u6.t984, i0.i1.i0.u6.t986, i0.i1.i0.u6.t988, i0.i1.i0.u6.t994, i0.i1.i0.u6.t1001, i0.i1.i0.u6.t1003, i0.i1.i0.u6.t1005, i0.i1.i0.u6.t1007, i0.i1.i0.u6.t1009, i0.i1.i0.u6.t1015, i0.i1.i0.u6.t1016, i0.i1.i0.u6.t1018, i0.i1.i0.u6.t1020, i0.i1.i0.u6.t1040, i0.i1.i0.u6.t1041, i0.i1.i0.u6.t1047, i0.i1.i0.u6.t1071, i0.i1.i0.u6.t1082, i0.i1.i0.u6.t1112, i0.i1.i0.u6.t1121, i0.i1.i0.u6.t1153, i0.i1.i0.u6.t1170, i0.i1.i0.u6.t1172, i0.i1.i0.u6.t1179, i0.i1.i0.u6.t1198, i0.i1.i0.u6.t1199, i0.i1.i0.u6.t1205, i0.i1.i0.u6.t1229, i0.i1.i0.u6.t1240, i0.i1.i0.u6.t1266, i0.i1.i0.u6.t1275, i0.i1.i0.u6.t1307, i0.i1.i0.u6.t1322, i0.i1.i0.u6.t1324, i0.i1.i0.u6.t1414, i0.i1.i0.u6.t1435, i0.i1.i0.u6.t1451, i0.i1.i0.u6.t1459, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :162/2533/277/2972
Computing Next relation with stutter on 202760 deadlock states
LTSmin run took 1046911 ms.
FORMULA CloudReconfiguration-PT-306-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, false, --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1046804 ms.
FORMULA CloudReconfiguration-PT-306-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, []((LTLAP17==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ LTLFireability = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -greatspnpath /home/mcc/BenchKit//greatspn/ -order META -manyOrder -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -greatspnpath /home/mcc/BenchKit//greatspn/ -order META -manyOrder -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Mar 27, 2019 9:06:49 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -greatspnpath, /home/mcc/BenchKit//greatspn/, -order, META, -manyOrder, -smt]
Mar 27, 2019 9:06:49 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Mar 27, 2019 9:06:49 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 407 ms
Mar 27, 2019 9:06:50 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 2584 places.
Mar 27, 2019 9:06:50 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 3094 transitions.
Mar 27, 2019 9:06:50 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
Mar 27, 2019 9:06:50 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 95 ms
Mar 27, 2019 9:06:51 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 789 ms
Mar 27, 2019 9:06:51 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 358 ms
Mar 27, 2019 9:06:52 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 3094 transitions.
Mar 27, 2019 9:06:52 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 3094 transitions.
Mar 27, 2019 9:06:52 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Too many transitions (3094) to apply POR reductions. Disabling POR matrices.
Mar 27, 2019 9:06:53 AM fr.lip6.move.gal.application.StructuralToGreatSPN handlePage
INFO: Transformed 2584 places.
Mar 27, 2019 9:06:53 AM fr.lip6.move.gal.application.StructuralToGreatSPN handlePage
INFO: Transformed 3094 transitions.
Mar 27, 2019 9:06:53 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 1325ms conformant to PINS in folder :/home/mcc/execution
Mar 27, 2019 9:06:54 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 26 ms
Mar 27, 2019 9:06:54 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 1 ms
Mar 27, 2019 9:26:55 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Mar 27, 2019 9:26:55 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 776 ms
Mar 27, 2019 9:26:56 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 746 ms
Mar 27, 2019 9:26:56 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Mar 27, 2019 9:26:56 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
Mar 27, 2019 9:26:57 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 2 events :t2871,t2871,
Mar 27, 2019 9:26:58 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 120 events :t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,
Mar 27, 2019 9:26:58 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 122 redundant transitions.
Mar 27, 2019 9:26:58 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 1079 ms
Mar 27, 2019 9:26:58 AM fr.lip6.move.gal.instantiate.CompositeBuilder fuseSimilarLabels
INFO: Found fuseable labels in CloudReconfiguration_PT_306_flat_flat_flat_mod_flat_sub0_sub1 :[i1.u6.t2998, i1.u6.t2976, i1.u6.t2997, i1.u6.t3008, i1.u6.t2975, i1.u6.t2996, i1.u6.t3007, i1.u6.t2974, i1.u6.t2995, i1.u6.t3006, i1.u6.t2973, i1.u6.t2979, i1.u6.t2978, i1.u6.t2999, i1.u6.t2977, i1.u6.t2990, i1.u6.t3001, i1.u6.t3000, i1.u6.t2994, i1.u6.t3005, i1.u6.t2972, i1.u6.t2993, i1.u6.t3004, i1.u6.t2971, i1.u6.t2992, i1.u6.t3003, i1.u6.t2970, i1.u6.t2991, i1.u6.t3002, i1.u6.t2987, i1.u6.t2986, i1.u6.t2985, i1.u6.t2984, i1.u6.t2969, i1.u6.t2968, i1.u6.t2989, i1.u6.t2988, i1.u6.t2983, i1.u6.t2982, i1.u6.t2981, i1.u6.t2980]
Mar 27, 2019 9:26:58 AM fr.lip6.move.gal.instantiate.CompositeBuilder fuseSimilarLabels
INFO: Found fuseable labels in CloudReconfiguration_PT_306_flat_flat_flat_mod_flat_sub0_sub1 :[i1.u5.t3019, i1.u5.t3018, i1.u5.t3050, i1.u5.t3031, i1.u5.t3030, i1.u5.t3015, i1.u5.t3037, i1.u5.t3014, i1.u5.t3036, i1.u5.t3017, i1.u5.t3039, i1.u5.t3016, i1.u5.t3038, i1.u5.t3011, i1.u5.t3033, i1.u5.t3010, i1.u5.t3032, i1.u5.t3013, i1.u5.t3035, i1.u5.t3012, i1.u5.t3034, i1.u5.t3029, i1.u5.t3040, i1.u5.t3020, i1.u5.t3042, i1.u5.t3041, i1.u5.t3026, i1.u5.t3048, i1.u5.t3025, i1.u5.t3047, i1.u5.t3028, i1.u5.t3027, i1.u5.t3049, i1.u5.t3022, i1.u5.t3044, i1.u5.t3021, i1.u5.t3043, i1.u5.t3024, i1.u5.t3046, i1.u5.t3023, i1.u5.t3045]
Mar 27, 2019 9:26:58 AM fr.lip6.move.gal.instantiate.CompositeBuilder fuseSimilarLabels
INFO: Found fuseable labels in CloudReconfiguration_PT_306_flat_flat_flat_mod_flat_sub0_sub1 :[i1.u7.t3080, i1.u7.t3060, i1.u7.t3082, i1.u7.t3081, i1.u7.t3062, i1.u7.t3084, i1.u7.t3061, i1.u7.t3083, i1.u7.t3064, i1.u7.t3086, i1.u7.t3063, i1.u7.t3085, i1.u7.t3066, i1.u7.t3088, i1.u7.t3065, i1.u7.t3087, i1.u7.t3068, i1.u7.t3067, i1.u7.t3089, i1.u7.t3069, i1.u7.t3091, i1.u7.t3090, i1.u7.t3071, i1.u7.t3093, i1.u7.t3070, i1.u7.t3092, i1.u7.t3073, i1.u7.t3072, i1.u7.t3053, i1.u7.t3075, i1.u7.t3074, i1.u7.t3055, i1.u7.t3077, i1.u7.t3054, i1.u7.t3076, i1.u7.t3057, i1.u7.t3079, i1.u7.t3056, i1.u7.t3078, i1.u7.t3059, i1.u7.t3058]
Mar 27, 2019 9:26:58 AM fr.lip6.move.gal.instantiate.CompositeBuilder fuseSimilarLabels
INFO: Found fuseable labels in CloudReconfiguration_PT_306_flat_flat_flat_mod_flat_sub0 :[i0.u5.t2872, i0.u7.t2873, i0.u6.t2871]
Mar 27, 2019 9:26:58 AM fr.lip6.move.gal.instantiate.CompositeBuilder fuseSimilarLabels
INFO: Found fuseable labels in CloudReconfiguration_PT_306_flat_flat_flat_mod_flat_sub0_sub1_sub0 :[i0.u5.t3045, i0.u5.t3023, i0.u5.t3044, i0.u5.t3022, i0.u5.t3043, i0.u5.t3021, i0.u5.t3042, i0.u5.t3020, i0.u5.t3049, i0.u5.t3027, i0.u5.t3048, i0.u5.t3026, i0.u5.t3047, i0.u5.t3025, i0.u5.t3046, i0.u5.t3024, i0.u5.t3041, i0.u5.t3040, i0.u5.t3029, i0.u5.t3028, i0.u5.t3034, i0.u5.t3012, i0.u5.t3033, i0.u5.t3011, i0.u5.t3032, i0.u5.t3010, i0.u5.t3031, i0.u5.t3038, i0.u5.t3016, i0.u5.t3037, i0.u5.t3015, i0.u5.t3036, i0.u5.t3014, i0.u5.t3035, i0.u5.t3013, i0.u5.t3030, i0.u5.t3050, i0.u5.t3019, i0.u5.t3018, i0.u5.t3039, i0.u5.t3017]
Mar 27, 2019 9:26:58 AM fr.lip6.move.gal.instantiate.CompositeBuilder fuseSimilarLabels
INFO: Found fuseable labels in CloudReconfiguration_PT_306_flat_flat_flat_mod_flat_sub0_sub1_sub0 :[i0.u6.t2984, i0.u6.t2983, i0.u6.t2986, i0.u6.t2985, i0.u6.t2988, i0.u6.t2987, i0.u6.t2968, i0.u6.t2989, i0.u6.t2969, i0.u6.t2980, i0.u6.t2982, i0.u6.t2981, i0.u6.t2995, i0.u6.t2973, i0.u6.t3006, i0.u6.t2994, i0.u6.t2972, i0.u6.t3005, i0.u6.t2997, i0.u6.t2975, i0.u6.t3008, i0.u6.t2996, i0.u6.t2974, i0.u6.t3007, i0.u6.t2999, i0.u6.t2977, i0.u6.t2998, i0.u6.t2976, i0.u6.t2979, i0.u6.t2978, i0.u6.t3000, i0.u6.t2991, i0.u6.t3002, i0.u6.t2990, i0.u6.t3001, i0.u6.t2993, i0.u6.t2971, i0.u6.t3004, i0.u6.t2992, i0.u6.t2970, i0.u6.t3003]
Mar 27, 2019 9:26:58 AM fr.lip6.move.gal.instantiate.CompositeBuilder fuseSimilarLabels
INFO: Found fuseable labels in Tu7_flat :[u7.t3091, u7.t3090, u7.t3093, u7.t3071, u7.t3092, u7.t3070, u7.t3069, u7.t3084, u7.t3062, u7.t3083, u7.t3061, u7.t3086, u7.t3064, u7.t3085, u7.t3063, u7.t3088, u7.t3066, u7.t3087, u7.t3065, u7.t3068, u7.t3089, u7.t3067, u7.t3080, u7.t3082, u7.t3060, u7.t3081, u7.t3059, u7.t3058, u7.t3073, u7.t3072, u7.t3075, u7.t3053, u7.t3074, u7.t3077, u7.t3055, u7.t3076, u7.t3054, u7.t3079, u7.t3057, u7.t3078, u7.t3056]
Mar 27, 2019 9:26:58 AM fr.lip6.move.gal.instantiate.CompositeBuilder fuseSimilarLabels
INFO: Found fuseable labels in CloudReconfiguration_PT_306_flat_flat_flat_mod_flat_sub0_sub1 :[i1.u7.t2873, i1.u6.t2871, i1.u5.t2872]
Mar 27, 2019 9:26:58 AM fr.lip6.move.gal.instantiate.CompositeBuilder fuseSimilarLabels
INFO: Found fuseable labels in Tu6_flat :[u6.t2969, u6.t2968, u6.t2981, u6.t2980, u6.t2985, u6.t2984, u6.t2983, u6.t2982, u6.t2989, u6.t2988, u6.t2987, u6.t2986, u6.t2979, u6.t3003, u6.t2992, u6.t2970, u6.t3002, u6.t2991, u6.t3001, u6.t2990, u6.t3000, u6.t3007, u6.t2996, u6.t2974, u6.t3006, u6.t2995, u6.t2973, u6.t3005, u6.t2994, u6.t2972, u6.t3004, u6.t2993, u6.t2971, u6.t2978, u6.t2999, u6.t2977, u6.t2998, u6.t2976, u6.t3008, u6.t2997, u6.t2975]
Mar 27, 2019 9:26:58 AM fr.lip6.move.gal.instantiate.CompositeBuilder fuseSimilarLabels
INFO: Found fuseable labels in Tu5_flat :[u5.t3028, u5.t3049, u5.t3027, u5.t3029, u5.t3046, u5.t3024, u5.t3045, u5.t3023, u5.t3048, u5.t3026, u5.t3047, u5.t3025, u5.t3042, u5.t3020, u5.t3041, u5.t3044, u5.t3022, u5.t3043, u5.t3021, u5.t3050, u5.t3017, u5.t3039, u5.t3016, u5.t3038, u5.t3019, u5.t3018, u5.t3013, u5.t3035, u5.t3012, u5.t3034, u5.t3015, u5.t3037, u5.t3014, u5.t3036, u5.t3031, u5.t3030, u5.t3011, u5.t3033, u5.t3010, u5.t3032, u5.t3040]
Mar 27, 2019 9:26:58 AM fr.lip6.move.gal.instantiate.CompositeBuilder fuseSimilarLabels
INFO: Found fuseable labels in CloudReconfiguration_PT_306_flat_flat_flat_mod_flat_sub0_sub1_sub0 :[i0.u5.t2872, i0.u6.t2871]
Mar 27, 2019 9:26:58 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 48 ms
Mar 27, 2019 9:26:58 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 1 ms
Mar 27, 2019 9:46:58 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Mar 27, 2019 9:46:59 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 535 ms
Mar 27, 2019 9:46:59 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 518 ms
Mar 27, 2019 9:46:59 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Mar 27, 2019 9:47:00 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
Mar 27, 2019 9:47:01 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 2 events :t2871,t2871,
Mar 27, 2019 9:47:01 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 120 events :t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3053,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t3010,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,t2968,
Mar 27, 2019 9:47:01 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 122 redundant transitions.
Mar 27, 2019 9:47:01 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 857 ms
Mar 27, 2019 9:47:01 AM fr.lip6.move.gal.instantiate.CompositeBuilder fuseSimilarLabels
INFO: Found fuseable labels in CloudReconfiguration_PT_306_flat_flat_flat_mod_flat_sub0_sub1 :[i1.u6.t2998, i1.u6.t2976, i1.u6.t2997, i1.u6.t3008, i1.u6.t2975, i1.u6.t2996, i1.u6.t3007, i1.u6.t2974, i1.u6.t2995, i1.u6.t3006, i1.u6.t2973, i1.u6.t2979, i1.u6.t2978, i1.u6.t2999, i1.u6.t2977, i1.u6.t2990, i1.u6.t3001, i1.u6.t3000, i1.u6.t2994, i1.u6.t3005, i1.u6.t2972, i1.u6.t2993, i1.u6.t3004, i1.u6.t2971, i1.u6.t2992, i1.u6.t3003, i1.u6.t2970, i1.u6.t2991, i1.u6.t3002, i1.u6.t2987, i1.u6.t2986, i1.u6.t2985, i1.u6.t2984, i1.u6.t2969, i1.u6.t2968, i1.u6.t2989, i1.u6.t2988, i1.u6.t2983, i1.u6.t2982, i1.u6.t2981, i1.u6.t2980]
Mar 27, 2019 9:47:01 AM fr.lip6.move.gal.instantiate.CompositeBuilder fuseSimilarLabels
INFO: Found fuseable labels in CloudReconfiguration_PT_306_flat_flat_flat_mod_flat_sub0_sub1 :[i1.u5.t3019, i1.u5.t3018, i1.u5.t3050, i1.u5.t3031, i1.u5.t3030, i1.u5.t3015, i1.u5.t3037, i1.u5.t3014, i1.u5.t3036, i1.u5.t3017, i1.u5.t3039, i1.u5.t3016, i1.u5.t3038, i1.u5.t3011, i1.u5.t3033, i1.u5.t3010, i1.u5.t3032, i1.u5.t3013, i1.u5.t3035, i1.u5.t3012, i1.u5.t3034, i1.u5.t3029, i1.u5.t3040, i1.u5.t3020, i1.u5.t3042, i1.u5.t3041, i1.u5.t3026, i1.u5.t3048, i1.u5.t3025, i1.u5.t3047, i1.u5.t3028, i1.u5.t3027, i1.u5.t3049, i1.u5.t3022, i1.u5.t3044, i1.u5.t3021, i1.u5.t3043, i1.u5.t3024, i1.u5.t3046, i1.u5.t3023, i1.u5.t3045]
Mar 27, 2019 9:47:01 AM fr.lip6.move.gal.instantiate.CompositeBuilder fuseSimilarLabels
INFO: Found fuseable labels in CloudReconfiguration_PT_306_flat_flat_flat_mod_flat_sub0_sub1 :[i1.u7.t3080, i1.u7.t3060, i1.u7.t3082, i1.u7.t3081, i1.u7.t3062, i1.u7.t3084, i1.u7.t3061, i1.u7.t3083, i1.u7.t3064, i1.u7.t3086, i1.u7.t3063, i1.u7.t3085, i1.u7.t3066, i1.u7.t3088, i1.u7.t3065, i1.u7.t3087, i1.u7.t3068, i1.u7.t3067, i1.u7.t3089, i1.u7.t3069, i1.u7.t3091, i1.u7.t3090, i1.u7.t3071, i1.u7.t3093, i1.u7.t3070, i1.u7.t3092, i1.u7.t3073, i1.u7.t3072, i1.u7.t3053, i1.u7.t3075, i1.u7.t3074, i1.u7.t3055, i1.u7.t3077, i1.u7.t3054, i1.u7.t3076, i1.u7.t3057, i1.u7.t3079, i1.u7.t3056, i1.u7.t3078, i1.u7.t3059, i1.u7.t3058]
Mar 27, 2019 9:47:01 AM fr.lip6.move.gal.instantiate.CompositeBuilder fuseSimilarLabels
INFO: Found fuseable labels in CloudReconfiguration_PT_306_flat_flat_flat_mod_flat_sub0 :[i0.u5.t2872, i0.u7.t2873, i0.u6.t2871]
Mar 27, 2019 9:47:01 AM fr.lip6.move.gal.instantiate.CompositeBuilder fuseSimilarLabels
INFO: Found fuseable labels in CloudReconfiguration_PT_306_flat_flat_flat_mod_flat_sub0_sub1_sub0 :[i0.u5.t3045, i0.u5.t3023, i0.u5.t3044, i0.u5.t3022, i0.u5.t3043, i0.u5.t3021, i0.u5.t3042, i0.u5.t3020, i0.u5.t3049, i0.u5.t3027, i0.u5.t3048, i0.u5.t3026, i0.u5.t3047, i0.u5.t3025, i0.u5.t3046, i0.u5.t3024, i0.u5.t3041, i0.u5.t3040, i0.u5.t3029, i0.u5.t3028, i0.u5.t3034, i0.u5.t3012, i0.u5.t3033, i0.u5.t3011, i0.u5.t3032, i0.u5.t3010, i0.u5.t3031, i0.u5.t3038, i0.u5.t3016, i0.u5.t3037, i0.u5.t3015, i0.u5.t3036, i0.u5.t3014, i0.u5.t3035, i0.u5.t3013, i0.u5.t3030, i0.u5.t3050, i0.u5.t3019, i0.u5.t3018, i0.u5.t3039, i0.u5.t3017]
Mar 27, 2019 9:47:01 AM fr.lip6.move.gal.instantiate.CompositeBuilder fuseSimilarLabels
INFO: Found fuseable labels in CloudReconfiguration_PT_306_flat_flat_flat_mod_flat_sub0_sub1_sub0 :[i0.u6.t2984, i0.u6.t2983, i0.u6.t2986, i0.u6.t2985, i0.u6.t2988, i0.u6.t2987, i0.u6.t2968, i0.u6.t2989, i0.u6.t2969, i0.u6.t2980, i0.u6.t2982, i0.u6.t2981, i0.u6.t2995, i0.u6.t2973, i0.u6.t3006, i0.u6.t2994, i0.u6.t2972, i0.u6.t3005, i0.u6.t2997, i0.u6.t2975, i0.u6.t3008, i0.u6.t2996, i0.u6.t2974, i0.u6.t3007, i0.u6.t2999, i0.u6.t2977, i0.u6.t2998, i0.u6.t2976, i0.u6.t2979, i0.u6.t2978, i0.u6.t3000, i0.u6.t2991, i0.u6.t3002, i0.u6.t2990, i0.u6.t3001, i0.u6.t2993, i0.u6.t2971, i0.u6.t3004, i0.u6.t2992, i0.u6.t2970, i0.u6.t3003]
Mar 27, 2019 9:47:01 AM fr.lip6.move.gal.instantiate.CompositeBuilder fuseSimilarLabels
INFO: Found fuseable labels in Tu7_flat :[u7.t3091, u7.t3090, u7.t3093, u7.t3071, u7.t3092, u7.t3070, u7.t3069, u7.t3084, u7.t3062, u7.t3083, u7.t3061, u7.t3086, u7.t3064, u7.t3085, u7.t3063, u7.t3088, u7.t3066, u7.t3087, u7.t3065, u7.t3068, u7.t3089, u7.t3067, u7.t3080, u7.t3082, u7.t3060, u7.t3081, u7.t3059, u7.t3058, u7.t3073, u7.t3072, u7.t3075, u7.t3053, u7.t3074, u7.t3077, u7.t3055, u7.t3076, u7.t3054, u7.t3079, u7.t3057, u7.t3078, u7.t3056]
Mar 27, 2019 9:47:01 AM fr.lip6.move.gal.instantiate.CompositeBuilder fuseSimilarLabels
INFO: Found fuseable labels in CloudReconfiguration_PT_306_flat_flat_flat_mod_flat_sub0_sub1 :[i1.u7.t2873, i1.u6.t2871, i1.u5.t2872]
Mar 27, 2019 9:47:01 AM fr.lip6.move.gal.instantiate.CompositeBuilder fuseSimilarLabels
INFO: Found fuseable labels in Tu6_flat :[u6.t2969, u6.t2968, u6.t2981, u6.t2980, u6.t2985, u6.t2984, u6.t2983, u6.t2982, u6.t2989, u6.t2988, u6.t2987, u6.t2986, u6.t2979, u6.t3003, u6.t2992, u6.t2970, u6.t3002, u6.t2991, u6.t3001, u6.t2990, u6.t3000, u6.t3007, u6.t2996, u6.t2974, u6.t3006, u6.t2995, u6.t2973, u6.t3005, u6.t2994, u6.t2972, u6.t3004, u6.t2993, u6.t2971, u6.t2978, u6.t2999, u6.t2977, u6.t2998, u6.t2976, u6.t3008, u6.t2997, u6.t2975]
Mar 27, 2019 9:47:01 AM fr.lip6.move.gal.instantiate.CompositeBuilder fuseSimilarLabels
INFO: Found fuseable labels in Tu5_flat :[u5.t3028, u5.t3049, u5.t3027, u5.t3029, u5.t3046, u5.t3024, u5.t3045, u5.t3023, u5.t3048, u5.t3026, u5.t3047, u5.t3025, u5.t3042, u5.t3020, u5.t3041, u5.t3044, u5.t3022, u5.t3043, u5.t3021, u5.t3050, u5.t3017, u5.t3039, u5.t3016, u5.t3038, u5.t3019, u5.t3018, u5.t3013, u5.t3035, u5.t3012, u5.t3034, u5.t3015, u5.t3037, u5.t3014, u5.t3036, u5.t3031, u5.t3030, u5.t3011, u5.t3033, u5.t3010, u5.t3032, u5.t3040]
Mar 27, 2019 9:47:01 AM fr.lip6.move.gal.instantiate.CompositeBuilder fuseSimilarLabels
INFO: Found fuseable labels in CloudReconfiguration_PT_306_flat_flat_flat_mod_flat_sub0_sub1_sub0 :[i0.u5.t2872, i0.u6.t2871]
Mar 27, 2019 9:47:01 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 10 ms
Mar 27, 2019 9:47:01 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 1 ms

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CloudReconfiguration-PT-306"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstoolsm"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3957"
echo " Executing tool itstoolsm"
echo " Input is CloudReconfiguration-PT-306, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r191-smll-155229651700160"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/CloudReconfiguration-PT-306.tgz
mv CloudReconfiguration-PT-306 execution
cd execution
if [ "LTLFireability" = "GlobalProperties" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
if [ "LTLFireability" = "UpperBounds" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;