Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/local/x2003239/mcc2019-input.r184-csrt-155344537600075.qcow2', fmt=qcow2 size=4294967296 backing_file=/local/x2003239/mcc2019-input.qcow2 encryption=off cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................
=====================================================================
Generated by BenchKit 2-3954
Executing tool itstools
Input is FamilyReunion-COL-L00010M0001C001P001G001, examination is GlobalProperties
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r184-csrt-155344537600075
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 288K
-rw-r--r-- 1 mcc users 3.4K Mar 24 07:03 CTLCardinality.txt
-rw-r--r-- 1 mcc users 16K Mar 24 07:03 CTLCardinality.xml
-rw-r--r-- 1 mcc users 3.4K Mar 24 06:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 16K Mar 24 06:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 128 Apr 5 12:35 GlobalProperties.txt
-rw-r--r-- 1 mcc users 366 Apr 5 12:35 GlobalProperties.xml
-rw-r--r-- 1 mcc users 2.8K Mar 24 06:50 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K Mar 24 06:50 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Mar 24 06:48 LTLFireability.txt
-rw-r--r-- 1 mcc users 9.4K Mar 24 06:48 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Mar 24 00:18 NewModel
-rw-r--r-- 1 mcc users 3.8K Mar 24 06:38 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 19K Mar 24 06:38 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 4.0K Mar 24 06:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 24 06:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Mar 24 06:46 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Mar 24 06:46 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 24 00:18 equiv_pt
-rw-r--r-- 1 mcc users 24 Mar 24 00:18 instance
-rw-r--r-- 1 mcc users 5 Mar 24 00:18 iscolored
-rw-r--r-- 1 mcc users 134K Mar 24 00:18 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-GlobalProperties-0

=== Now, execution of the tool begins

BK_START 1554496882532

20:41:30.741 [main] ERROR PNML validation - The rng grammar file can't be accessed : www.pnml.org
20:41:30.743 [main] ERROR import - Grammar file errors have been raised, the validation can't be done, process will continue without Grammar validation
Working with output stream class java.io.PrintStream
Flatten gal took : 1936 ms
Constant places removed 67 places and 11 transitions.
Implicit places reduction removed 132 places :[l7_21, l7_20, l7_19, l7_18, l7_17, l7_16, l7_15, l7_14, l7_13, l7_12, l7_11, l7_10, l7_9, l7_8, l7_7, l7_6, l7_5, l7_4, l7_3, l7_2, l7_1, l7_0, m6_21, m6_20, m6_19, m6_18, m6_17, m6_16, m6_15, m6_14, m6_13, m6_12, m6_11, m6_10, m6_9, m6_8, m6_7, m6_6, m6_5, m6_4, m6_3, m6_2, m6_1, m6_0, l5_21, l5_20, l5_19, l5_18, l5_17, l5_16, l5_15, l5_14, l5_13, l5_12, l5_11, l5_10, l5_9, l5_8, l5_7, l5_6, l5_5, l5_4, l5_3, l5_2, l5_1, l5_0, m4_21, m4_20, m4_19, m4_18, m4_17, m4_16, m4_15, m4_14, m4_13, m4_12, m4_11, m4_10, m4_9, m4_8, m4_7, m4_6, m4_5, m4_4, m4_3, m4_2, m4_1, m4_0, l3_21, l3_20, l3_19, l3_18, l3_17, l3_16, l3_15, l3_14, l3_13, l3_12, l3_11, l3_10, l3_9, l3_8, l3_7, l3_6, l3_5, l3_4, l3_3, l3_2, l3_1, l3_0, m2_21, m2_20, m2_19, m2_18, m2_17, m2_16, m2_15, m2_14, m2_13, m2_12, m2_11, m2_10, m2_9, m2_8, m2_7, m2_6, m2_5, m2_4, m2_3, m2_2, m2_1, m2_0]
Performed 671 Post agglomeration using F-continuation condition.
Iterating post reduction 0 with 870 rules applied. Total rules applied 870 place count 1277 transition count 552
Constant places removed 726 places and 0 transitions.
Performed 33 Post agglomeration using F-continuation condition.
Iterating post reduction 1 with 759 rules applied. Total rules applied 1629 place count 551 transition count 519
Constant places removed 33 places and 0 transitions.
Iterating post reduction 2 with 33 rules applied. Total rules applied 1662 place count 518 transition count 519
Symmetric choice reduction at 3 with 100 rule applications. Total rules 1762 place count 518 transition count 519
Constant places removed 100 places and 111 transitions.
Reduce isomorphic transitions removed 22 transitions.
Performed 66 Post agglomeration using F-continuation condition.
Iterating post reduction 3 with 188 rules applied. Total rules applied 1950 place count 418 transition count 320
Constant places removed 77 places and 0 transitions.
Implicit places reduction removed 11 places :[l16_10, l16_9, l16_8, l16_7, l16_6, l16_5, l16_4, l16_3, l16_2, l16_1, l16_0]
Performed 22 Post agglomeration using F-continuation condition.
Iterating post reduction 4 with 110 rules applied. Total rules applied 2060 place count 330 transition count 298
Constant places removed 22 places and 0 transitions.
Iterating post reduction 5 with 22 rules applied. Total rules applied 2082 place count 308 transition count 298
Performed 22 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 6 with 22 Pre rules applied. Total rules applied 2082 place count 308 transition count 276
Constant places removed 22 places and 0 transitions.
Iterating post reduction 6 with 22 rules applied. Total rules applied 2104 place count 286 transition count 276
Symmetric choice reduction at 7 with 4 rule applications. Total rules 2108 place count 286 transition count 276
Constant places removed 4 places and 44 transitions.
Reduce isomorphic transitions removed 22 transitions.
Implicit places reduction removed 55 places :[l20_10, l20_9, l20_8, l20_7, l20_6, l20_5, l20_4, l20_3, l20_2, l20_1, l20_0, l18_10, l18_9, l18_8, l18_7, l18_6, l18_5, l18_4, l18_3, l18_2, l18_1, l18_0, l10_10, l10_9, l10_8, l10_7, l10_6, l10_5, l10_4, l10_3, l10_2, l10_1, l10_0, l36_10, l36_9, l36_8, l36_7, l36_6, l36_5, l36_4, l36_3, l36_2, l36_1, l36_0, l31_10, l31_9, l31_8, l31_7, l31_6, l31_5, l31_4, l31_3, l31_2, l31_1, l31_0]
Performed 77 Post agglomeration using F-continuation condition.
Iterating post reduction 7 with 158 rules applied. Total rules applied 2266 place count 227 transition count 133
Constant places removed 77 places and 0 transitions.
Iterating post reduction 8 with 77 rules applied. Total rules applied 2343 place count 150 transition count 133
Performed 22 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 9 with 22 Pre rules applied. Total rules applied 2343 place count 150 transition count 111
Constant places removed 22 places and 0 transitions.
Iterating post reduction 9 with 22 rules applied. Total rules applied 2365 place count 128 transition count 111
Symmetric choice reduction at 10 with 12 rule applications. Total rules 2377 place count 128 transition count 111
Constant places removed 12 places and 22 transitions.
Reduce isomorphic transitions removed 11 transitions.
Iterating post reduction 10 with 23 rules applied. Total rules applied 2400 place count 116 transition count 78
Constant places removed 11 places and 11 transitions.
Iterating post reduction 11 with 11 rules applied. Total rules applied 2411 place count 105 transition count 67
Constant places removed 11 places and 0 transitions.
Iterating post reduction 12 with 11 rules applied. Total rules applied 2422 place count 94 transition count 67
Constant places removed 11 places and 11 transitions.
Iterating post reduction 13 with 11 rules applied. Total rules applied 2433 place count 83 transition count 56
Performed 1 Post agglomeration using F-continuation condition.
Constant places removed 1 places and 0 transitions.
Iterating post reduction 14 with 1 rules applied. Total rules applied 2434 place count 82 transition count 55
Applied a total of 2434 rules in 942 ms. Remains 82 /1476 variables (removed 1394) and now considering 55/1234 (removed 1179) transitions.
// Phase 1: matrix 55 rows 82 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 55 rows 82 cols
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903171603/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/GlobalProperties.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903171603/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/GlobalProperties.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
built 55 ordering constraints for composite.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,8.49347e+07,2.15457,33048,18090,34,82499,182,178,36557,28,215,0


Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,55,3.52062,66432,193,11,151495,296,728,94301,148,1823,529595

System contains 55 deadlocks (shown below if less than --print-limit option) !
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-GlobalProperties-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
[ 55 states ] showing 10 first states
[ LxG20={[ ]
} LxG18={[ ]
} LxC20={[ ]
} LxC18={[ ]
} LxG16={[ ]
} LxG14={[ ]
} LxC16={[ c5_16=1 ]
} LxC14={[ c5_14=1 ]
} LegalResident10={[ ]
} LxG12={[ ]
} LegalResident9={[ ]
} LxC12={[ c5_12=1 ]
} LxG10={[ ]
} LegalResident8={[ lc3_8=1 l34_8=1 ]
} LegalResident7={[ lc3_7=1 l34_7=1 ]
} LxC10={[ c5_10=1 ]
} GovernmentCommission0={[ ]
} LegalResident6={[ lc3_6=1 l34_6=1 ]
} LxG8={[ ]
} LegalResident5={[ lc3_5=1 l34_5=1 ]
} LxC8={[ c5_8=1 ]
} LxG6={[ ]
} LegalResident4={[ lc3_4=1 l34_4=1 ]
} LxC6={[ c5_6=1 ]
} CINFORMI0={[ ]
} LegalResident3={[ lc3_3=1 l34_3=1 ]
} LxG4={[ ]
} PublicAdminOffice0={[ ]
} MICSystem0={[ ]
} LxC4={[ c5_4=1 ]
} LegalResident2={[ lc3_2=1 l34_2=1 ]
} LxG2={[ ]
} LegalResident1={[ lc3_1=1 l34_1=1 ]
} LxC2={[ c5_2=1 ]
} LxG0={[ ]
} LegalResident0={[ lc3_0=1 l34_0=1 ]
} LxC0={[ c5_0=1 ]
} ]
[ LxG20={[ ]
} LxG18={[ ]
} LxC20={[ ]
} LxC18={[ c5_18=1 ]
} LxG16={[ ]
} LxG14={[ ]
} LxC16={[ ]
} LxC14={[ c5_14=1 ]
} LegalResident10={[ ]
} LxG12={[ ]
} LegalResident9={[ lc3_9=1 l34_9=1 ]
} LxC12={[ c5_12=1 ]
} LxG10={[ ]
} LegalResident8={[ ]
} LegalResident7={[ lc3_7=1 l34_7=1 ]
} LxC10={[ c5_10=1 ]
} GovernmentCommission0={[ ]
} LegalResident6={[ lc3_6=1 l34_6=1 ]
} LxG8={[ ]
} LegalResident5={[ lc3_5=1 l34_5=1 ]
} LxC8={[ c5_8=1 ]
} LxG6={[ ]
} LegalResident4={[ lc3_4=1 l34_4=1 ]
} LxC6={[ c5_6=1 ]
} CINFORMI0={[ ]
} LegalResident3={[ lc3_3=1 l34_3=1 ]
} LxG4={[ ]
} PublicAdminOffice0={[ ]
} MICSystem0={[ ]
} LxC4={[ c5_4=1 ]
} LegalResident2={[ lc3_2=1 l34_2=1 ]
} LxG2={[ ]
} LegalResident1={[ lc3_1=1 l34_1=1 ]
} LxC2={[ c5_2=1 ]
} LxG0={[ ]
} LegalResident0={[ lc3_0=1 l34_0=1 ]
} LxC0={[ c5_0=1 ]
} ]
[ LxG20={[ ]
} LxG18={[ ]
} LxC20={[ ]
} LxC18={[ c5_18=1 ]
} LxG16={[ ]
} LxG14={[ ]
} LxC16={[ c5_16=1 ]
} LxC14={[ ]
} LegalResident10={[ ]
} LxG12={[ ]
} LegalResident9={[ lc3_9=1 l34_9=1 ]
} LxC12={[ c5_12=1 ]
} LxG10={[ ]
} LegalResident8={[ lc3_8=1 l34_8=1 ]
} LegalResident7={[ ]
} LxC10={[ c5_10=1 ]
} GovernmentCommission0={[ ]
} LegalResident6={[ lc3_6=1 l34_6=1 ]
} LxG8={[ ]
} LegalResident5={[ lc3_5=1 l34_5=1 ]
} LxC8={[ c5_8=1 ]
} LxG6={[ ]
} LegalResident4={[ lc3_4=1 l34_4=1 ]
} LxC6={[ c5_6=1 ]
} CINFORMI0={[ ]
} LegalResident3={[ lc3_3=1 l34_3=1 ]
} LxG4={[ ]
} PublicAdminOffice0={[ ]
} MICSystem0={[ ]
} LxC4={[ c5_4=1 ]
} LegalResident2={[ lc3_2=1 l34_2=1 ]
} LxG2={[ ]
} LegalResident1={[ lc3_1=1 l34_1=1 ]
} LxC2={[ c5_2=1 ]
} LxG0={[ ]
} LegalResident0={[ lc3_0=1 l34_0=1 ]
} LxC0={[ c5_0=1 ]
} ]
[ LxG20={[ ]
} LxG18={[ ]
} LxC20={[ ]
} LxC18={[ c5_18=1 ]
} LxG16={[ ]
} LxG14={[ ]
} LxC16={[ c5_16=1 ]
} LxC14={[ c5_14=1 ]
} LegalResident10={[ ]
} LxG12={[ ]
} LegalResident9={[ lc3_9=1 l34_9=1 ]
} LxC12={[ ]
} LxG10={[ ]
} LegalResident8={[ lc3_8=1 l34_8=1 ]
} LegalResident7={[ lc3_7=1 l34_7=1 ]
} LxC10={[ c5_10=1 ]
} GovernmentCommission0={[ ]
} LegalResident6={[ ]
} LxG8={[ ]
} LegalResident5={[ lc3_5=1 l34_5=1 ]
} LxC8={[ c5_8=1 ]
} LxG6={[ ]
} LegalResident4={[ lc3_4=1 l34_4=1 ]
} LxC6={[ c5_6=1 ]
} CINFORMI0={[ ]
} LegalResident3={[ lc3_3=1 l34_3=1 ]
} LxG4={[ ]
} PublicAdminOffice0={[ ]
} MICSystem0={[ ]
} LxC4={[ c5_4=1 ]
} LegalResident2={[ lc3_2=1 l34_2=1 ]
} LxG2={[ ]
} LegalResident1={[ lc3_1=1 l34_1=1 ]
} LxC2={[ c5_2=1 ]
} LxG0={[ ]
} LegalResident0={[ lc3_0=1 l34_0=1 ]
} LxC0={[ c5_0=1 ]
} ]
[ LxG20={[ ]
} LxG18={[ ]
} LxC20={[ ]
} LxC18={[ c5_18=1 ]
} LxG16={[ ]
} LxG14={[ ]
} LxC16={[ c5_16=1 ]
} LxC14={[ c5_14=1 ]
} LegalResident10={[ ]
} LxG12={[ ]
} LegalResident9={[ lc3_9=1 l34_9=1 ]
} LxC12={[ c5_12=1 ]
} LxG10={[ ]
} LegalResident8={[ lc3_8=1 l34_8=1 ]
} LegalResident7={[ lc3_7=1 l34_7=1 ]
} LxC10={[ ]
} GovernmentCommission0={[ ]
} LegalResident6={[ lc3_6=1 l34_6=1 ]
} LxG8={[ ]
} LegalResident5={[ ]
} LxC8={[ c5_8=1 ]
} LxG6={[ ]
} LegalResident4={[ lc3_4=1 l34_4=1 ]
} LxC6={[ c5_6=1 ]
} CINFORMI0={[ ]
} LegalResident3={[ lc3_3=1 l34_3=1 ]
} LxG4={[ ]
} PublicAdminOffice0={[ ]
} MICSystem0={[ ]
} LxC4={[ c5_4=1 ]
} LegalResident2={[ lc3_2=1 l34_2=1 ]
} LxG2={[ ]
} LegalResident1={[ lc3_1=1 l34_1=1 ]
} LxC2={[ c5_2=1 ]
} LxG0={[ ]
} LegalResident0={[ lc3_0=1 l34_0=1 ]
} LxC0={[ c5_0=1 ]
} ]
[ LxG20={[ ]
} LxG18={[ ]
} LxC20={[ ]
} LxC18={[ c5_18=1 ]
} LxG16={[ ]
} LxG14={[ ]
} LxC16={[ c5_16=1 ]
} LxC14={[ c5_14=1 ]
} LegalResident10={[ ]
} LxG12={[ ]
} LegalResident9={[ lc3_9=1 l34_9=1 ]
} LxC12={[ c5_12=1 ]
} LxG10={[ ]
} LegalResident8={[ lc3_8=1 l34_8=1 ]
} LegalResident7={[ lc3_7=1 l34_7=1 ]
} LxC10={[ c5_10=1 ]
} GovernmentCommission0={[ ]
} LegalResident6={[ lc3_6=1 l34_6=1 ]
} LxG8={[ ]
} LegalResident5={[ lc3_5=1 l34_5=1 ]
} LxC8={[ ]
} LxG6={[ ]
} LegalResident4={[ ]
} LxC6={[ c5_6=1 ]
} CINFORMI0={[ ]
} LegalResident3={[ lc3_3=1 l34_3=1 ]
} LxG4={[ ]
} PublicAdminOffice0={[ ]
} MICSystem0={[ ]
} LxC4={[ c5_4=1 ]
} LegalResident2={[ lc3_2=1 l34_2=1 ]
} LxG2={[ ]
} LegalResident1={[ lc3_1=1 l34_1=1 ]
} LxC2={[ c5_2=1 ]
} LxG0={[ ]
} LegalResident0={[ lc3_0=1 l34_0=1 ]
} LxC0={[ c5_0=1 ]
} ]
[ LxG20={[ ]
} LxG18={[ ]
} LxC20={[ ]
} LxC18={[ c5_18=1 ]
} LxG16={[ ]
} LxG14={[ ]
} LxC16={[ c5_16=1 ]
} LxC14={[ c5_14=1 ]
} LegalResident10={[ ]
} LxG12={[ ]
} LegalResident9={[ lc3_9=1 l34_9=1 ]
} LxC12={[ c5_12=1 ]
} LxG10={[ ]
} LegalResident8={[ lc3_8=1 l34_8=1 ]
} LegalResident7={[ lc3_7=1 l34_7=1 ]
} LxC10={[ c5_10=1 ]
} GovernmentCommission0={[ ]
} LegalResident6={[ lc3_6=1 l34_6=1 ]
} LxG8={[ ]
} LegalResident5={[ lc3_5=1 l34_5=1 ]
} LxC8={[ c5_8=1 ]
} LxG6={[ ]
} LegalResident4={[ lc3_4=1 l34_4=1 ]
} LxC6={[ ]
} CINFORMI0={[ ]
} LegalResident3={[ ]
} LxG4={[ ]
} PublicAdminOffice0={[ ]
} MICSystem0={[ ]
} LxC4={[ c5_4=1 ]
} LegalResident2={[ lc3_2=1 l34_2=1 ]
} LxG2={[ ]
} LegalResident1={[ lc3_1=1 l34_1=1 ]
} LxC2={[ c5_2=1 ]
} LxG0={[ ]
} LegalResident0={[ lc3_0=1 l34_0=1 ]
} LxC0={[ c5_0=1 ]
} ]
[ LxG20={[ ]
} LxG18={[ ]
} LxC20={[ ]
} LxC18={[ c5_18=1 ]
} LxG16={[ ]
} LxG14={[ ]
} LxC16={[ c5_16=1 ]
} LxC14={[ c5_14=1 ]
} LegalResident10={[ ]
} LxG12={[ ]
} LegalResident9={[ lc3_9=1 l34_9=1 ]
} LxC12={[ c5_12=1 ]
} LxG10={[ ]
} LegalResident8={[ lc3_8=1 l34_8=1 ]
} LegalResident7={[ lc3_7=1 l34_7=1 ]
} LxC10={[ c5_10=1 ]
} GovernmentCommission0={[ ]
} LegalResident6={[ lc3_6=1 l34_6=1 ]
} LxG8={[ ]
} LegalResident5={[ lc3_5=1 l34_5=1 ]
} LxC8={[ c5_8=1 ]
} LxG6={[ ]
} LegalResident4={[ lc3_4=1 l34_4=1 ]
} LxC6={[ c5_6=1 ]
} CINFORMI0={[ ]
} LegalResident3={[ lc3_3=1 l34_3=1 ]
} LxG4={[ ]
} PublicAdminOffice0={[ ]
} MICSystem0={[ ]
} LxC4={[ ]
} LegalResident2={[ ]
} LxG2={[ ]
} LegalResident1={[ lc3_1=1 l34_1=1 ]
} LxC2={[ c5_2=1 ]
} LxG0={[ ]
} LegalResident0={[ lc3_0=1 l34_0=1 ]
} LxC0={[ c5_0=1 ]
} ]
[ LxG20={[ ]
} LxG18={[ ]
} LxC20={[ ]
} LxC18={[ c5_18=1 ]
} LxG16={[ ]
} LxG14={[ ]
} LxC16={[ c5_16=1 ]
} LxC14={[ c5_14=1 ]
} LegalResident10={[ ]
} LxG12={[ ]
} LegalResident9={[ lc3_9=1 l34_9=1 ]
} LxC12={[ c5_12=1 ]
} LxG10={[ ]
} LegalResident8={[ lc3_8=1 l34_8=1 ]
} LegalResident7={[ lc3_7=1 l34_7=1 ]
} LxC10={[ c5_10=1 ]
} GovernmentCommission0={[ ]
} LegalResident6={[ lc3_6=1 l34_6=1 ]
} LxG8={[ ]
} LegalResident5={[ lc3_5=1 l34_5=1 ]
} LxC8={[ c5_8=1 ]
} LxG6={[ ]
} LegalResident4={[ lc3_4=1 l34_4=1 ]
} LxC6={[ c5_6=1 ]
} CINFORMI0={[ ]
} LegalResident3={[ lc3_3=1 l34_3=1 ]
} LxG4={[ ]
} PublicAdminOffice0={[ ]
} MICSystem0={[ ]
} LxC4={[ c5_4=1 ]
} LegalResident2={[ lc3_2=1 l34_2=1 ]
} LxG2={[ ]
} LegalResident1={[ ]
} LxC2={[ ]
} LxG0={[ ]
} LegalResident0={[ lc3_0=1 l34_0=1 ]
} LxC0={[ c5_0=1 ]
} ]
[ LxG20={[ ]
} LxG18={[ ]
} LxC20={[ ]
} LxC18={[ c5_18=1 ]
} LxG16={[ ]
} LxG14={[ ]
} LxC16={[ c5_16=1 ]
} LxC14={[ c5_14=1 ]
} LegalResident10={[ ]
} LxG12={[ ]
} LegalResident9={[ lc3_9=1 l34_9=1 ]
} LxC12={[ c5_12=1 ]
} LxG10={[ ]
} LegalResident8={[ lc3_8=1 l34_8=1 ]
} LegalResident7={[ lc3_7=1 l34_7=1 ]
} LxC10={[ c5_10=1 ]
} GovernmentCommission0={[ ]
} LegalResident6={[ lc3_6=1 l34_6=1 ]
} LxG8={[ ]
} LegalResident5={[ lc3_5=1 l34_5=1 ]
} LxC8={[ c5_8=1 ]
} LxG6={[ ]
} LegalResident4={[ lc3_4=1 l34_4=1 ]
} LxC6={[ c5_6=1 ]
} CINFORMI0={[ ]
} LegalResident3={[ lc3_3=1 l34_3=1 ]
} LxG4={[ ]
} PublicAdminOffice0={[ ]
} MICSystem0={[ ]
} LxC4={[ c5_4=1 ]
} LegalResident2={[ lc3_2=1 l34_2=1 ]
} LxG2={[ ]
} LegalResident1={[ lc3_1=1 l34_1=1 ]
} LxC2={[ c5_2=1 ]
} LxG0={[ ]
} LegalResident0={[ ]
} LxC0={[ ]
} ]
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O2, model.c], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1554496903682

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ GlobalProperties = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution GlobalProperties -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination GlobalProperties -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Apr 05, 2019 8:41:27 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, GlobalProperties, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Apr 05, 2019 8:41:27 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Apr 05, 2019 8:41:27 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
Apr 05, 2019 8:41:32 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Load time of PNML (colored model parsed with PNMLFW) : 4997 ms
Apr 05, 2019 8:41:32 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 104 places.
Apr 05, 2019 8:41:32 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Computed order using colors.
Apr 05, 2019 8:41:32 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: sort/places :LxM->m1,ml0,l2,m2,lm1,l3,m3,ml1,l4,lm2,m4,m5,l5,ml2,l6,lm3,m6,m7,ml3,l7,m9,m10,ml4,
Response->r0,
CINFORMI->c2,c4,c7,c0,c1,
LegalResident->lm0,l12,l0,l30,l31,lc1,l1,l32,lc2,l33,lc3,l34,cg0,l35,lg0,l36,l8,l9,lm4,l38,l10,l11,l13,l16,l14,lc0,l15,l17,l18,lp0,l19,lp1,l20,l21,l22,l24,l25,l23,l28,l26,l27,l29,
LxP->p1,p3,p2,p5,p4,p6,p9,pl0,pl1,
LxC->c3,cl2,c5,c6,cl0,cl1,
GovernmentCommission->g0,g2,g4,
LxR->gl1,l37,l39,l40,
MICSystem->m0,m8,m11,
PublicAdminOffice->p0,p7,p8,p10,p11,
LxG->g1,gl0,g3,

Apr 05, 2019 8:41:32 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 66 transitions.
Apr 05, 2019 8:41:32 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Computed order based on color domains.
Apr 05, 2019 8:41:32 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 16 ms
Apr 05, 2019 8:41:32 PM fr.lip6.move.gal.instantiate.DomainAnalyzer computeVariableDomains
INFO: Found a total of 5 fixed domain variables (out of 1486 variables) in GAL type FamilyReunion_COL_L00010M0001C001P001G001
Apr 05, 2019 8:41:32 PM fr.lip6.move.gal.instantiate.Simplifier printConstantVars
INFO: Found a total of 10 constant array cells/variables (out of 1486 variables) in type FamilyReunion_COL_L00010M0001C001P001G001
Apr 05, 2019 8:41:32 PM fr.lip6.move.gal.instantiate.Simplifier printConstantVars
INFO: m0[0-1], r0[0-1], p0[0-1], c0[0-1], c2[0-1],
Apr 05, 2019 8:41:33 PM fr.lip6.move.gal.instantiate.Instantiator instantiateParameters
INFO: On-the-fly reduction of False transitions avoided exploring 11.0 instantiations of transitions. Total transitions/syncs built is 1456
Apr 05, 2019 8:41:33 PM fr.lip6.move.gal.instantiate.DomainAnalyzer computeVariableDomains
INFO: Found a total of 5 fixed domain variables (out of 1486 variables) in GAL type FamilyReunion_COL_L00010M0001C001P001G001
Apr 05, 2019 8:41:33 PM fr.lip6.move.gal.instantiate.Simplifier printConstantVars
INFO: Found a total of 21 constant array cells/variables (out of 1486 variables) in type FamilyReunion_COL_L00010M0001C001P001G001
Apr 05, 2019 8:41:33 PM fr.lip6.move.gal.instantiate.Simplifier printConstantVars
INFO: m0[0-1], l40[1,3,5,7,9,11,13,15,17,19,21], r0[0-1], p0[0-1], c0[0-1], c2[0-1],
Apr 05, 2019 8:41:33 PM fr.lip6.move.gal.instantiate.Simplifier simplifyConstantVariables
INFO: Removed constant array :m0[]
Apr 05, 2019 8:41:33 PM fr.lip6.move.gal.instantiate.Simplifier simplifyConstantVariables
INFO: Removed constant array :r0[]
Apr 05, 2019 8:41:33 PM fr.lip6.move.gal.instantiate.Simplifier simplifyConstantVariables
INFO: Removed constant array :p0[]
Apr 05, 2019 8:41:33 PM fr.lip6.move.gal.instantiate.Simplifier simplifyConstantVariables
INFO: Removed constant array :c0[]
Apr 05, 2019 8:41:33 PM fr.lip6.move.gal.instantiate.Simplifier simplifyConstantVariables
INFO: Removed constant array :c2[]
Apr 05, 2019 8:41:33 PM fr.lip6.move.gal.instantiate.PropertySimplifier evalInInitialState
WARNING: Unexpected boolean logic operator in evalInInitialState fr.lip6.move.gal.impl.EXImpl
Apr 05, 2019 8:41:33 PM fr.lip6.move.gal.instantiate.PropertySimplifier rewriteWithInitialState
INFO: Reachable property FamilyReunion-COL-L00010M0001C001P001G001-GlobalProperties-0 is trivially true : it is verified in initial state.
Apr 05, 2019 8:41:33 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 493 ms
Apr 05, 2019 8:41:34 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 127 ms
Apr 05, 2019 8:41:35 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 785 transitions. Expanding to a total of 1467 deterministic transitions.
Apr 05, 2019 8:41:35 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 41 ms.
Apr 05, 2019 8:41:38 PM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Apr 05, 2019 8:41:38 PM fr.lip6.move.gal.instantiate.PropertySimplifier rewriteWithInitialState
INFO: Reachable property FamilyReunion-COL-L00010M0001C001P001G001-GlobalProperties-0 is trivially true : it is verified in initial state.
Apr 05, 2019 8:41:38 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 54 ms
Apr 05, 2019 8:41:38 PM fr.lip6.move.gal.instantiate.PropertySimplifier rewriteWithInitialState
INFO: Reachable property FamilyReunion-COL-L00010M0001C001P001G001-GlobalProperties-0 is trivially true : it is verified in initial state.
Apr 05, 2019 8:41:38 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 47 ms
Apr 05, 2019 8:41:38 PM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Apr 05, 2019 8:41:38 PM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
Apr 05, 2019 8:41:38 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 55 transitions.
Apr 05, 2019 8:41:38 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 0 place invariants in 64 ms
Apr 05, 2019 8:41:38 PM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 10 events :t660.t671.t715.t759.t792.t825.t814.t682.t847.t859.t881.t902.t924.t935.t947.t979.t1023.t1001.t1045.t1057.t1081.t1102.t1124.t1078,t660.t671.t715.t759.t792.t825.t814.t682.t847.t859.t881.t902.t924.t935.t947.t979.t1023.t1001.t1045.t1057.t1081.t1102.t1124.t1078,t660.t671.t715.t759.t792.t825.t814.t682.t847.t859.t881.t902.t924.t935.t947.t979.t1023.t1001.t1045.t1057.t1081.t1102.t1124.t1078,t660.t671.t715.t759.t792.t825.t814.t682.t847.t859.t881.t902.t924.t935.t947.t979.t1023.t1001.t1045.t1057.t1081.t1102.t1124.t1078,t660.t671.t715.t759.t792.t825.t814.t682.t847.t859.t881.t902.t924.t935.t947.t979.t1023.t1001.t1045.t1057.t1081.t1102.t1124.t1078,t660.t671.t715.t759.t792.t825.t814.t682.t847.t859.t881.t902.t924.t935.t947.t979.t1023.t1001.t1045.t1057.t1081.t1102.t1124.t1078,t660.t671.t715.t759.t792.t825.t814.t682.t847.t859.t881.t902.t924.t935.t947.t979.t1023.t1001.t1045.t1057.t1081.t1102.t1124.t1078,t660.t671.t715.t759.t792.t825.t814.t682.t847.t859.t881.t902.t924.t935.t947.t979.t1023.t1001.t1045.t1057.t1081.t1102.t1124.t1078,t660.t671.t715.t759.t792.t825.t814.t682.t847.t859.t881.t902.t924.t935.t947.t979.t1023.t1001.t1045.t1057.t1081.t1102.t1124.t1078,t660.t671.t715.t759.t792.t825.t814.t682.t847.t859.t881.t902.t924.t935.t947.t979.t1023.t1001.t1045.t1057.t1081.t1102.t1124.t1078,
Apr 05, 2019 8:41:38 PM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 20 events :t286.t517.t572.t617.t693.t737.t781,t286.t517.t572.t617.t693.t737.t781,t286.t517.t572.t617.t693.t737.t781,t286.t517.t572.t617.t693.t737.t781,t286.t517.t572.t617.t693.t737.t781,t286.t517.t572.t617.t693.t737.t781,t286.t517.t572.t617.t693.t737.t781,t286.t517.t572.t617.t693.t737.t781,t286.t517.t572.t617.t693.t737.t781,t286.t517.t572.t617.t693.t737.t781,t341.t385.t451.t473,t341.t385.t451.t473,t341.t385.t451.t473,t341.t385.t451.t473,t341.t385.t451.t473,t341.t385.t451.t473,t341.t385.t451.t473,t341.t385.t451.t473,t341.t385.t451.t473,t341.t385.t451.t473,
Apr 05, 2019 8:41:38 PM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 20 events :t660.t671.t715.t759.t792.t825.t814.t682.t847.t859.t881.t902.t924.t935.t947.t979.t1023.t1001.t1045.t1057.t1081.t1102.t1124.t1078,t660.t671.t715.t759.t792.t825.t814.t682.t847.t859.t881.t902.t924.t935.t947.t979.t1023.t1001.t1045.t1057.t1081.t1102.t1124.t1078,t660.t671.t715.t759.t792.t825.t814.t682.t847.t859.t881.t902.t924.t935.t947.t979.t1023.t1001.t1045.t1057.t1081.t1102.t1124.t1078,t660.t671.t715.t759.t792.t825.t814.t682.t847.t859.t881.t902.t924.t935.t947.t979.t1023.t1001.t1045.t1057.t1081.t1102.t1124.t1078,t660.t671.t715.t759.t792.t825.t814.t682.t847.t859.t881.t902.t924.t935.t947.t979.t1023.t1001.t1045.t1057.t1081.t1102.t1124.t1078,t660.t671.t715.t759.t792.t825.t814.t682.t847.t859.t881.t902.t924.t935.t947.t979.t1023.t1001.t1045.t1057.t1081.t1102.t1124.t1078,t660.t671.t715.t759.t792.t825.t814.t682.t847.t859.t881.t902.t924.t935.t947.t979.t1023.t1001.t1045.t1057.t1081.t1102.t1124.t1078,t660.t671.t715.t759.t792.t825.t814.t682.t847.t859.t881.t902.t924.t935.t947.t979.t1023.t1001.t1045.t1057.t1081.t1102.t1124.t1078,t660.t671.t715.t759.t792.t825.t814.t682.t847.t859.t881.t902.t924.t935.t947.t979.t1023.t1001.t1045.t1057.t1081.t1102.t1124.t1078,t660.t671.t715.t759.t792.t825.t814.t682.t847.t859.t881.t902.t924.t935.t947.t979.t1023.t1001.t1045.t1057.t1081.t1102.t1124.t1078,t1135.t1157.t1179.t1190.t1201.t1212.t1223.t0.t44.t78.t122.t143.t209.t308,t1135.t1157.t1179.t1190.t1201.t1212.t1223.t0.t44.t78.t122.t143.t209.t308,t1135.t1157.t1179.t1190.t1201.t1212.t1223.t0.t44.t78.t122.t143.t209.t308,t1135.t1157.t1179.t1190.t1201.t1212.t1223.t0.t44.t78.t122.t143.t209.t308,t1135.t1157.t1179.t1190.t1201.t1212.t1223.t0.t44.t78.t122.t143.t209.t308,t1135.t1157.t1179.t1190.t1201.t1212.t1223.t0.t44.t78.t122.t143.t209.t308,t1135.t1157.t1179.t1190.t1201.t1212.t1223.t0.t44.t78.t122.t143.t209.t308,t1135.t1157.t1179.t1190.t1201.t1212.t1223.t0.t44.t78.t122.t143.t209.t308,t1135.t1157.t1179.t1190.t1201.t1212.t1223.t0.t44.t78.t122.t143.t209.t308,t1135.t1157.t1179.t1190.t1201.t1212.t1223.t0.t44.t78.t122.t143.t209.t308,
Apr 05, 2019 8:41:38 PM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 20 events :t1135.t1157.t1179.t1190.t1201.t1212.t1223.t0.t44.t78.t122.t143.t209.t308,t1135.t1157.t1179.t1190.t1201.t1212.t1223.t0.t44.t78.t122.t143.t209.t308,t1135.t1157.t1179.t1190.t1201.t1212.t1223.t0.t44.t78.t122.t143.t209.t308,t1135.t1157.t1179.t1190.t1201.t1212.t1223.t0.t44.t78.t122.t143.t209.t308,t1135.t1157.t1179.t1190.t1201.t1212.t1223.t0.t44.t78.t122.t143.t209.t308,t1135.t1157.t1179.t1190.t1201.t1212.t1223.t0.t44.t78.t122.t143.t209.t308,t1135.t1157.t1179.t1190.t1201.t1212.t1223.t0.t44.t78.t122.t143.t209.t308,t1135.t1157.t1179.t1190.t1201.t1212.t1223.t0.t44.t78.t122.t143.t209.t308,t1135.t1157.t1179.t1190.t1201.t1212.t1223.t0.t44.t78.t122.t143.t209.t308,t1135.t1157.t1179.t1190.t1201.t1212.t1223.t0.t44.t78.t122.t143.t209.t308,t220,t220,t220,t220,t220,t220,t220,t220,t220,t220,
Apr 05, 2019 8:41:38 PM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 70 redundant transitions.
Apr 05, 2019 8:41:38 PM fr.lip6.move.gal.instantiate.PropertySimplifier rewriteWithInitialState
INFO: Reachable property FamilyReunion-COL-L00010M0001C001P001G001-GlobalProperties-0 is trivially true : it is verified in initial state.
Apr 05, 2019 8:41:38 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 422 ms
Apr 05, 2019 8:41:38 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/GlobalProperties.pnml.gal : 8 ms
Apr 05, 2019 8:41:40 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 82 variables to be positive in 2289 ms
Apr 05, 2019 8:41:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 55 transitions.
Apr 05, 2019 8:41:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/55 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Apr 05, 2019 8:41:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 2 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Apr 05, 2019 8:41:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 55 transitions.
Apr 05, 2019 8:41:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 2 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Apr 05, 2019 8:41:41 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 55 transitions.
Apr 05, 2019 8:41:42 PM org.smtlib.impl.Script execute
WARNING: Script execution failed on command (assert (and (>= (select s0 8) 1) (>= (select s0 11) 1))) with error (error "Failed to assert expression: java.io.IOException: Broken pipe (and (>= (select s0 8) 1) (>= (select s0 11) 1))")
[(assert (and (>= (select s0 8) 1) (>= (select s0 11) 1)))]
Skipping mayMatrices nes/nds SMT solver raised an exception.
java.lang.RuntimeException: SMT solver raised an exception.
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.computeCoEnablingMatrix(NecessaryEnablingsolver.java:475)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:530)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
Apr 05, 2019 8:41:42 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 4331ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L00010M0001C001P001G001"
export BK_EXAMINATION="GlobalProperties"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3954"
echo " Executing tool itstools"
echo " Input is FamilyReunion-COL-L00010M0001C001P001G001, examination is GlobalProperties"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r184-csrt-155344537600075"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L00010M0001C001P001G001.tgz
mv FamilyReunion-COL-L00010M0001C001P001G001 execution
cd execution
if [ "GlobalProperties" = "GlobalProperties" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
if [ "GlobalProperties" = "UpperBounds" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "GlobalProperties" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "GlobalProperties" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "GlobalProperties.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property GlobalProperties.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "GlobalProperties.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' GlobalProperties.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;