Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/local/x2003239/mcc2019-input.r184-csrt-155344537500016.qcow2', fmt=qcow2 size=4294967296 backing_file=/local/x2003239/mcc2019-input.qcow2 encryption=off cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................
=====================================================================
Generated by BenchKit 2-3954
Executing tool itstools
Input is BART-PT-005, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r184-csrt-155344537500016
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.4M
-rw-r--r-- 1 mcc users 3.4K Mar 10 19:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 16K Mar 10 19:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 3.5K Mar 10 19:08 CTLFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 10 19:08 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 10 17:46 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K Mar 10 17:46 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.5K Mar 10 19:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 9.9K Mar 10 19:07 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Mar 10 19:07 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.8K Mar 10 19:07 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Mar 10 17:46 NewModel
-rw-r--r-- 1 mcc users 3.6K Mar 10 19:04 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 14K Mar 10 19:04 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 102 Mar 10 18:58 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 340 Mar 10 18:58 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 3.5K Mar 10 18:59 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 15K Mar 10 18:59 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Mar 10 19:07 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Mar 10 19:07 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 10 17:46 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 10 17:46 instance
-rw-r--r-- 1 mcc users 6 Mar 10 17:46 iscolored
-rw-r--r-- 1 mcc users 1.2M Mar 10 17:46 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BART-PT-005-LTLFireability-00
FORMULA_NAME BART-PT-005-LTLFireability-01
FORMULA_NAME BART-PT-005-LTLFireability-02
FORMULA_NAME BART-PT-005-LTLFireability-03
FORMULA_NAME BART-PT-005-LTLFireability-04
FORMULA_NAME BART-PT-005-LTLFireability-05
FORMULA_NAME BART-PT-005-LTLFireability-06
FORMULA_NAME BART-PT-005-LTLFireability-07
FORMULA_NAME BART-PT-005-LTLFireability-08
FORMULA_NAME BART-PT-005-LTLFireability-09
FORMULA_NAME BART-PT-005-LTLFireability-10
FORMULA_NAME BART-PT-005-LTLFireability-11
FORMULA_NAME BART-PT-005-LTLFireability-12
FORMULA_NAME BART-PT-005-LTLFireability-13
FORMULA_NAME BART-PT-005-LTLFireability-14
FORMULA_NAME BART-PT-005-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1553544721227

Working with output stream class java.io.PrintStream
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903171603/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903171603/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((X(X(X(G(G("(TrainState_1_1_25>=1)")))))))
Formula 0 simplified : !XXXG"(TrainState_1_1_25>=1)"
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 1010 rows 660 cols
invariant :TrainState_3_0_0 + TrainState_3_1_1 + TrainState_3_1_2 + TrainState_3_1_3 + TrainState_3_1_4 + TrainState_3_2_4 + TrainState_3_1_5 + TrainState_3_2_5 + TrainState_3_1_6 + TrainState_3_2_6 + TrainState_3_1_7 + TrainState_3_2_7 + TrainState_3_3_7 + TrainState_3_1_8 + TrainState_3_2_8 + TrainState_3_3_8 + TrainState_3_1_9 + TrainState_3_2_9 + TrainState_3_3_9 + TrainState_3_1_10 + TrainState_3_2_10 + TrainState_3_3_10 + TrainState_3_1_11 + TrainState_3_2_11 + TrainState_3_3_11 + TrainState_3_4_11 + TrainState_3_1_12 + TrainState_3_2_12 + TrainState_3_3_12 + TrainState_3_4_12 + TrainState_3_1_13 + TrainState_3_2_13 + TrainState_3_3_13 + TrainState_3_4_13 + TrainState_3_1_14 + TrainState_3_2_14 + TrainState_3_3_14 + TrainState_3_4_14 + TrainState_3_1_15 + TrainState_3_2_15 + TrainState_3_3_15 + TrainState_3_4_15 + TrainState_3_1_16 + TrainState_3_2_16 + TrainState_3_3_16 + TrainState_3_4_16 + TrainState_3_1_17 + TrainState_3_2_17 + TrainState_3_3_17 + TrainState_3_4_17 + TrainState_3_1_18 + TrainState_3_2_18 + TrainState_3_3_18 + TrainState_3_4_18 + TrainState_3_1_19 + TrainState_3_2_19 + TrainState_3_3_19 + TrainState_3_4_19 + TrainState_3_1_20 + TrainState_3_2_20 + TrainState_3_3_20 + TrainState_3_4_20 + TrainState_3_1_21 + TrainState_3_2_21 + TrainState_3_3_21 + TrainState_3_4_21 + TrainState_3_1_22 + TrainState_3_2_22 + TrainState_3_3_22 + TrainState_3_4_22 + TrainState_3_1_23 + TrainState_3_2_23 + TrainState_3_3_23 + TrainState_3_4_23 + TrainState_3_1_24 + TrainState_3_2_24 + TrainState_3_3_24 + TrainState_3_4_24 + TrainState_3_1_25 + TrainState_3_2_25 + TrainState_3_3_25 + TrainState_3_4_25 + TrainState_3_1_26 + TrainState_3_2_26 + TrainState_3_3_26 + TrainState_3_4_26 + TrainState_3_1_27 + TrainState_3_2_27 + TrainState_3_3_27 + TrainState_3_4_27 + TrainState_3_1_28 + TrainState_3_2_28 + TrainState_3_3_28 + TrainState_3_4_28 + TrainState_3_1_29 + TrainState_3_2_29 + TrainState_3_3_29 + TrainState_3_4_29 + TrainState_3_1_30 + TrainState_3_2_30 + TrainState_3_3_30 + TrainState_3_4_30 + TrainState_3_1_31 + TrainState_3_2_31 + TrainState_3_3_31 + TrainState_3_4_31 + TrainState_3_1_32 + TrainState_3_2_32 + TrainState_3_3_32 + TrainState_3_4_32 + TrainState_3_1_33 + TrainState_3_2_33 + TrainState_3_3_33 + TrainState_3_4_33 + TrainState_3_1_34 + TrainState_3_2_34 + TrainState_3_3_34 + TrainState_3_4_34 + TrainState_3_1_35 + TrainState_3_2_35 + TrainState_3_3_35 + TrainState_3_1_36 + TrainState_3_2_36 + TrainState_3_3_36 + TrainState_3_1_37 + TrainState_3_2_37 + TrainState_3_3_37 + TrainState_3_1_38 + TrainState_3_2_38 + TrainState_3_1_39 + TrainState_3_2_39 + TrainState_3_1_40 = 1
invariant :TrainState_5_0_0 + TrainState_5_1_1 + TrainState_5_1_2 + TrainState_5_1_3 + TrainState_5_1_4 + TrainState_5_2_4 + TrainState_5_1_5 + TrainState_5_2_5 + TrainState_5_1_6 + TrainState_5_2_6 + TrainState_5_1_7 + TrainState_5_2_7 + TrainState_5_3_7 + TrainState_5_1_8 + TrainState_5_2_8 + TrainState_5_3_8 + TrainState_5_1_9 + TrainState_5_2_9 + TrainState_5_3_9 + TrainState_5_1_10 + TrainState_5_2_10 + TrainState_5_3_10 + TrainState_5_1_11 + TrainState_5_2_11 + TrainState_5_3_11 + TrainState_5_4_11 + TrainState_5_1_12 + TrainState_5_2_12 + TrainState_5_3_12 + TrainState_5_4_12 + TrainState_5_1_13 + TrainState_5_2_13 + TrainState_5_3_13 + TrainState_5_4_13 + TrainState_5_1_14 + TrainState_5_2_14 + TrainState_5_3_14 + TrainState_5_4_14 + TrainState_5_1_15 + TrainState_5_2_15 + TrainState_5_3_15 + TrainState_5_4_15 + TrainState_5_1_16 + TrainState_5_2_16 + TrainState_5_3_16 + TrainState_5_4_16 + TrainState_5_1_17 + TrainState_5_2_17 + TrainState_5_3_17 + TrainState_5_4_17 + TrainState_5_1_18 + TrainState_5_2_18 + TrainState_5_3_18 + TrainState_5_4_18 + TrainState_5_1_19 + TrainState_5_2_19 + TrainState_5_3_19 + TrainState_5_4_19 + TrainState_5_1_20 + TrainState_5_2_20 + TrainState_5_3_20 + TrainState_5_4_20 + TrainState_5_1_21 + TrainState_5_2_21 + TrainState_5_3_21 + TrainState_5_4_21 + TrainState_5_1_22 + TrainState_5_2_22 + TrainState_5_3_22 + TrainState_5_4_22 + TrainState_5_1_23 + TrainState_5_2_23 + TrainState_5_3_23 + TrainState_5_4_23 + TrainState_5_1_24 + TrainState_5_2_24 + TrainState_5_3_24 + TrainState_5_4_24 + TrainState_5_1_25 + TrainState_5_2_25 + TrainState_5_3_25 + TrainState_5_4_25 + TrainState_5_1_26 + TrainState_5_2_26 + TrainState_5_3_26 + TrainState_5_4_26 + TrainState_5_1_27 + TrainState_5_2_27 + TrainState_5_3_27 + TrainState_5_4_27 + TrainState_5_1_28 + TrainState_5_2_28 + TrainState_5_3_28 + TrainState_5_4_28 + TrainState_5_1_29 + TrainState_5_2_29 + TrainState_5_3_29 + TrainState_5_4_29 + TrainState_5_1_30 + TrainState_5_2_30 + TrainState_5_3_30 + TrainState_5_4_30 + TrainState_5_1_31 + TrainState_5_2_31 + TrainState_5_3_31 + TrainState_5_4_31 + TrainState_5_1_32 + TrainState_5_2_32 + TrainState_5_3_32 + TrainState_5_4_32 + TrainState_5_1_33 + TrainState_5_2_33 + TrainState_5_3_33 + TrainState_5_4_33 + TrainState_5_1_34 + TrainState_5_2_34 + TrainState_5_3_34 + TrainState_5_4_34 + TrainState_5_1_35 + TrainState_5_2_35 + TrainState_5_3_35 + TrainState_5_1_36 + TrainState_5_2_36 + TrainState_5_3_36 + TrainState_5_1_37 + TrainState_5_2_37 + TrainState_5_3_37 + TrainState_5_1_38 + TrainState_5_2_38 + TrainState_5_1_39 + TrainState_5_2_39 + TrainState_5_1_40 = 1
invariant :TrainState_1_0_0 + TrainState_1_1_1 + TrainState_1_1_2 + TrainState_1_1_3 + TrainState_1_1_4 + TrainState_1_2_4 + TrainState_1_1_5 + TrainState_1_2_5 + TrainState_1_1_6 + TrainState_1_2_6 + TrainState_1_1_7 + TrainState_1_2_7 + TrainState_1_3_7 + TrainState_1_1_8 + TrainState_1_2_8 + TrainState_1_3_8 + TrainState_1_1_9 + TrainState_1_2_9 + TrainState_1_3_9 + TrainState_1_1_10 + TrainState_1_2_10 + TrainState_1_3_10 + TrainState_1_1_11 + TrainState_1_2_11 + TrainState_1_3_11 + TrainState_1_4_11 + TrainState_1_1_12 + TrainState_1_2_12 + TrainState_1_3_12 + TrainState_1_4_12 + TrainState_1_1_13 + TrainState_1_2_13 + TrainState_1_3_13 + TrainState_1_4_13 + TrainState_1_1_14 + TrainState_1_2_14 + TrainState_1_3_14 + TrainState_1_4_14 + TrainState_1_1_15 + TrainState_1_2_15 + TrainState_1_3_15 + TrainState_1_4_15 + TrainState_1_1_16 + TrainState_1_2_16 + TrainState_1_3_16 + TrainState_1_4_16 + TrainState_1_1_17 + TrainState_1_2_17 + TrainState_1_3_17 + TrainState_1_4_17 + TrainState_1_1_18 + TrainState_1_2_18 + TrainState_1_3_18 + TrainState_1_4_18 + TrainState_1_1_19 + TrainState_1_2_19 + TrainState_1_3_19 + TrainState_1_4_19 + TrainState_1_1_20 + TrainState_1_2_20 + TrainState_1_3_20 + TrainState_1_4_20 + TrainState_1_1_21 + TrainState_1_2_21 + TrainState_1_3_21 + TrainState_1_4_21 + TrainState_1_1_22 + TrainState_1_2_22 + TrainState_1_3_22 + TrainState_1_4_22 + TrainState_1_1_23 + TrainState_1_2_23 + TrainState_1_3_23 + TrainState_1_4_23 + TrainState_1_1_24 + TrainState_1_2_24 + TrainState_1_3_24 + TrainState_1_4_24 + TrainState_1_1_25 + TrainState_1_2_25 + TrainState_1_3_25 + TrainState_1_4_25 + TrainState_1_1_26 + TrainState_1_2_26 + TrainState_1_3_26 + TrainState_1_4_26 + TrainState_1_1_27 + TrainState_1_2_27 + TrainState_1_3_27 + TrainState_1_4_27 + TrainState_1_1_28 + TrainState_1_2_28 + TrainState_1_3_28 + TrainState_1_4_28 + TrainState_1_1_29 + TrainState_1_2_29 + TrainState_1_3_29 + TrainState_1_4_29 + TrainState_1_1_30 + TrainState_1_2_30 + TrainState_1_3_30 + TrainState_1_4_30 + TrainState_1_1_31 + TrainState_1_2_31 + TrainState_1_3_31 + TrainState_1_4_31 + TrainState_1_1_32 + TrainState_1_2_32 + TrainState_1_3_32 + TrainState_1_4_32 + TrainState_1_1_33 + TrainState_1_2_33 + TrainState_1_3_33 + TrainState_1_4_33 + TrainState_1_1_34 + TrainState_1_2_34 + TrainState_1_3_34 + TrainState_1_4_34 + TrainState_1_1_35 + TrainState_1_2_35 + TrainState_1_3_35 + TrainState_1_1_36 + TrainState_1_2_36 + TrainState_1_3_36 + TrainState_1_1_37 + TrainState_1_2_37 + TrainState_1_3_37 + TrainState_1_1_38 + TrainState_1_2_38 + TrainState_1_1_39 + TrainState_1_2_39 + TrainState_1_1_40 = 1
invariant :TrainState_4_0_0 + TrainState_4_1_1 + TrainState_4_1_2 + TrainState_4_1_3 + TrainState_4_1_4 + TrainState_4_2_4 + TrainState_4_1_5 + TrainState_4_2_5 + TrainState_4_1_6 + TrainState_4_2_6 + TrainState_4_1_7 + TrainState_4_2_7 + TrainState_4_3_7 + TrainState_4_1_8 + TrainState_4_2_8 + TrainState_4_3_8 + TrainState_4_1_9 + TrainState_4_2_9 + TrainState_4_3_9 + TrainState_4_1_10 + TrainState_4_2_10 + TrainState_4_3_10 + TrainState_4_1_11 + TrainState_4_2_11 + TrainState_4_3_11 + TrainState_4_4_11 + TrainState_4_1_12 + TrainState_4_2_12 + TrainState_4_3_12 + TrainState_4_4_12 + TrainState_4_1_13 + TrainState_4_2_13 + TrainState_4_3_13 + TrainState_4_4_13 + TrainState_4_1_14 + TrainState_4_2_14 + TrainState_4_3_14 + TrainState_4_4_14 + TrainState_4_1_15 + TrainState_4_2_15 + TrainState_4_3_15 + TrainState_4_4_15 + TrainState_4_1_16 + TrainState_4_2_16 + TrainState_4_3_16 + TrainState_4_4_16 + TrainState_4_1_17 + TrainState_4_2_17 + TrainState_4_3_17 + TrainState_4_4_17 + TrainState_4_1_18 + TrainState_4_2_18 + TrainState_4_3_18 + TrainState_4_4_18 + TrainState_4_1_19 + TrainState_4_2_19 + TrainState_4_3_19 + TrainState_4_4_19 + TrainState_4_1_20 + TrainState_4_2_20 + TrainState_4_3_20 + TrainState_4_4_20 + TrainState_4_1_21 + TrainState_4_2_21 + TrainState_4_3_21 + TrainState_4_4_21 + TrainState_4_1_22 + TrainState_4_2_22 + TrainState_4_3_22 + TrainState_4_4_22 + TrainState_4_1_23 + TrainState_4_2_23 + TrainState_4_3_23 + TrainState_4_4_23 + TrainState_4_1_24 + TrainState_4_2_24 + TrainState_4_3_24 + TrainState_4_4_24 + TrainState_4_1_25 + TrainState_4_2_25 + TrainState_4_3_25 + TrainState_4_4_25 + TrainState_4_1_26 + TrainState_4_2_26 + TrainState_4_3_26 + TrainState_4_4_26 + TrainState_4_1_27 + TrainState_4_2_27 + TrainState_4_3_27 + TrainState_4_4_27 + TrainState_4_1_28 + TrainState_4_2_28 + TrainState_4_3_28 + TrainState_4_4_28 + TrainState_4_1_29 + TrainState_4_2_29 + TrainState_4_3_29 + TrainState_4_4_29 + TrainState_4_1_30 + TrainState_4_2_30 + TrainState_4_3_30 + TrainState_4_4_30 + TrainState_4_1_31 + TrainState_4_2_31 + TrainState_4_3_31 + TrainState_4_4_31 + TrainState_4_1_32 + TrainState_4_2_32 + TrainState_4_3_32 + TrainState_4_4_32 + TrainState_4_1_33 + TrainState_4_2_33 + TrainState_4_3_33 + TrainState_4_4_33 + TrainState_4_1_34 + TrainState_4_2_34 + TrainState_4_3_34 + TrainState_4_4_34 + TrainState_4_1_35 + TrainState_4_2_35 + TrainState_4_3_35 + TrainState_4_1_36 + TrainState_4_2_36 + TrainState_4_3_36 + TrainState_4_1_37 + TrainState_4_2_37 + TrainState_4_3_37 + TrainState_4_1_38 + TrainState_4_2_38 + TrainState_4_1_39 + TrainState_4_2_39 + TrainState_4_1_40 = 1
invariant :TrainState_2_0_0 + TrainState_2_1_1 + TrainState_2_1_2 + TrainState_2_1_3 + TrainState_2_1_4 + TrainState_2_2_4 + TrainState_2_1_5 + TrainState_2_2_5 + TrainState_2_1_6 + TrainState_2_2_6 + TrainState_2_1_7 + TrainState_2_2_7 + TrainState_2_3_7 + TrainState_2_1_8 + TrainState_2_2_8 + TrainState_2_3_8 + TrainState_2_1_9 + TrainState_2_2_9 + TrainState_2_3_9 + TrainState_2_1_10 + TrainState_2_2_10 + TrainState_2_3_10 + TrainState_2_1_11 + TrainState_2_2_11 + TrainState_2_3_11 + TrainState_2_4_11 + TrainState_2_1_12 + TrainState_2_2_12 + TrainState_2_3_12 + TrainState_2_4_12 + TrainState_2_1_13 + TrainState_2_2_13 + TrainState_2_3_13 + TrainState_2_4_13 + TrainState_2_1_14 + TrainState_2_2_14 + TrainState_2_3_14 + TrainState_2_4_14 + TrainState_2_1_15 + TrainState_2_2_15 + TrainState_2_3_15 + TrainState_2_4_15 + TrainState_2_1_16 + TrainState_2_2_16 + TrainState_2_3_16 + TrainState_2_4_16 + TrainState_2_1_17 + TrainState_2_2_17 + TrainState_2_3_17 + TrainState_2_4_17 + TrainState_2_1_18 + TrainState_2_2_18 + TrainState_2_3_18 + TrainState_2_4_18 + TrainState_2_1_19 + TrainState_2_2_19 + TrainState_2_3_19 + TrainState_2_4_19 + TrainState_2_1_20 + TrainState_2_2_20 + TrainState_2_3_20 + TrainState_2_4_20 + TrainState_2_1_21 + TrainState_2_2_21 + TrainState_2_3_21 + TrainState_2_4_21 + TrainState_2_1_22 + TrainState_2_2_22 + TrainState_2_3_22 + TrainState_2_4_22 + TrainState_2_1_23 + TrainState_2_2_23 + TrainState_2_3_23 + TrainState_2_4_23 + TrainState_2_1_24 + TrainState_2_2_24 + TrainState_2_3_24 + TrainState_2_4_24 + TrainState_2_1_25 + TrainState_2_2_25 + TrainState_2_3_25 + TrainState_2_4_25 + TrainState_2_1_26 + TrainState_2_2_26 + TrainState_2_3_26 + TrainState_2_4_26 + TrainState_2_1_27 + TrainState_2_2_27 + TrainState_2_3_27 + TrainState_2_4_27 + TrainState_2_1_28 + TrainState_2_2_28 + TrainState_2_3_28 + TrainState_2_4_28 + TrainState_2_1_29 + TrainState_2_2_29 + TrainState_2_3_29 + TrainState_2_4_29 + TrainState_2_1_30 + TrainState_2_2_30 + TrainState_2_3_30 + TrainState_2_4_30 + TrainState_2_1_31 + TrainState_2_2_31 + TrainState_2_3_31 + TrainState_2_4_31 + TrainState_2_1_32 + TrainState_2_2_32 + TrainState_2_3_32 + TrainState_2_4_32 + TrainState_2_1_33 + TrainState_2_2_33 + TrainState_2_3_33 + TrainState_2_4_33 + TrainState_2_1_34 + TrainState_2_2_34 + TrainState_2_3_34 + TrainState_2_4_34 + TrainState_2_1_35 + TrainState_2_2_35 + TrainState_2_3_35 + TrainState_2_1_36 + TrainState_2_2_36 + TrainState_2_3_36 + TrainState_2_1_37 + TrainState_2_2_37 + TrainState_2_3_37 + TrainState_2_1_38 + TrainState_2_2_38 + TrainState_2_1_39 + TrainState_2_2_39 + TrainState_2_1_40 = 1
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O2, model.c], workingDir=/home/mcc/execution]
Compilation finished in 11659 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 116 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X(X(X([]([]((LTLAP0==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 4147 ms.
FORMULA BART-PT-005-LTLFireability-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, [](([]((LTLAP1==true)))U([]([]((LTLAP2==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 7752 ms.
FORMULA BART-PT-005-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, <>(X(<>(<>([]((LTLAP3==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 392 ms.
FORMULA BART-PT-005-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X((LTLAP4==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1446 ms.
FORMULA BART-PT-005-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, false, --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 7763 ms.
FORMULA BART-PT-005-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, [](X(<>(X((LTLAP5==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1748 ms.
FORMULA BART-PT-005-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, (X([](X((LTLAP6==true)))))U(<>((LTLAP7==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 939 ms.
FORMULA BART-PT-005-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, []((LTLAP8==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 7794 ms.
FORMULA BART-PT-005-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, true, --buchi-type=spotba], workingDir=/home/mcc/execution]
Reverse transition relation is exact ! Faster fixpoint algorithm enabled.
LTSmin run took 7879 ms.
FORMULA BART-PT-005-LTLFireability-08 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, (((LTLAP9==true))U(X((LTLAP10==true))))U(((LTLAP11==true))U(X((LTLAP12==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 403 ms.
FORMULA BART-PT-005-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, <>([](<>(X((LTLAP13==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 817 ms.
FORMULA BART-PT-005-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X(<>(X(X(X((LTLAP14==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 6196 ms.
FORMULA BART-PT-005-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, [](<>(<>(<>((LTLAP15==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 7683 ms.
FORMULA BART-PT-005-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, <>((LTLAP16==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 7659 ms.
FORMULA BART-PT-005-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, <>((<>([]((LTLAP17==true))))U(X(X((LTLAP10==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1034 ms.
FORMULA BART-PT-005-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, <>(<>(((LTLAP18==true))U([]((LTLAP19==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 7663 ms.
FORMULA BART-PT-005-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1553544816205

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ LTLFireability = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Mar 25, 2019 8:12:03 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Mar 25, 2019 8:12:03 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Mar 25, 2019 8:12:03 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 200 ms
Mar 25, 2019 8:12:03 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 870 places.
Mar 25, 2019 8:12:03 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 1010 transitions.
Mar 25, 2019 8:12:04 PM fr.lip6.move.gal.instantiate.DomainAnalyzer computeVariableDomains
INFO: Found a total of 210 fixed domain variables (out of 870 variables) in GAL type BART_PT_005
Mar 25, 2019 8:12:04 PM fr.lip6.move.gal.instantiate.Simplifier printConstantVars
INFO: Found a total of 210 constant array cells/variables (out of 870 variables) in type BART_PT_005
Mar 25, 2019 8:12:04 PM fr.lip6.move.gal.instantiate.Simplifier printConstantVars
INFO: NewDistTable_39_3_36,NewDistTable_35_3_32,NewDistTable_8_2_6,NewDistTable_18_3_15,NewDistTable_31_2_29,NewDistTable_19_2_17,NewDistTable_14_3_11,NewDistTable_28_1_27,NewDistTable_17_5_12,NewDistTable_13_3_10,NewDistTable_7_4_3,DistStation_6,NewDistTable_9_1_8,NewDistTable_24_4_20,NewDistTable_27_5_22,NewDistTable_14_4_10,NewDistTable_21_3_18,NewDistTable_8_1_7,NewDistTable_34_5_29,NewDistTable_7_3_4,DistStation_33,NewDistTable_20_4_16,NewDistTable_26_4_22,DistStation_24,NewDistTable_9_2_7,NewDistTable_11_5_6,NewDistTable_2_1_1,NewDistTable_12_3_9,NewDistTable_24_5_19,NewDistTable_36_4_32,NewDistTable_14_1_13,NewDistTable_28_2_26,DistStation_34,DistStation_19,NewDistTable_2_2_0,NewDistTable_21_4_17,NewDistTable_37_4_33,NewDistTable_30_3_27,DistStation_20,NewDistTable_18_2_16,DistStation_38,NewDistTable_20_5_15,NewDistTable_30_5_25,NewDistTable_30_1_29,DistStation_15,NewDistTable_26_1_25,NewDistTable_21_2_19,DistStation_9,DistStation_7,DistStation_10,NewDistTable_35_4_31,NewDistTable_6_1_5,NewDistTable_24_2_22,NewDistTable_8_4_4,NewDistTable_36_1_35,NewDistTable_24_1_23,NewDistTable_16_1_15,DistStation_22,NewDistTable_34_1_33,StopTable_3_6,NewDistTable_9_3_6,NewDistTable_15_2_13,NewDistTable_19_3_16,NewDistTable_21_1_20,NewDistTable_16_5_11,NewDistTable_11_2_9,DistStation_35,StopTable_4_10,NewDistTable_20_1_19,NewDistTable_38_1_37,NewDistTable_21_5_16,NewDistTable_15_4_11,DistStation_8,NewDistTable_10_4_6,NewDistTable_32_2_30,NewDistTable_11_4_7,DistStation_26,NewDistTable_22_5_17,NewDistTable_27_1_26,DistStation_16,NewDistTable_24_3_21,NewDistTable_16_3_13,NewDistTable_17_4_13,DistStation_25,NewDistTable_4_2_2,NewDistTable_6_2_4,DistStation_18,NewDistTable_3_2_1,NewDistTable_26_3_23,NewDistTable_36_3_33,NewDistTable_38_3_35,NewDistTable_10_2_8,DistStation_21,NewDistTable_28_5_23,DistStation_37,NewDistTable_5_2_3,NewDistTable_7_2_5,NewDistTable_26_5_21,NewDistTable_19_5_14,DistStation_12,DistStation_17,NewDistTable_19_4_15,NewDistTable_22_4_18,NewDistTable_25_1_24,NewDistTable_18_5_13,NewDistTable_17_1_16,NewDistTable_4_1_3,NewDistTable_13_2_11,NewDistTable_14_2_12,NewDistTable_32_3_29,NewDistTable_7_1_6,NewDistTable_13_4_9,NewDistTable_16_4_12,NewDistTable_20_2_18,NewDistTable_11_3_8,NewDistTable_15_5_10,NewDistTable_31_1_30,NewDistTable_9_4_5,DistStation_11,NewDistTable_31_5_26,NewDistTable_5_3_2,DistStation_27,NewDistTable_10_3_7,NewDistTable_29_2_27,NewDistTable_10_1_9,NewDistTable_34_4_30,NewDistTable_23_2_21,NewDistTable_12_2_10,DistStation_13,NewDistTable_29_5_24,NewDistTable_35_2_33,NewDistTable_33_4_29,NewDistTable_26_2_24,DistStation_39,DistStation_36,NewDistTable_25_2_23,NewDistTable_23_5_18,NewDistTable_12_4_8,NewDistTable_25_4_21,DistStation_5,NewDistTable_16_2_14,NewDistTable_27_2_25,NewDistTable_28_4_24,NewDistTable_35_1_34,NewDistTable_37_3_34,NewDistTable_31_3_28,NewDistTable_23_4_19,NewDistTable_23_3_20,NewDistTable_18_1_17,NewDistTable_4_3_1,NewDistTable_40_2_38,NewDistTable_28_3_25,StopTable_2_3,NewDistTable_39_2_37,NewDistTable_12_5_7,NewDistTable_40_1_39,NewDistTable_13_5_8,DistStation_32,DistStation_40,DistStation_23,DistStation_30,DistStation_29,NewDistTable_17_2_15,NewDistTable_30_2_28,NewDistTable_6_3_3,NewDistTable_36_2_34,NewDistTable_13_1_12,NewDistTable_33_1_32,NewDistTable_27_4_23,NewDistTable_8_3_5,DistStation_14,NewDistTable_22_2_20,NewDistTable_30_4_26,NewDistTable_25_3_22,NewDistTable_17_3_14,NewDistTable_3_1_2,NewDistTable_39_1_38,NewDistTable_37_1_36,DistStation_28,StopTable_1_1,NewDistTable_29_1_28,NewDistTable_29_4_25,NewDistTable_34_3_31,NewDistTable_32_4_28,NewDistTable_15_1_14,NewDistTable_34_2_32,NewDistTable_31_4_27,NewDistTable_22_1_21,NewDistTable_33_5_28,NewDistTable_32_5_27,NewDistTable_23_1_22,NewDistTable_25_5_20,NewDistTable_32_1_31,NewDistTable_38_2_36,NewDistTable_12_1_11,NewDistTable_14_5_9,NewDistTable_33_3_30,NewDistTable_33_2_31,NewDistTable_27_3_24,StopTable_5_15,NewDistTable_20_3_17,NewDistTable_29_3_26,DistStation_31,NewDistTable_5_1_4,NewDistTable_15_3_12,NewDistTable_22_3_19,NewDistTable_11_1_10,NewDistTable_37_2_35,NewDistTable_19_1_18,NewDistTable_18_4_14,
Mar 25, 2019 8:12:04 PM fr.lip6.move.gal.instantiate.Simplifier simplifyConstantVariables
INFO: Removed 210 constant variables :NewDistTable_39_3_36=1, NewDistTable_35_3_32=1, NewDistTable_8_2_6=1, NewDistTable_18_3_15=1, NewDistTable_31_2_29=1, NewDistTable_19_2_17=1, NewDistTable_14_3_11=1, NewDistTable_28_1_27=1, NewDistTable_17_5_12=1, NewDistTable_13_3_10=1, NewDistTable_7_4_3=1, DistStation_6=1, NewDistTable_9_1_8=1, NewDistTable_24_4_20=1, NewDistTable_27_5_22=1, NewDistTable_14_4_10=1, NewDistTable_21_3_18=1, NewDistTable_8_1_7=1, NewDistTable_34_5_29=1, NewDistTable_7_3_4=1, DistStation_33=1, NewDistTable_20_4_16=1, NewDistTable_26_4_22=1, DistStation_24=1, NewDistTable_9_2_7=1, NewDistTable_11_5_6=1, NewDistTable_2_1_1=1, NewDistTable_12_3_9=1, NewDistTable_24_5_19=1, NewDistTable_36_4_32=1, NewDistTable_14_1_13=1, NewDistTable_28_2_26=1, DistStation_34=1, DistStation_19=1, NewDistTable_2_2_0=1, NewDistTable_21_4_17=1, NewDistTable_37_4_33=1, NewDistTable_30_3_27=1, DistStation_20=1, NewDistTable_18_2_16=1, DistStation_38=1, NewDistTable_20_5_15=1, NewDistTable_30_5_25=1, NewDistTable_30_1_29=1, DistStation_15=1, NewDistTable_26_1_25=1, NewDistTable_21_2_19=1, DistStation_9=1, DistStation_7=1, DistStation_10=1, NewDistTable_35_4_31=1, NewDistTable_6_1_5=1, NewDistTable_24_2_22=1, NewDistTable_8_4_4=1, NewDistTable_36_1_35=1, NewDistTable_24_1_23=1, NewDistTable_16_1_15=1, DistStation_22=1, NewDistTable_34_1_33=1, StopTable_3_6=1, NewDistTable_9_3_6=1, NewDistTable_15_2_13=1, NewDistTable_19_3_16=1, NewDistTable_21_1_20=1, NewDistTable_16_5_11=1, NewDistTable_11_2_9=1, DistStation_35=1, StopTable_4_10=1, NewDistTable_20_1_19=1, NewDistTable_38_1_37=1, NewDistTable_21_5_16=1, NewDistTable_15_4_11=1, DistStation_8=1, NewDistTable_10_4_6=1, NewDistTable_32_2_30=1, NewDistTable_11_4_7=1, DistStation_26=1, NewDistTable_22_5_17=1, NewDistTable_27_1_26=1, DistStation_16=1, NewDistTable_24_3_21=1, NewDistTable_16_3_13=1, NewDistTable_17_4_13=1, DistStation_25=1, NewDistTable_4_2_2=1, NewDistTable_6_2_4=1, DistStation_18=1, NewDistTable_3_2_1=1, NewDistTable_26_3_23=1, NewDistTable_36_3_33=1, NewDistTable_38_3_35=1, NewDistTable_10_2_8=1, DistStation_21=1, NewDistTable_28_5_23=1, DistStation_37=1, NewDistTable_5_2_3=1, NewDistTable_7_2_5=1, NewDistTable_26_5_21=1, NewDistTable_19_5_14=1, DistStation_12=1, DistStation_17=1, NewDistTable_19_4_15=1, NewDistTable_22_4_18=1, NewDistTable_25_1_24=1, NewDistTable_18_5_13=1, NewDistTable_17_1_16=1, NewDistTable_4_1_3=1, NewDistTable_13_2_11=1, NewDistTable_14_2_12=1, NewDistTable_32_3_29=1, NewDistTable_7_1_6=1, NewDistTable_13_4_9=1, NewDistTable_16_4_12=1, NewDistTable_20_2_18=1, NewDistTable_11_3_8=1, NewDistTable_15_5_10=1, NewDistTable_31_1_30=1, NewDistTable_9_4_5=1, DistStation_11=1, NewDistTable_31_5_26=1, NewDistTable_5_3_2=1, DistStation_27=1, NewDistTable_10_3_7=1, NewDistTable_29_2_27=1, NewDistTable_10_1_9=1, NewDistTable_34_4_30=1, NewDistTable_23_2_21=1, NewDistTable_12_2_10=1, DistStation_13=1, NewDistTable_29_5_24=1, NewDistTable_35_2_33=1, NewDistTable_33_4_29=1, NewDistTable_26_2_24=1, DistStation_39=1, DistStation_36=1, NewDistTable_25_2_23=1, NewDistTable_23_5_18=1, NewDistTable_12_4_8=1, NewDistTable_25_4_21=1, DistStation_5=1, NewDistTable_16_2_14=1, NewDistTable_27_2_25=1, NewDistTable_28_4_24=1, NewDistTable_35_1_34=1, NewDistTable_37_3_34=1, NewDistTable_31_3_28=1, NewDistTable_23_4_19=1, NewDistTable_23_3_20=1, NewDistTable_18_1_17=1, NewDistTable_4_3_1=1, NewDistTable_40_2_38=1, NewDistTable_28_3_25=1, StopTable_2_3=1, NewDistTable_39_2_37=1, NewDistTable_12_5_7=1, NewDistTable_40_1_39=1, NewDistTable_13_5_8=1, DistStation_32=1, DistStation_40=1, DistStation_23=1, DistStation_30=1, DistStation_29=1, NewDistTable_17_2_15=1, NewDistTable_30_2_28=1, NewDistTable_6_3_3=1, NewDistTable_36_2_34=1, NewDistTable_13_1_12=1, NewDistTable_33_1_32=1, NewDistTable_27_4_23=1, NewDistTable_8_3_5=1, DistStation_14=1, NewDistTable_22_2_20=1, NewDistTable_30_4_26=1, NewDistTable_25_3_22=1, NewDistTable_17_3_14=1, NewDistTable_3_1_2=1, NewDistTable_39_1_38=1, NewDistTable_37_1_36=1, DistStation_28=1, StopTable_1_1=1, NewDistTable_29_1_28=1, NewDistTable_29_4_25=1, NewDistTable_34_3_31=1, NewDistTable_32_4_28=1, NewDistTable_15_1_14=1, NewDistTable_34_2_32=1, NewDistTable_31_4_27=1, NewDistTable_22_1_21=1, NewDistTable_33_5_28=1, NewDistTable_32_5_27=1, NewDistTable_23_1_22=1, NewDistTable_25_5_20=1, NewDistTable_32_1_31=1, NewDistTable_38_2_36=1, NewDistTable_12_1_11=1, NewDistTable_14_5_9=1, NewDistTable_33_3_30=1, NewDistTable_33_2_31=1, NewDistTable_27_3_24=1, StopTable_5_15=1, NewDistTable_20_3_17=1, NewDistTable_29_3_26=1, DistStation_31=1, NewDistTable_5_1_4=1, NewDistTable_15_3_12=1, NewDistTable_22_3_19=1, NewDistTable_11_1_10=1, NewDistTable_37_2_35=1, NewDistTable_19_1_18=1, NewDistTable_18_4_14=1
Mar 25, 2019 8:12:04 PM fr.lip6.move.gal.instantiate.Simplifier simplifyConstantVariables
INFO: Simplified 3110 expressions due to constant valuations.
Mar 25, 2019 8:12:04 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 379 ms
Mar 25, 2019 8:12:04 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 38 ms
Mar 25, 2019 8:12:04 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 1 ms
Mar 25, 2019 8:12:04 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1010 transitions.
Mar 25, 2019 8:12:05 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 5 place invariants in 244 ms
Mar 25, 2019 8:12:06 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 660 variables to be positive in 1262 ms
Mar 25, 2019 8:12:06 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 1010 transitions.
Mar 25, 2019 8:12:06 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/1010 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 25, 2019 8:12:06 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 92 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 25, 2019 8:12:06 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 1010 transitions.
Mar 25, 2019 8:12:06 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 52 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 25, 2019 8:12:07 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 1010 transitions.
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown' twice, overapproximating result to 1.
Mar 25, 2019 8:12:09 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 1677 ms. Total solver calls (SAT/UNSAT): 1206(36/1170)
Mar 25, 2019 8:12:09 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 1010 transitions.
Mar 25, 2019 8:12:12 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 3120 ms. Total solver calls (SAT/UNSAT): 1718(0/1718)
Mar 25, 2019 8:12:12 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 8235ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BART-PT-005"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3954"
echo " Executing tool itstools"
echo " Input is BART-PT-005, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r184-csrt-155344537500016"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/BART-PT-005.tgz
mv BART-PT-005 execution
cd execution
if [ "LTLFireability" = "GlobalProperties" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
if [ "LTLFireability" = "UpperBounds" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;