About the Execution of ITS-Tools for BART-PT-005
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
2501.580 | 214935.00 | 221772.00 | 131.30 | FFTTFTTFFTFTTTTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/local/x2003239/mcc2019-input.r184-csrt-155344537500014.qcow2', fmt=qcow2 size=4294967296 backing_file=/local/x2003239/mcc2019-input.qcow2 encryption=off cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................
=====================================================================
Generated by BenchKit 2-3954
Executing tool itstools
Input is BART-PT-005, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r184-csrt-155344537500014
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.4M
-rw-r--r-- 1 mcc users 3.4K Mar 10 19:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 16K Mar 10 19:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 3.5K Mar 10 19:08 CTLFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 10 19:08 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 10 17:46 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K Mar 10 17:46 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.5K Mar 10 19:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 9.9K Mar 10 19:07 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Mar 10 19:07 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.8K Mar 10 19:07 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Mar 10 17:46 NewModel
-rw-r--r-- 1 mcc users 3.6K Mar 10 19:04 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 14K Mar 10 19:04 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 102 Mar 10 18:58 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 340 Mar 10 18:58 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 3.5K Mar 10 18:59 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 15K Mar 10 18:59 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Mar 10 19:07 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Mar 10 19:07 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 10 17:46 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 10 17:46 instance
-rw-r--r-- 1 mcc users 6 Mar 10 17:46 iscolored
-rw-r--r-- 1 mcc users 1.2M Mar 10 17:46 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME BART-PT-005-CTLFireability-00
FORMULA_NAME BART-PT-005-CTLFireability-01
FORMULA_NAME BART-PT-005-CTLFireability-02
FORMULA_NAME BART-PT-005-CTLFireability-03
FORMULA_NAME BART-PT-005-CTLFireability-04
FORMULA_NAME BART-PT-005-CTLFireability-05
FORMULA_NAME BART-PT-005-CTLFireability-06
FORMULA_NAME BART-PT-005-CTLFireability-07
FORMULA_NAME BART-PT-005-CTLFireability-08
FORMULA_NAME BART-PT-005-CTLFireability-09
FORMULA_NAME BART-PT-005-CTLFireability-10
FORMULA_NAME BART-PT-005-CTLFireability-11
FORMULA_NAME BART-PT-005-CTLFireability-12
FORMULA_NAME BART-PT-005-CTLFireability-13
FORMULA_NAME BART-PT-005-CTLFireability-14
FORMULA_NAME BART-PT-005-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1553544720557
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903171603/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/CTLFireability.pnml.gal, -t, CGAL, -ctl, /home/mcc/execution/CTLFireability.ctl], workingDir=/home/mcc/execution]
its-ctl command run as :
/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903171603/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/CTLFireability.pnml.gal -t CGAL -ctl /home/mcc/execution/CTLFireability.ctl
No direction supplied, using forward translation only.
Parsed 16 CTL formulae.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,4.00746e+10,8.25223,190604,2,20712,5,1.21389e+06,6,0,3653,884823,0
Converting to forward existential form...Done !
original formula: AG(A(((TrainState_3_3_29>=1)&&(TrainState_4_0_0>=1)) U !((TrainState_2_3_35>=1))))
=> equivalent forward existential formula: ([(FwdU(FwdU(Init,TRUE),!(!((TrainState_2_3_35>=1)))) * (!(((TrainState_3_3_29>=1)&&(TrainState_4_0_0>=1))) * !(!((TrainState_2_3_35>=1)))))] = FALSE * [FwdG(FwdU(Init,TRUE),!(!((TrainState_2_3_35>=1))))] = FALSE)
Hit Full ! (commute/partial/dont) 1008/0/2
(forward)formula 0,0,40.1595,811868,1,0,6,4.84586e+06,19,0,15742,884823,8
FORMULA BART-PT-005-CTLFireability-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !
***************************************
original formula: (((AF((TrainState_1_1_10>=1)) + AG((TrainState_5_0_0>=1))) * EF(EG((TrainState_2_1_35>=1)))) + !(E(((TrainState_4_0_0>=1)||(TrainState_1_1_6>=1)) U !((TrainState_2_1_36>=1)))))
=> equivalent forward existential formula: [(FwdU((Init * !(((!(EG(!((TrainState_1_1_10>=1)))) + !(E(TRUE U !((TrainState_5_0_0>=1))))) * E(TRUE U EG((TrainState_2_1_35>=1)))))),((TrainState_4_0_0>=1)||(TrainState_1_1_6>=1))) * !((TrainState_2_1_36>=1)))] = FALSE
Reverse transition relation is exact ! Faster fixpoint algorithm enabled.
Hit Full ! (commute/partial/dont) 969/0/41
(forward)formula 1,0,50.1992,1050788,1,0,16,6.68551e+06,49,6,18305,1.65252e+06,21
FORMULA BART-PT-005-CTLFireability-01 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !
***************************************
original formula: E((((!(TrainState_4_2_29>=1))||((TrainState_2_0_0>=1)&&(TrainState_1_4_13>=1)))&&(((TrainState_5_0_0>=1)||(TrainState_4_1_26>=1))&&((TrainState_5_1_8>=1)||(TrainState_4_1_21>=1)))) U EF(((TrainState_5_1_23>=1)&&(TrainState_1_4_34>=1))))
=> equivalent forward existential formula: [(FwdU(FwdU(Init,(((!(TrainState_4_2_29>=1))||((TrainState_2_0_0>=1)&&(TrainState_1_4_13>=1)))&&(((TrainState_5_0_0>=1)||(TrainState_4_1_26>=1))&&((TrainState_5_1_8>=1)||(TrainState_4_1_21>=1))))),TRUE) * ((TrainState_5_1_23>=1)&&(TrainState_1_4_34>=1)))] != FALSE
Hit Full ! (commute/partial/dont) 920/58/90
(forward)formula 2,1,56.1122,1125236,1,0,19,7.11473e+06,58,7,18376,2.11914e+06,27
FORMULA BART-PT-005-CTLFireability-02 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !
***************************************
original formula: (EF((TrainState_4_4_26>=1)) + AX(AG((TrainState_1_1_34>=1))))
=> equivalent forward existential formula: [(FwdU(EY((Init * !(E(TRUE U (TrainState_4_4_26>=1))))),TRUE) * !((TrainState_1_1_34>=1)))] = FALSE
(forward)formula 3,1,56.7767,1146620,1,0,23,7.25652e+06,61,8,18377,2.16914e+06,31
FORMULA BART-PT-005-CTLFireability-03 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !
***************************************
original formula: AG(!((((!(TrainState_4_1_13>=1))||(TrainState_1_1_38>=1)) * AF((TrainState_1_4_22>=1)))))
=> equivalent forward existential formula: [((FwdU(Init,TRUE) * ((!(TrainState_4_1_13>=1))||(TrainState_1_1_38>=1))) * !(EG(!((TrainState_1_4_22>=1)))))] = FALSE
(forward)formula 4,0,57.9379,1185428,1,0,27,7.54463e+06,70,11,18383,2.27324e+06,34
FORMULA BART-PT-005-CTLFireability-04 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !
***************************************
original formula: A((TrainState_2_4_30>=1) U EF((TrainState_3_3_32>=1)))
=> equivalent forward existential formula: [((Init * !(EG(!(E(TRUE U (TrainState_3_3_32>=1)))))) * !(E(!(E(TRUE U (TrainState_3_3_32>=1))) U (!((TrainState_2_4_30>=1)) * !(E(TRUE U (TrainState_3_3_32>=1)))))))] != FALSE
(forward)formula 5,1,58.6414,1204700,1,0,28,7.68859e+06,78,12,18386,2.31977e+06,37
FORMULA BART-PT-005-CTLFireability-05 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !
***************************************
original formula: EF((TrainState_1_3_10>=1))
=> equivalent forward existential formula: [(FwdU(Init,TRUE) * (TrainState_1_3_10>=1))] != FALSE
(forward)formula 6,1,58.6582,1204700,1,0,30,7.68915e+06,79,13,18386,2.32872e+06,38
FORMULA BART-PT-005-CTLFireability-06 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !
***************************************
original formula: AF(((((!(TrainState_1_1_30>=1))||((TrainState_4_0_0>=1)||(TrainState_1_1_9>=1))) * EX((TrainState_3_3_26>=1))) + EG((TrainState_2_2_24>=1))))
=> equivalent forward existential formula: [FwdG(Init,!(((((!(TrainState_1_1_30>=1))||((TrainState_4_0_0>=1)||(TrainState_1_1_9>=1))) * EX((TrainState_3_3_26>=1))) + EG((TrainState_2_2_24>=1)))))] = FALSE
(forward)formula 7,0,160.117,2210392,1,0,71,1.43675e+07,10,47,9931,7.92221e+06,24
FORMULA BART-PT-005-CTLFireability-07 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !
***************************************
original formula: ((EX(((TrainState_2_3_21>=1)||(TrainState_2_0_0>=1))) + (AX((TrainState_1_3_15>=1)) * EF((TrainState_3_0_0>=1)))) * AG(!((TrainState_1_3_37>=1))))
=> equivalent forward existential formula: (([(EY((Init * !(EX(((TrainState_2_3_21>=1)||(TrainState_2_0_0>=1)))))) * !((TrainState_1_3_15>=1)))] = FALSE * [((Init * !(EX(((TrainState_2_3_21>=1)||(TrainState_2_0_0>=1))))) * !(E(TRUE U (TrainState_3_0_0>=1))))] = FALSE) * [(FwdU(Init,TRUE) * (TrainState_1_3_37>=1))] = FALSE)
(forward)formula 8,0,160.119,2210392,1,0,71,1.43675e+07,11,47,9931,7.92221e+06,25
FORMULA BART-PT-005-CTLFireability-08 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !
***************************************
original formula: !(AG(!(((TrainState_3_3_10>=1)&&(TrainState_4_2_5>=1)))))
=> equivalent forward existential formula: [(FwdU(Init,TRUE) * ((TrainState_3_3_10>=1)&&(TrainState_4_2_5>=1)))] != FALSE
(forward)formula 9,1,160.156,2210392,1,0,71,1.43675e+07,12,47,9932,7.92221e+06,26
FORMULA BART-PT-005-CTLFireability-09 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !
***************************************
original formula: A((!(((TrainState_1_1_13>=1)&&(TrainState_1_1_32>=1))) + AX((TrainState_2_1_15>=1))) U ((TrainState_4_1_18>=1)||(!(TrainState_1_0_0>=1))))
=> equivalent forward existential formula: [((Init * !(EG(!(((TrainState_4_1_18>=1)||(!(TrainState_1_0_0>=1))))))) * !(E(!(((TrainState_4_1_18>=1)||(!(TrainState_1_0_0>=1)))) U (!((!(((TrainState_1_1_13>=1)&&(TrainState_1_1_32>=1))) + !(EX(!((TrainState_2_1_15>=1)))))) * !(((TrainState_4_1_18>=1)||(!(TrainState_1_0_0>=1))))))))] != FALSE
(forward)formula 10,0,168.028,2210392,1,0,71,1.43675e+07,24,47,11456,7.92221e+06,32
FORMULA BART-PT-005-CTLFireability-10 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !
***************************************
original formula: AX(EG(!((TrainState_1_3_18>=1))))
=> equivalent forward existential formula: [(EY(Init) * !(EG(!((TrainState_1_3_18>=1)))))] = FALSE
(forward)formula 11,1,170.993,2210392,1,0,71,1.43675e+07,32,47,11460,7.92221e+06,35
FORMULA BART-PT-005-CTLFireability-11 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !
***************************************
original formula: EF((EG(((TrainState_1_3_11>=1)&&(TrainState_2_2_33>=1))) * (TrainState_4_0_0>=1)))
=> equivalent forward existential formula: [FwdG((FwdU(Init,TRUE) * (TrainState_4_0_0>=1)),((TrainState_1_3_11>=1)&&(TrainState_2_2_33>=1)))] != FALSE
Hit Full ! (commute/partial/dont) 1005/5/5
(forward)formula 12,1,172.421,2210392,1,0,71,1.43675e+07,40,47,12777,7.92221e+06,40
FORMULA BART-PT-005-CTLFireability-12 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !
***************************************
original formula: EG((((!(TrainState_4_0_0>=1))||(TrainState_4_0_0>=1)) + AG((TrainState_4_1_10>=1))))
=> equivalent forward existential formula: [FwdG(Init,(((!(TrainState_4_0_0>=1))||(TrainState_4_0_0>=1)) + !(E(TRUE U !((TrainState_4_1_10>=1))))))] != FALSE
(forward)formula 13,1,178.186,2210392,1,0,71,1.43675e+07,51,47,15256,7.92221e+06,47
FORMULA BART-PT-005-CTLFireability-13 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !
***************************************
original formula: EG(!((TrainState_2_1_6>=1)))
=> equivalent forward existential formula: [FwdG(Init,!((TrainState_2_1_6>=1)))] != FALSE
Hit Full ! (commute/partial/dont) 1006/0/4
(forward)formula 14,1,182.005,2210392,1,0,71,1.43675e+07,59,47,16468,7.92221e+06,51
FORMULA BART-PT-005-CTLFireability-14 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !
***************************************
original formula: A(A((TrainState_3_4_34>=1) U (TrainState_5_1_13>=1)) U !(AF((TrainState_1_3_14>=1))))
=> equivalent forward existential formula: [((Init * !(EG(!(!(!(EG(!((TrainState_1_3_14>=1))))))))) * !(E(!(!(!(EG(!((TrainState_1_3_14>=1)))))) U (!(!((E(!((TrainState_5_1_13>=1)) U (!((TrainState_3_4_34>=1)) * !((TrainState_5_1_13>=1)))) + EG(!((TrainState_5_1_13>=1)))))) * !(!(!(EG(!((TrainState_1_3_14>=1))))))))))] != FALSE
Hit Full ! (commute/partial/dont) 1006/0/4
Using saturation style SCC detection
(forward)formula 15,1,210.773,2219364,1,0,71,1.55108e+07,85,47,18737,7.92221e+06,64
FORMULA BART-PT-005-CTLFireability-15 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !
***************************************
BK_STOP 1553544935492
--------------------
content from stderr:
+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ CTLFireability = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution CTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination CTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Mar 25, 2019 8:12:02 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Mar 25, 2019 8:12:02 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Mar 25, 2019 8:12:02 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 177 ms
Mar 25, 2019 8:12:02 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 870 places.
Mar 25, 2019 8:12:02 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 1010 transitions.
Mar 25, 2019 8:12:03 PM fr.lip6.move.gal.instantiate.DomainAnalyzer computeVariableDomains
INFO: Found a total of 210 fixed domain variables (out of 870 variables) in GAL type BART_PT_005
Mar 25, 2019 8:12:03 PM fr.lip6.move.gal.instantiate.Simplifier printConstantVars
INFO: Found a total of 210 constant array cells/variables (out of 870 variables) in type BART_PT_005
Mar 25, 2019 8:12:03 PM fr.lip6.move.gal.instantiate.Simplifier printConstantVars
INFO: NewDistTable_39_3_36,NewDistTable_35_3_32,NewDistTable_8_2_6,NewDistTable_18_3_15,NewDistTable_31_2_29,NewDistTable_19_2_17,NewDistTable_14_3_11,NewDistTable_28_1_27,NewDistTable_17_5_12,NewDistTable_13_3_10,NewDistTable_7_4_3,DistStation_6,NewDistTable_9_1_8,NewDistTable_24_4_20,NewDistTable_27_5_22,NewDistTable_14_4_10,NewDistTable_21_3_18,NewDistTable_8_1_7,NewDistTable_34_5_29,NewDistTable_7_3_4,DistStation_33,NewDistTable_20_4_16,NewDistTable_26_4_22,DistStation_24,NewDistTable_9_2_7,NewDistTable_11_5_6,NewDistTable_2_1_1,NewDistTable_12_3_9,NewDistTable_24_5_19,NewDistTable_36_4_32,NewDistTable_14_1_13,NewDistTable_28_2_26,DistStation_34,DistStation_19,NewDistTable_2_2_0,NewDistTable_21_4_17,NewDistTable_37_4_33,NewDistTable_30_3_27,DistStation_20,NewDistTable_18_2_16,DistStation_38,NewDistTable_20_5_15,NewDistTable_30_5_25,NewDistTable_30_1_29,DistStation_15,NewDistTable_26_1_25,NewDistTable_21_2_19,DistStation_9,DistStation_7,DistStation_10,NewDistTable_35_4_31,NewDistTable_6_1_5,NewDistTable_24_2_22,NewDistTable_8_4_4,NewDistTable_36_1_35,NewDistTable_24_1_23,NewDistTable_16_1_15,DistStation_22,NewDistTable_34_1_33,StopTable_3_6,NewDistTable_9_3_6,NewDistTable_15_2_13,NewDistTable_19_3_16,NewDistTable_21_1_20,NewDistTable_16_5_11,NewDistTable_11_2_9,DistStation_35,StopTable_4_10,NewDistTable_20_1_19,NewDistTable_38_1_37,NewDistTable_21_5_16,NewDistTable_15_4_11,DistStation_8,NewDistTable_10_4_6,NewDistTable_32_2_30,NewDistTable_11_4_7,DistStation_26,NewDistTable_22_5_17,NewDistTable_27_1_26,DistStation_16,NewDistTable_24_3_21,NewDistTable_16_3_13,NewDistTable_17_4_13,DistStation_25,NewDistTable_4_2_2,NewDistTable_6_2_4,DistStation_18,NewDistTable_3_2_1,NewDistTable_26_3_23,NewDistTable_36_3_33,NewDistTable_38_3_35,NewDistTable_10_2_8,DistStation_21,NewDistTable_28_5_23,DistStation_37,NewDistTable_5_2_3,NewDistTable_7_2_5,NewDistTable_26_5_21,NewDistTable_19_5_14,DistStation_12,DistStation_17,NewDistTable_19_4_15,NewDistTable_22_4_18,NewDistTable_25_1_24,NewDistTable_18_5_13,NewDistTable_17_1_16,NewDistTable_4_1_3,NewDistTable_13_2_11,NewDistTable_14_2_12,NewDistTable_32_3_29,NewDistTable_7_1_6,NewDistTable_13_4_9,NewDistTable_16_4_12,NewDistTable_20_2_18,NewDistTable_11_3_8,NewDistTable_15_5_10,NewDistTable_31_1_30,NewDistTable_9_4_5,DistStation_11,NewDistTable_31_5_26,NewDistTable_5_3_2,DistStation_27,NewDistTable_10_3_7,NewDistTable_29_2_27,NewDistTable_10_1_9,NewDistTable_34_4_30,NewDistTable_23_2_21,NewDistTable_12_2_10,DistStation_13,NewDistTable_29_5_24,NewDistTable_35_2_33,NewDistTable_33_4_29,NewDistTable_26_2_24,DistStation_39,DistStation_36,NewDistTable_25_2_23,NewDistTable_23_5_18,NewDistTable_12_4_8,NewDistTable_25_4_21,DistStation_5,NewDistTable_16_2_14,NewDistTable_27_2_25,NewDistTable_28_4_24,NewDistTable_35_1_34,NewDistTable_37_3_34,NewDistTable_31_3_28,NewDistTable_23_4_19,NewDistTable_23_3_20,NewDistTable_18_1_17,NewDistTable_4_3_1,NewDistTable_40_2_38,NewDistTable_28_3_25,StopTable_2_3,NewDistTable_39_2_37,NewDistTable_12_5_7,NewDistTable_40_1_39,NewDistTable_13_5_8,DistStation_32,DistStation_40,DistStation_23,DistStation_30,DistStation_29,NewDistTable_17_2_15,NewDistTable_30_2_28,NewDistTable_6_3_3,NewDistTable_36_2_34,NewDistTable_13_1_12,NewDistTable_33_1_32,NewDistTable_27_4_23,NewDistTable_8_3_5,DistStation_14,NewDistTable_22_2_20,NewDistTable_30_4_26,NewDistTable_25_3_22,NewDistTable_17_3_14,NewDistTable_3_1_2,NewDistTable_39_1_38,NewDistTable_37_1_36,DistStation_28,StopTable_1_1,NewDistTable_29_1_28,NewDistTable_29_4_25,NewDistTable_34_3_31,NewDistTable_32_4_28,NewDistTable_15_1_14,NewDistTable_34_2_32,NewDistTable_31_4_27,NewDistTable_22_1_21,NewDistTable_33_5_28,NewDistTable_32_5_27,NewDistTable_23_1_22,NewDistTable_25_5_20,NewDistTable_32_1_31,NewDistTable_38_2_36,NewDistTable_12_1_11,NewDistTable_14_5_9,NewDistTable_33_3_30,NewDistTable_33_2_31,NewDistTable_27_3_24,StopTable_5_15,NewDistTable_20_3_17,NewDistTable_29_3_26,DistStation_31,NewDistTable_5_1_4,NewDistTable_15_3_12,NewDistTable_22_3_19,NewDistTable_11_1_10,NewDistTable_37_2_35,NewDistTable_19_1_18,NewDistTable_18_4_14,
Mar 25, 2019 8:12:03 PM fr.lip6.move.gal.instantiate.Simplifier simplifyConstantVariables
INFO: Removed 210 constant variables :NewDistTable_39_3_36=1, NewDistTable_35_3_32=1, NewDistTable_8_2_6=1, NewDistTable_18_3_15=1, NewDistTable_31_2_29=1, NewDistTable_19_2_17=1, NewDistTable_14_3_11=1, NewDistTable_28_1_27=1, NewDistTable_17_5_12=1, NewDistTable_13_3_10=1, NewDistTable_7_4_3=1, DistStation_6=1, NewDistTable_9_1_8=1, NewDistTable_24_4_20=1, NewDistTable_27_5_22=1, NewDistTable_14_4_10=1, NewDistTable_21_3_18=1, NewDistTable_8_1_7=1, NewDistTable_34_5_29=1, NewDistTable_7_3_4=1, DistStation_33=1, NewDistTable_20_4_16=1, NewDistTable_26_4_22=1, DistStation_24=1, NewDistTable_9_2_7=1, NewDistTable_11_5_6=1, NewDistTable_2_1_1=1, NewDistTable_12_3_9=1, NewDistTable_24_5_19=1, NewDistTable_36_4_32=1, NewDistTable_14_1_13=1, NewDistTable_28_2_26=1, DistStation_34=1, DistStation_19=1, NewDistTable_2_2_0=1, NewDistTable_21_4_17=1, NewDistTable_37_4_33=1, NewDistTable_30_3_27=1, DistStation_20=1, NewDistTable_18_2_16=1, DistStation_38=1, NewDistTable_20_5_15=1, NewDistTable_30_5_25=1, NewDistTable_30_1_29=1, DistStation_15=1, NewDistTable_26_1_25=1, NewDistTable_21_2_19=1, DistStation_9=1, DistStation_7=1, DistStation_10=1, NewDistTable_35_4_31=1, NewDistTable_6_1_5=1, NewDistTable_24_2_22=1, NewDistTable_8_4_4=1, NewDistTable_36_1_35=1, NewDistTable_24_1_23=1, NewDistTable_16_1_15=1, DistStation_22=1, NewDistTable_34_1_33=1, StopTable_3_6=1, NewDistTable_9_3_6=1, NewDistTable_15_2_13=1, NewDistTable_19_3_16=1, NewDistTable_21_1_20=1, NewDistTable_16_5_11=1, NewDistTable_11_2_9=1, DistStation_35=1, StopTable_4_10=1, NewDistTable_20_1_19=1, NewDistTable_38_1_37=1, NewDistTable_21_5_16=1, NewDistTable_15_4_11=1, DistStation_8=1, NewDistTable_10_4_6=1, NewDistTable_32_2_30=1, NewDistTable_11_4_7=1, DistStation_26=1, NewDistTable_22_5_17=1, NewDistTable_27_1_26=1, DistStation_16=1, NewDistTable_24_3_21=1, NewDistTable_16_3_13=1, NewDistTable_17_4_13=1, DistStation_25=1, NewDistTable_4_2_2=1, NewDistTable_6_2_4=1, DistStation_18=1, NewDistTable_3_2_1=1, NewDistTable_26_3_23=1, NewDistTable_36_3_33=1, NewDistTable_38_3_35=1, NewDistTable_10_2_8=1, DistStation_21=1, NewDistTable_28_5_23=1, DistStation_37=1, NewDistTable_5_2_3=1, NewDistTable_7_2_5=1, NewDistTable_26_5_21=1, NewDistTable_19_5_14=1, DistStation_12=1, DistStation_17=1, NewDistTable_19_4_15=1, NewDistTable_22_4_18=1, NewDistTable_25_1_24=1, NewDistTable_18_5_13=1, NewDistTable_17_1_16=1, NewDistTable_4_1_3=1, NewDistTable_13_2_11=1, NewDistTable_14_2_12=1, NewDistTable_32_3_29=1, NewDistTable_7_1_6=1, NewDistTable_13_4_9=1, NewDistTable_16_4_12=1, NewDistTable_20_2_18=1, NewDistTable_11_3_8=1, NewDistTable_15_5_10=1, NewDistTable_31_1_30=1, NewDistTable_9_4_5=1, DistStation_11=1, NewDistTable_31_5_26=1, NewDistTable_5_3_2=1, DistStation_27=1, NewDistTable_10_3_7=1, NewDistTable_29_2_27=1, NewDistTable_10_1_9=1, NewDistTable_34_4_30=1, NewDistTable_23_2_21=1, NewDistTable_12_2_10=1, DistStation_13=1, NewDistTable_29_5_24=1, NewDistTable_35_2_33=1, NewDistTable_33_4_29=1, NewDistTable_26_2_24=1, DistStation_39=1, DistStation_36=1, NewDistTable_25_2_23=1, NewDistTable_23_5_18=1, NewDistTable_12_4_8=1, NewDistTable_25_4_21=1, DistStation_5=1, NewDistTable_16_2_14=1, NewDistTable_27_2_25=1, NewDistTable_28_4_24=1, NewDistTable_35_1_34=1, NewDistTable_37_3_34=1, NewDistTable_31_3_28=1, NewDistTable_23_4_19=1, NewDistTable_23_3_20=1, NewDistTable_18_1_17=1, NewDistTable_4_3_1=1, NewDistTable_40_2_38=1, NewDistTable_28_3_25=1, StopTable_2_3=1, NewDistTable_39_2_37=1, NewDistTable_12_5_7=1, NewDistTable_40_1_39=1, NewDistTable_13_5_8=1, DistStation_32=1, DistStation_40=1, DistStation_23=1, DistStation_30=1, DistStation_29=1, NewDistTable_17_2_15=1, NewDistTable_30_2_28=1, NewDistTable_6_3_3=1, NewDistTable_36_2_34=1, NewDistTable_13_1_12=1, NewDistTable_33_1_32=1, NewDistTable_27_4_23=1, NewDistTable_8_3_5=1, DistStation_14=1, NewDistTable_22_2_20=1, NewDistTable_30_4_26=1, NewDistTable_25_3_22=1, NewDistTable_17_3_14=1, NewDistTable_3_1_2=1, NewDistTable_39_1_38=1, NewDistTable_37_1_36=1, DistStation_28=1, StopTable_1_1=1, NewDistTable_29_1_28=1, NewDistTable_29_4_25=1, NewDistTable_34_3_31=1, NewDistTable_32_4_28=1, NewDistTable_15_1_14=1, NewDistTable_34_2_32=1, NewDistTable_31_4_27=1, NewDistTable_22_1_21=1, NewDistTable_33_5_28=1, NewDistTable_32_5_27=1, NewDistTable_23_1_22=1, NewDistTable_25_5_20=1, NewDistTable_32_1_31=1, NewDistTable_38_2_36=1, NewDistTable_12_1_11=1, NewDistTable_14_5_9=1, NewDistTable_33_3_30=1, NewDistTable_33_2_31=1, NewDistTable_27_3_24=1, StopTable_5_15=1, NewDistTable_20_3_17=1, NewDistTable_29_3_26=1, DistStation_31=1, NewDistTable_5_1_4=1, NewDistTable_15_3_12=1, NewDistTable_22_3_19=1, NewDistTable_11_1_10=1, NewDistTable_37_2_35=1, NewDistTable_19_1_18=1, NewDistTable_18_4_14=1
Mar 25, 2019 8:12:03 PM fr.lip6.move.gal.instantiate.Simplifier simplifyConstantVariables
INFO: Simplified 3219 expressions due to constant valuations.
Mar 25, 2019 8:12:03 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 424 ms
Mar 25, 2019 8:12:03 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/CTLFireability.pnml.gal : 40 ms
Mar 25, 2019 8:12:03 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSCTLTools
INFO: Time to serialize properties into /home/mcc/execution/CTLFireability.ctl : 1 ms
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BART-PT-005"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3954"
echo " Executing tool itstools"
echo " Input is BART-PT-005, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r184-csrt-155344537500014"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/BART-PT-005.tgz
mv BART-PT-005 execution
cd execution
if [ "CTLFireability" = "GlobalProperties" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
if [ "CTLFireability" = "UpperBounds" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;