Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/local/x2003239/mcc2019-input.r184-csrt-155344537500005.qcow2', fmt=qcow2 size=4294967296 backing_file=/local/x2003239/mcc2019-input.qcow2 encryption=off cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................
=====================================================================
Generated by BenchKit 2-3954
Executing tool itstools
Input is BART-PT-002, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r184-csrt-155344537500005
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 688K
-rw-r--r-- 1 mcc users 4.2K Mar 10 19:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 20K Mar 10 19:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 3.5K Mar 10 19:08 CTLFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 10 19:08 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 10 17:46 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K Mar 10 17:46 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.7K Mar 10 19:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K Mar 10 19:07 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Mar 10 19:07 LTLFireability.txt
-rw-r--r-- 1 mcc users 11K Mar 10 19:07 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Mar 10 17:46 NewModel
-rw-r--r-- 1 mcc users 3.9K Mar 10 19:03 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K Mar 10 19:03 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 102 Mar 10 18:58 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 340 Mar 10 18:58 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 4.4K Mar 10 18:59 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 20K Mar 10 18:59 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Mar 10 19:07 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Mar 10 19:07 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 10 17:46 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 10 17:46 instance
-rw-r--r-- 1 mcc users 6 Mar 10 17:46 iscolored
-rw-r--r-- 1 mcc users 506K Mar 10 17:46 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BART-PT-002-CTLFireability-00
FORMULA_NAME BART-PT-002-CTLFireability-01
FORMULA_NAME BART-PT-002-CTLFireability-02
FORMULA_NAME BART-PT-002-CTLFireability-03
FORMULA_NAME BART-PT-002-CTLFireability-04
FORMULA_NAME BART-PT-002-CTLFireability-05
FORMULA_NAME BART-PT-002-CTLFireability-06
FORMULA_NAME BART-PT-002-CTLFireability-07
FORMULA_NAME BART-PT-002-CTLFireability-08
FORMULA_NAME BART-PT-002-CTLFireability-09
FORMULA_NAME BART-PT-002-CTLFireability-10
FORMULA_NAME BART-PT-002-CTLFireability-11
FORMULA_NAME BART-PT-002-CTLFireability-12
FORMULA_NAME BART-PT-002-CTLFireability-13
FORMULA_NAME BART-PT-002-CTLFireability-14
FORMULA_NAME BART-PT-002-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1553544720520

Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903171603/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/CTLFireability.pnml.gal, -t, CGAL, -ctl, /home/mcc/execution/CTLFireability.ctl], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903171603/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/CTLFireability.pnml.gal -t CGAL -ctl /home/mcc/execution/CTLFireability.ctl
No direction supplied, using forward translation only.
Parsed 16 CTL formulae.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,17424,0.206086,9296,2,1046,5,21923,6,0,1463,18180,0


Converting to forward existential form...Done !
original formula: E((TrainState_1_1_19>=1) U EG(!((TrainState_2_2_7>=1))))
=> equivalent forward existential formula: [FwdG(FwdU(Init,(TrainState_1_1_19>=1)),!((TrainState_2_2_7>=1)))] != FALSE
Hit Full ! (commute/partial/dont) 400/0/4
Hit Full ! (commute/partial/dont) 401/0/3
(forward)formula 0,1,0.852684,26740,1,0,7,113460,27,1,6319,35686,11
FORMULA BART-PT-002-CTLFireability-00 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: AG((AF(((TrainState_1_2_4>=1)&&(TrainState_1_3_21>=1))) + (AG((TrainState_1_3_36>=1)) + !(((TrainState_2_0_0>=1)&&(TrainState_1_2_7>=1))))))
=> equivalent forward existential formula: [(FwdU(((FwdU(Init,TRUE) * !(!(EG(!(((TrainState_1_2_4>=1)&&(TrainState_1_3_21>=1))))))) * !(!(((TrainState_2_0_0>=1)&&(TrainState_1_2_7>=1))))),TRUE) * !((TrainState_1_3_36>=1)))] = FALSE
Reverse transition relation is exact ! Faster fixpoint algorithm enabled.
(forward)formula 1,0,0.933771,28588,1,0,11,119134,37,4,6830,44628,17
FORMULA BART-PT-002-CTLFireability-01 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: AF((TrainState_2_1_37>=1))
=> equivalent forward existential formula: [FwdG(Init,!((TrainState_2_1_37>=1)))] = FALSE
Hit Full ! (commute/partial/dont) 400/0/4
(forward)formula 2,0,0.958385,29116,1,0,13,120176,45,5,6957,46392,21
FORMULA BART-PT-002-CTLFireability-02 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: EG(((EX((TrainState_1_1_31>=1)) + AF((TrainState_2_1_39>=1))) + !(AX((TrainState_1_3_35>=1)))))
=> equivalent forward existential formula: [FwdG(Init,((EX((TrainState_1_1_31>=1)) + !(EG(!((TrainState_2_1_39>=1))))) + !(!(EX(!((TrainState_1_3_35>=1)))))))] != FALSE
(forward)formula 3,1,0.983911,30436,1,0,19,129565,56,9,6962,50483,30
FORMULA BART-PT-002-CTLFireability-03 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: !(EX((EX((TrainState_2_1_9>=1)) * EF((TrainState_2_3_19>=1)))))
=> equivalent forward existential formula: [(FwdU((EY(Init) * EX((TrainState_2_1_9>=1))),TRUE) * (TrainState_2_3_19>=1))] = FALSE
(forward)formula 4,0,1.0482,32436,1,0,25,147421,58,11,6962,57403,36
FORMULA BART-PT-002-CTLFireability-04 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: AG(AF((TrainState_1_0_0>=1)))
=> equivalent forward existential formula: [FwdG(FwdU(Init,TRUE),!((TrainState_1_0_0>=1)))] = FALSE
Hit Full ! (commute/partial/dont) 367/0/37
(forward)formula 5,0,1.09775,33492,1,0,26,149548,66,11,7305,61693,40
FORMULA BART-PT-002-CTLFireability-05 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: ((E((TrainState_1_1_8>=1) U ((TrainState_1_1_38>=1)&&(TrainState_1_1_12>=1))) * AX(((TrainState_2_1_30>=1)&&(TrainState_2_3_25>=1)))) + AF((TrainState_2_2_26>=1)))
=> equivalent forward existential formula: [FwdG((Init * !((E((TrainState_1_1_8>=1) U ((TrainState_1_1_38>=1)&&(TrainState_1_1_12>=1))) * !(EX(!(((TrainState_2_1_30>=1)&&(TrainState_2_3_25>=1)))))))),!((TrainState_2_2_26>=1)))] = FALSE
Hit Full ! (commute/partial/dont) 402/0/2
(forward)formula 6,0,1.14199,34548,1,0,28,152005,78,12,7522,66185,45
FORMULA BART-PT-002-CTLFireability-06 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: (AG(((!(TrainState_2_3_9>=1))||((TrainState_1_2_25>=1)||(TrainState_1_3_20>=1)))) + EG((TrainState_1_1_34>=1)))
=> equivalent forward existential formula: [(FwdU((Init * !(EG((TrainState_1_1_34>=1)))),TRUE) * !(((!(TrainState_2_3_9>=1))||((TrainState_1_2_25>=1)||(TrainState_1_3_20>=1)))))] = FALSE
(forward)formula 7,0,1.15867,35076,1,0,33,157504,87,16,7531,69186,48
FORMULA BART-PT-002-CTLFireability-07 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: !(EG(!((TrainState_2_1_18>=1))))
=> equivalent forward existential formula: [FwdG(Init,!((TrainState_2_1_18>=1)))] = FALSE
Hit Full ! (commute/partial/dont) 400/0/4
(forward)formula 8,0,1.23127,36924,1,0,35,163719,95,17,7876,78818,52
FORMULA BART-PT-002-CTLFireability-08 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: (A(AF((TrainState_1_1_1>=1)) U !(((TrainState_1_1_29>=1)&&(TrainState_1_3_34>=1)))) * AG(!(((TrainState_1_0_0>=1)&&(TrainState_1_2_17>=1)))))
=> equivalent forward existential formula: (([FwdG((FwdU(Init,!(!(((TrainState_1_1_29>=1)&&(TrainState_1_3_34>=1))))) * !(!(((TrainState_1_1_29>=1)&&(TrainState_1_3_34>=1))))),!((TrainState_1_1_1>=1)))] = FALSE * [FwdG(Init,!(!(((TrainState_1_1_29>=1)&&(TrainState_1_3_34>=1)))))] = FALSE) * [(FwdU(Init,TRUE) * ((TrainState_1_0_0>=1)&&(TrainState_1_2_17>=1)))] = FALSE)
(forward)formula 9,1,1.23506,37452,1,0,36,164118,109,17,7883,78820,54
FORMULA BART-PT-002-CTLFireability-09 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: (E(((!(TrainState_2_4_21>=1))||((TrainState_1_4_18>=1)||(TrainState_1_1_37>=1))) U AF((TrainState_2_3_11>=1))) + AG((TrainState_1_2_7>=1)))
=> equivalent forward existential formula: [(FwdU((Init * !(E(((!(TrainState_2_4_21>=1))||((TrainState_1_4_18>=1)||(TrainState_1_1_37>=1))) U !(EG(!((TrainState_2_3_11>=1))))))),TRUE) * !((TrainState_1_2_7>=1)))] = FALSE
Hit Full ! (commute/partial/dont) 394/0/10
(forward)formula 10,1,1.50114,44052,1,0,43,217134,126,21,8422,98799,60
FORMULA BART-PT-002-CTLFireability-10 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: E(EX(!((TrainState_1_2_19>=1))) U (EG((TrainState_2_0_0>=1)) * !((TrainState_2_1_1>=1))))
=> equivalent forward existential formula: [FwdG((FwdU(Init,EX(!((TrainState_1_2_19>=1)))) * !((TrainState_2_1_1>=1))),(TrainState_2_0_0>=1))] != FALSE
Hit Full ! (commute/partial/dont) 367/0/37
(forward)formula 11,1,1.59785,46164,1,0,47,230135,137,24,8758,104864,67
FORMULA BART-PT-002-CTLFireability-11 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: EG((AG(((TrainState_2_3_37>=1)||(TrainState_2_4_12>=1))) + !(AX((TrainState_2_1_35>=1)))))
=> equivalent forward existential formula: [FwdG(Init,(!(E(TRUE U !(((TrainState_2_3_37>=1)||(TrainState_2_4_12>=1))))) + !(!(EX(!((TrainState_2_1_35>=1)))))))] != FALSE
(forward)formula 12,1,1.64977,47220,1,0,49,235261,142,24,9036,106726,73
FORMULA BART-PT-002-CTLFireability-12 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: !(A(!(((TrainState_2_4_23>=1)&&(TrainState_1_1_30>=1))) U AX((TrainState_2_0_0>=1))))
=> equivalent forward existential formula: ([(EY((FwdU(Init,!(!(EX(!((TrainState_2_0_0>=1)))))) * !(!(((TrainState_2_4_23>=1)&&(TrainState_1_1_30>=1)))))) * !((TrainState_2_0_0>=1)))] != FALSE + [FwdG(Init,!(!(EX(!((TrainState_2_0_0>=1))))))] != FALSE)
(forward)formula 13,1,1.6743,48276,1,0,53,244451,144,27,9038,110707,77
FORMULA BART-PT-002-CTLFireability-13 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: AF((TrainState_1_3_34>=1))
=> equivalent forward existential formula: [FwdG(Init,!((TrainState_1_3_34>=1)))] = FALSE
Hit Full ! (commute/partial/dont) 402/0/2
(forward)formula 14,0,1.68315,48540,1,0,55,244967,152,28,9087,111471,81
FORMULA BART-PT-002-CTLFireability-14 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: EX(AF((TrainState_1_4_12>=1)))
=> equivalent forward existential formula: [(EY(Init) * !(EG(!((TrainState_1_4_12>=1)))))] != FALSE
(forward)formula 15,0,1.72098,50124,1,0,57,259365,160,30,9091,116445,83
FORMULA BART-PT-002-CTLFireability-15 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************


BK_STOP 1553544725676

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ CTLFireability = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution CTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination CTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Mar 25, 2019 8:12:02 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Mar 25, 2019 8:12:02 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Mar 25, 2019 8:12:02 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 154 ms
Mar 25, 2019 8:12:02 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 474 places.
Mar 25, 2019 8:12:03 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 404 transitions.
Mar 25, 2019 8:12:03 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 49 ms
Mar 25, 2019 8:12:03 PM fr.lip6.move.gal.instantiate.DomainAnalyzer computeVariableDomains
INFO: Found a total of 210 fixed domain variables (out of 474 variables) in GAL type BART_PT_002
Mar 25, 2019 8:12:03 PM fr.lip6.move.gal.instantiate.Simplifier printConstantVars
INFO: Found a total of 210 constant array cells/variables (out of 474 variables) in type BART_PT_002
Mar 25, 2019 8:12:03 PM fr.lip6.move.gal.instantiate.Simplifier printConstantVars
INFO: NewDistTable_36_4_32,StopTable_2_3,NewDistTable_17_3_14,NewDistTable_8_4_4,NewDistTable_27_3_24,NewDistTable_26_1_25,NewDistTable_29_3_26,NewDistTable_7_1_6,DistStation_7,NewDistTable_34_1_33,NewDistTable_14_5_9,NewDistTable_16_5_11,NewDistTable_32_5_27,NewDistTable_39_2_37,DistStation_23,NewDistTable_25_3_22,NewDistTable_15_5_10,NewDistTable_3_2_1,DistStation_24,NewDistTable_20_2_18,NewDistTable_33_5_28,DistStation_37,NewDistTable_22_5_17,NewDistTable_22_4_18,NewDistTable_16_3_13,NewDistTable_34_2_32,DistStation_29,DistStation_31,NewDistTable_28_1_27,NewDistTable_32_2_30,NewDistTable_21_1_20,NewDistTable_39_1_38,NewDistTable_31_4_27,NewDistTable_16_4_12,DistStation_8,NewDistTable_40_1_39,NewDistTable_27_5_22,NewDistTable_23_3_20,DistStation_11,NewDistTable_18_2_16,NewDistTable_31_2_29,NewDistTable_21_2_19,NewDistTable_25_1_24,NewDistTable_32_4_28,NewDistTable_27_2_25,NewDistTable_22_1_21,NewDistTable_14_3_11,DistStation_14,NewDistTable_29_5_24,NewDistTable_8_1_7,DistStation_6,NewDistTable_10_3_7,NewDistTable_3_1_2,NewDistTable_5_1_4,NewDistTable_9_4_5,NewDistTable_33_2_31,NewDistTable_13_4_9,NewDistTable_32_3_29,DistStation_5,NewDistTable_5_3_2,NewDistTable_19_2_17,DistStation_9,NewDistTable_27_1_26,NewDistTable_20_1_19,NewDistTable_22_2_20,NewDistTable_38_2_36,NewDistTable_7_4_3,NewDistTable_40_2_38,NewDistTable_38_3_35,NewDistTable_11_2_9,DistStation_25,NewDistTable_26_5_21,NewDistTable_29_1_28,NewDistTable_17_4_13,NewDistTable_4_1_3,NewDistTable_28_2_26,NewDistTable_15_3_12,NewDistTable_27_4_23,NewDistTable_23_5_18,NewDistTable_15_4_11,NewDistTable_10_4_6,DistStation_10,NewDistTable_35_4_31,DistStation_39,NewDistTable_37_3_34,DistStation_32,NewDistTable_17_5_12,NewDistTable_35_1_34,NewDistTable_6_1_5,NewDistTable_20_4_16,StopTable_4_10,NewDistTable_14_2_12,NewDistTable_37_4_33,NewDistTable_33_4_29,DistStation_18,NewDistTable_14_1_13,NewDistTable_18_1_17,NewDistTable_34_5_29,NewDistTable_29_4_25,DistStation_35,DistStation_19,DistStation_26,NewDistTable_30_4_26,NewDistTable_8_2_6,NewDistTable_13_1_12,DistStation_16,DistStation_33,NewDistTable_33_1_32,NewDistTable_19_4_15,DistStation_30,NewDistTable_21_3_18,NewDistTable_30_2_28,NewDistTable_39_3_36,NewDistTable_23_4_19,NewDistTable_35_2_33,NewDistTable_7_2_5,NewDistTable_18_5_13,NewDistTable_25_2_23,NewDistTable_23_2_21,NewDistTable_26_4_22,NewDistTable_28_3_25,NewDistTable_33_3_30,DistStation_36,NewDistTable_5_2_3,NewDistTable_7_3_4,NewDistTable_11_5_6,NewDistTable_20_5_15,NewDistTable_24_3_21,NewDistTable_30_1_29,NewDistTable_9_1_8,NewDistTable_37_1_36,NewDistTable_16_2_14,NewDistTable_35_3_32,NewDistTable_20_3_17,NewDistTable_21_4_17,NewDistTable_30_3_27,NewDistTable_26_2_24,StopTable_1_1,DistStation_20,NewDistTable_14_4_10,NewDistTable_8_3_5,NewDistTable_13_3_10,NewDistTable_34_4_30,NewDistTable_10_2_8,NewDistTable_23_1_22,DistStation_38,NewDistTable_19_3_16,NewDistTable_36_2_34,NewDistTable_12_2_10,NewDistTable_21_5_16,StopTable_5_15,NewDistTable_38_1_37,NewDistTable_18_3_15,NewDistTable_2_1_1,NewDistTable_29_2_27,DistStation_17,NewDistTable_12_1_11,DistStation_34,NewDistTable_12_4_8,DistStation_13,NewDistTable_30_5_25,DistStation_40,NewDistTable_36_1_35,NewDistTable_6_3_3,NewDistTable_36_3_33,NewDistTable_18_4_14,NewDistTable_4_3_1,NewDistTable_25_5_20,NewDistTable_32_1_31,NewDistTable_24_2_22,NewDistTable_28_4_24,NewDistTable_16_1_15,NewDistTable_31_3_28,NewDistTable_9_2_7,NewDistTable_9_3_6,NewDistTable_12_3_9,NewDistTable_19_1_18,NewDistTable_24_4_20,NewDistTable_24_1_23,NewDistTable_15_1_14,NewDistTable_24_5_19,DistStation_22,NewDistTable_11_1_10,NewDistTable_17_1_16,NewDistTable_26_3_23,NewDistTable_28_5_23,DistStation_28,NewDistTable_31_5_26,NewDistTable_15_2_13,NewDistTable_11_3_8,DistStation_27,NewDistTable_22_3_19,NewDistTable_37_2_35,NewDistTable_34_3_31,NewDistTable_4_2_2,NewDistTable_6_2_4,NewDistTable_2_2_0,NewDistTable_17_2_15,NewDistTable_13_2_11,DistStation_15,DistStation_21,NewDistTable_31_1_30,DistStation_12,NewDistTable_10_1_9,NewDistTable_11_4_7,NewDistTable_12_5_7,NewDistTable_13_5_8,StopTable_3_6,NewDistTable_19_5_14,NewDistTable_25_4_21,
Mar 25, 2019 8:12:03 PM fr.lip6.move.gal.instantiate.Simplifier simplifyConstantVariables
INFO: Removed 210 constant variables :NewDistTable_36_4_32=1, StopTable_2_3=1, NewDistTable_17_3_14=1, NewDistTable_8_4_4=1, NewDistTable_27_3_24=1, NewDistTable_26_1_25=1, NewDistTable_29_3_26=1, NewDistTable_7_1_6=1, DistStation_7=1, NewDistTable_34_1_33=1, NewDistTable_14_5_9=1, NewDistTable_16_5_11=1, NewDistTable_32_5_27=1, NewDistTable_39_2_37=1, DistStation_23=1, NewDistTable_25_3_22=1, NewDistTable_15_5_10=1, NewDistTable_3_2_1=1, DistStation_24=1, NewDistTable_20_2_18=1, NewDistTable_33_5_28=1, DistStation_37=1, NewDistTable_22_5_17=1, NewDistTable_22_4_18=1, NewDistTable_16_3_13=1, NewDistTable_34_2_32=1, DistStation_29=1, DistStation_31=1, NewDistTable_28_1_27=1, NewDistTable_32_2_30=1, NewDistTable_21_1_20=1, NewDistTable_39_1_38=1, NewDistTable_31_4_27=1, NewDistTable_16_4_12=1, DistStation_8=1, NewDistTable_40_1_39=1, NewDistTable_27_5_22=1, NewDistTable_23_3_20=1, DistStation_11=1, NewDistTable_18_2_16=1, NewDistTable_31_2_29=1, NewDistTable_21_2_19=1, NewDistTable_25_1_24=1, NewDistTable_32_4_28=1, NewDistTable_27_2_25=1, NewDistTable_22_1_21=1, NewDistTable_14_3_11=1, DistStation_14=1, NewDistTable_29_5_24=1, NewDistTable_8_1_7=1, DistStation_6=1, NewDistTable_10_3_7=1, NewDistTable_3_1_2=1, NewDistTable_5_1_4=1, NewDistTable_9_4_5=1, NewDistTable_33_2_31=1, NewDistTable_13_4_9=1, NewDistTable_32_3_29=1, DistStation_5=1, NewDistTable_5_3_2=1, NewDistTable_19_2_17=1, DistStation_9=1, NewDistTable_27_1_26=1, NewDistTable_20_1_19=1, NewDistTable_22_2_20=1, NewDistTable_38_2_36=1, NewDistTable_7_4_3=1, NewDistTable_40_2_38=1, NewDistTable_38_3_35=1, NewDistTable_11_2_9=1, DistStation_25=1, NewDistTable_26_5_21=1, NewDistTable_29_1_28=1, NewDistTable_17_4_13=1, NewDistTable_4_1_3=1, NewDistTable_28_2_26=1, NewDistTable_15_3_12=1, NewDistTable_27_4_23=1, NewDistTable_23_5_18=1, NewDistTable_15_4_11=1, NewDistTable_10_4_6=1, DistStation_10=1, NewDistTable_35_4_31=1, DistStation_39=1, NewDistTable_37_3_34=1, DistStation_32=1, NewDistTable_17_5_12=1, NewDistTable_35_1_34=1, NewDistTable_6_1_5=1, NewDistTable_20_4_16=1, StopTable_4_10=1, NewDistTable_14_2_12=1, NewDistTable_37_4_33=1, NewDistTable_33_4_29=1, DistStation_18=1, NewDistTable_14_1_13=1, NewDistTable_18_1_17=1, NewDistTable_34_5_29=1, NewDistTable_29_4_25=1, DistStation_35=1, DistStation_19=1, DistStation_26=1, NewDistTable_30_4_26=1, NewDistTable_8_2_6=1, NewDistTable_13_1_12=1, DistStation_16=1, DistStation_33=1, NewDistTable_33_1_32=1, NewDistTable_19_4_15=1, DistStation_30=1, NewDistTable_21_3_18=1, NewDistTable_30_2_28=1, NewDistTable_39_3_36=1, NewDistTable_23_4_19=1, NewDistTable_35_2_33=1, NewDistTable_7_2_5=1, NewDistTable_18_5_13=1, NewDistTable_25_2_23=1, NewDistTable_23_2_21=1, NewDistTable_26_4_22=1, NewDistTable_28_3_25=1, NewDistTable_33_3_30=1, DistStation_36=1, NewDistTable_5_2_3=1, NewDistTable_7_3_4=1, NewDistTable_11_5_6=1, NewDistTable_20_5_15=1, NewDistTable_24_3_21=1, NewDistTable_30_1_29=1, NewDistTable_9_1_8=1, NewDistTable_37_1_36=1, NewDistTable_16_2_14=1, NewDistTable_35_3_32=1, NewDistTable_20_3_17=1, NewDistTable_21_4_17=1, NewDistTable_30_3_27=1, NewDistTable_26_2_24=1, StopTable_1_1=1, DistStation_20=1, NewDistTable_14_4_10=1, NewDistTable_8_3_5=1, NewDistTable_13_3_10=1, NewDistTable_34_4_30=1, NewDistTable_10_2_8=1, NewDistTable_23_1_22=1, DistStation_38=1, NewDistTable_19_3_16=1, NewDistTable_36_2_34=1, NewDistTable_12_2_10=1, NewDistTable_21_5_16=1, StopTable_5_15=1, NewDistTable_38_1_37=1, NewDistTable_18_3_15=1, NewDistTable_2_1_1=1, NewDistTable_29_2_27=1, DistStation_17=1, NewDistTable_12_1_11=1, DistStation_34=1, NewDistTable_12_4_8=1, DistStation_13=1, NewDistTable_30_5_25=1, DistStation_40=1, NewDistTable_36_1_35=1, NewDistTable_6_3_3=1, NewDistTable_36_3_33=1, NewDistTable_18_4_14=1, NewDistTable_4_3_1=1, NewDistTable_25_5_20=1, NewDistTable_32_1_31=1, NewDistTable_24_2_22=1, NewDistTable_28_4_24=1, NewDistTable_16_1_15=1, NewDistTable_31_3_28=1, NewDistTable_9_2_7=1, NewDistTable_9_3_6=1, NewDistTable_12_3_9=1, NewDistTable_19_1_18=1, NewDistTable_24_4_20=1, NewDistTable_24_1_23=1, NewDistTable_15_1_14=1, NewDistTable_24_5_19=1, DistStation_22=1, NewDistTable_11_1_10=1, NewDistTable_17_1_16=1, NewDistTable_26_3_23=1, NewDistTable_28_5_23=1, DistStation_28=1, NewDistTable_31_5_26=1, NewDistTable_15_2_13=1, NewDistTable_11_3_8=1, DistStation_27=1, NewDistTable_22_3_19=1, NewDistTable_37_2_35=1, NewDistTable_34_3_31=1, NewDistTable_4_2_2=1, NewDistTable_6_2_4=1, NewDistTable_2_2_0=1, NewDistTable_17_2_15=1, NewDistTable_13_2_11=1, DistStation_15=1, DistStation_21=1, NewDistTable_31_1_30=1, DistStation_12=1, NewDistTable_10_1_9=1, NewDistTable_11_4_7=1, NewDistTable_12_5_7=1, NewDistTable_13_5_8=1, StopTable_3_6=1, NewDistTable_19_5_14=1, NewDistTable_25_4_21=1
Mar 25, 2019 8:12:03 PM fr.lip6.move.gal.instantiate.Simplifier simplifyConstantVariables
INFO: Simplified 1390 expressions due to constant valuations.
Mar 25, 2019 8:12:03 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 270 ms
Mar 25, 2019 8:12:03 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/CTLFireability.pnml.gal : 8 ms
Mar 25, 2019 8:12:03 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSCTLTools
INFO: Time to serialize properties into /home/mcc/execution/CTLFireability.ctl : 27 ms

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BART-PT-002"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3954"
echo " Executing tool itstools"
echo " Input is BART-PT-002, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r184-csrt-155344537500005"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/BART-PT-002.tgz
mv BART-PT-002 execution
cd execution
if [ "CTLFireability" = "GlobalProperties" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
if [ "CTLFireability" = "UpperBounds" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;