Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fko/mcc2019-input.r173-oct2-155297753700457.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fko/mcc2019-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.............................................................................
=====================================================================
Generated by BenchKit 2-3954
Executing tool itstools
Input is Vasy2003-PT-none, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r173-oct2-155297753700457
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 384K
-rw-r--r-- 1 mcc users 4.8K Feb 12 21:20 CTLCardinality.txt
-rw-r--r-- 1 mcc users 30K Feb 12 21:20 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 9 05:44 CTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 9 05:44 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 10 17:31 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K Mar 10 17:31 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 103 Feb 24 15:06 GlobalProperties.txt
-rw-r--r-- 1 mcc users 341 Feb 24 15:06 GlobalProperties.xml
-rw-r--r-- 1 mcc users 2.4K Feb 5 01:55 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K Feb 5 01:55 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.8K Feb 4 22:50 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.2K Feb 4 22:50 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.3K Feb 4 22:17 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K Feb 4 22:17 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 1 23:23 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 12K Feb 1 23:23 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 4 22:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 4 22:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jan 29 09:35 equiv_col
-rw-r--r-- 1 mcc users 5 Jan 29 09:35 instance
-rw-r--r-- 1 mcc users 6 Jan 29 09:35 iscolored
-rw-r--r-- 1 mcc users 0 Jan 29 09:35 model-fix.log
-rw-r--r-- 1 mcc users 207K Mar 10 17:31 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Vasy2003-PT-none-LTLFireability-00
FORMULA_NAME Vasy2003-PT-none-LTLFireability-01
FORMULA_NAME Vasy2003-PT-none-LTLFireability-02
FORMULA_NAME Vasy2003-PT-none-LTLFireability-03
FORMULA_NAME Vasy2003-PT-none-LTLFireability-04
FORMULA_NAME Vasy2003-PT-none-LTLFireability-05
FORMULA_NAME Vasy2003-PT-none-LTLFireability-06
FORMULA_NAME Vasy2003-PT-none-LTLFireability-07
FORMULA_NAME Vasy2003-PT-none-LTLFireability-08
FORMULA_NAME Vasy2003-PT-none-LTLFireability-09
FORMULA_NAME Vasy2003-PT-none-LTLFireability-10
FORMULA_NAME Vasy2003-PT-none-LTLFireability-11
FORMULA_NAME Vasy2003-PT-none-LTLFireability-12
FORMULA_NAME Vasy2003-PT-none-LTLFireability-13
FORMULA_NAME Vasy2003-PT-none-LTLFireability-14
FORMULA_NAME Vasy2003-PT-none-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1553240174502

Working with output stream class java.io.PrintStream
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903111103/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903111103/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((G(X(X(("((u52.p377>=1)&&(u58.p480>=1))")U("((u51.p126>=1)&&(u52.p260>=1))"))))))
Formula 0 simplified : !GXX("((u52.p377>=1)&&(u58.p480>=1))" U "((u51.p126>=1)&&(u52.p260>=1))")
built 93 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 696
// Phase 1: matrix 696 rows 485 cols
invariant :u41:p110 + u41:p111 + u52:p184 + u52:p431 + u61:p0 = 1
invariant :u23:p72 + u23:p73 + u23:p74 + u61:p0 = 1
invariant :-1'u52:p192 + -1'u52:p440 + u57:p464 + u58:p479 = 0
invariant :u14:p27 + u14:p28 + u14:p29 + u14:p30 + u14:p31 + u14:p32 + u61:p0 = 1
invariant :u35:p97 + u35:p98 + u61:p0 = 1
invariant :u43:p115 + -1'u52:p188 + -1'u52:p435 = 0
invariant :u21:p64 + u21:p65 + u21:p66 + u21:p67 + u21:p68 + u61:p0 = 1
invariant :u52:p190 + u52:p245 + u52:p248 + u52:p250 + u52:p303 + u52:p306 + u52:p438 + u59:p482 + u60:p484 + 2'u61:p0 = 2
invariant :u34:p95 + u34:p96 + u61:p0 = 1
invariant :u51:p126 + u51:p127 + u61:p0 = 1
invariant :u33:p93 + u33:p94 + u61:p0 = 1
invariant :u41:p109 + -1'u52:p184 + -1'u52:p431 = 0
invariant :u25:p77 + u25:p78 + u61:p0 = 1
invariant :u40:p107 + u40:p108 + u61:p0 = 1
invariant :u31:p89 + u31:p90 + u61:p0 = 1
invariant :u26:p79 + u26:p80 + u61:p0 = 1
invariant :u3:p5 + u3:p6 + u61:p0 = 1
invariant :u30:p87 + u30:p88 + u61:p0 = 1
invariant :u27:p81 + u27:p82 + u61:p0 = 1
invariant :u29:p85 + u29:p86 + u61:p0 = 1
invariant :u58:p466 + u58:p467 + u58:p468 + u58:p469 + u58:p470 + u58:p471 + u58:p472 + u58:p473 + u58:p474 + u58:p475 + u58:p476 + u58:p477 + u58:p478 + u58:p479 + u58:p480 + u61:p0 = 1
invariant :u52:p192 + u52:p440 + u57:p451 + u57:p452 + u57:p453 + u57:p454 + u57:p455 + u57:p456 + u57:p457 + u57:p458 + u57:p459 + u57:p460 + u57:p461 + u57:p462 + u57:p463 + u57:p465 + -1'u58:p479 + u61:p0 = 1
invariant :u17:p45 + u17:p46 + u17:p47 + u17:p50 + u17:p51 + u17:p52 + -1'u55:p446 = 0
invariant :u53:p442 + u53:p443 + u61:p0 = 1
invariant :u46:p120 + u61:p0 = 1
invariant :u20:p62 + u20:p63 + u61:p0 = 1
invariant :u45:p119 + u61:p0 = 1
invariant :u15:p33 + u15:p34 + u15:p35 + u15:p36 + u15:p37 + u15:p38 + u61:p0 = 1
invariant :u7:p13 + u7:p14 + u61:p0 = 1
invariant :u43:p116 + u43:p117 + u52:p188 + u52:p435 + u61:p0 = 1
invariant :u2:p3 + u2:p4 + u61:p0 = 1
invariant :u42:p112 + -1'u52:p186 + -1'u52:p433 = 0
invariant :u11:p21 + u11:p22 + u61:p0 = 1
invariant :u36:p99 + u36:p100 + u61:p0 = 1
invariant :u44:p118 + u61:p0 = 1
invariant :u55:p446 + u55:p447 + u55:p448 + u61:p0 = 1
invariant :u4:p7 + u4:p8 + u61:p0 = 1
invariant :u18:p57 + u18:p58 + u61:p0 = 1
invariant :u1:p1 + u1:p2 + u61:p0 = 1
invariant :u6:p11 + u6:p12 + u61:p0 = 1
invariant :u54:p444 + u54:p445 + u61:p0 = 1
invariant :u22:p69 + u22:p70 + u22:p71 + u61:p0 = 1
invariant :u8:p15 + u8:p16 + u61:p0 = 1
invariant :u12:p23 + u12:p24 + u61:p0 = 1
invariant :u24:p75 + u24:p76 + u61:p0 = 1
invariant :u10:p19 + u10:p20 + u61:p0 = 1
invariant :u32:p91 + u32:p92 + u61:p0 = 1
invariant :u47:p121 + u61:p0 = 1
invariant :u28:p83 + u28:p84 + u61:p0 = 1
invariant :u42:p113 + u42:p114 + u52:p186 + u52:p433 + u61:p0 = 1
invariant :u56:p449 + u56:p450 + u61:p0 = 1
invariant :u52:p128 + u52:p129 + u52:p130 + u52:p131 + u52:p132 + u52:p133 + u52:p134 + u52:p135 + u52:p136 + u52:p137 + u52:p138 + u52:p139 + u52:p140 + u52:p141 + u52:p142 + u52:p143 + u52:p144 + u52:p145 + u52:p146 + u52:p147 + u52:p148 + u52:p149 + u52:p150 + u52:p151 + u52:p152 + u52:p153 + u52:p154 + u52:p155 + u52:p156 + u52:p157 + u52:p158 + u52:p159 + u52:p160 + u52:p161 + u52:p162 + u52:p163 + u52:p164 + u52:p165 + u52:p166 + u52:p167 + u52:p168 + u52:p169 + u52:p170 + u52:p171 + u52:p172 + u52:p173 + u52:p174 + u52:p175 + u52:p176 + u52:p177 + u52:p178 + u52:p179 + u52:p180 + u52:p181 + u52:p182 + u52:p183 + u52:p184 + u52:p185 + u52:p186 + u52:p187 + u52:p188 + u52:p189 + u52:p190 + u52:p191 + u52:p192 + u52:p193 + u52:p194 + u52:p195 + u52:p196 + u52:p197 + u52:p198 + u52:p199 + u52:p200 + u52:p201 + u52:p202 + u52:p203 + u52:p204 + u52:p205 + u52:p206 + u52:p207 + u52:p208 + u52:p209 + u52:p210 + u52:p211 + u52:p212 + u52:p213 + u52:p214 + u52:p215 + u52:p216 + u52:p217 + u52:p218 + u52:p219 + u52:p220 + u52:p221 + u52:p222 + u52:p223 + u52:p224 + u52:p225 + u52:p226 + u52:p227 + u52:p228 + u52:p229 + u52:p230 + u52:p231 + u52:p232 + u52:p233 + u52:p234 + u52:p235 + u52:p236 + u52:p237 + u52:p238 + u52:p239 + u52:p240 + u52:p241 + u52:p242 + u52:p243 + u52:p244 + u52:p245 + u52:p246 + u52:p247 + u52:p248 + u52:p249 + u52:p250 + u52:p251 + u52:p252 + u52:p253 + u52:p254 + u52:p255 + u52:p256 + u52:p257 + u52:p258 + u52:p259 + u52:p260 + u52:p261 + u52:p262 + u52:p263 + u52:p264 + u52:p265 + u52:p266 + u52:p267 + u52:p268 + u52:p269 + u52:p270 + u52:p271 + u52:p272 + u52:p273 + u52:p274 + u52:p275 + u52:p276 + u52:p277 + u52:p278 + u52:p279 + u52:p280 + u52:p281 + u52:p282 + u52:p283 + u52:p284 + u52:p285 + u52:p286 + u52:p287 + u52:p288 + u52:p289 + u52:p290 + u52:p291 + u52:p292 + u52:p293 + u52:p294 + u52:p295 + u52:p296 + u52:p297 + u52:p298 + u52:p299 + u52:p300 + u52:p301 + u52:p302 + u52:p303 + u52:p304 + u52:p305 + u52:p306 + u52:p307 + u52:p308 + u52:p309 + u52:p310 + u52:p311 + u52:p312 + u52:p313 + u52:p314 + u52:p315 + u52:p316 + u52:p317 + u52:p318 + u52:p319 + u52:p320 + u52:p321 + u52:p322 + u52:p323 + u52:p324 + u52:p325 + u52:p326 + u52:p327 + u52:p328 + u52:p329 + u52:p330 + u52:p331 + u52:p332 + u52:p333 + u52:p334 + u52:p335 + u52:p336 + u52:p337 + u52:p338 + u52:p339 + u52:p340 + u52:p341 + u52:p342 + u52:p343 + u52:p344 + u52:p345 + u52:p346 + u52:p347 + u52:p348 + u52:p349 + u52:p350 + u52:p351 + u52:p352 + u52:p353 + u52:p354 + u52:p355 + u52:p356 + u52:p357 + u52:p358 + u52:p359 + u52:p360 + u52:p361 + u52:p362 + u52:p363 + u52:p364 + u52:p365 + u52:p366 + u52:p367 + u52:p368 + u52:p369 + u52:p370 + u52:p371 + u52:p372 + u52:p373 + u52:p374 + u52:p375 + u52:p376 + u52:p377 + u52:p378 + u52:p379 + u52:p380 + u52:p381 + u52:p382 + u52:p383 + u52:p384 + u52:p385 + u52:p386 + u52:p387 + u52:p388 + u52:p389 + u52:p390 + u52:p391 + u52:p392 + u52:p393 + u52:p394 + u52:p395 + u52:p396 + u52:p397 + u52:p398 + u52:p399 + u52:p400 + u52:p401 + u52:p402 + u52:p403 + u52:p404 + u52:p405 + u52:p406 + u52:p407 + u52:p408 + u52:p409 + u52:p410 + u52:p411 + u52:p412 + u52:p413 + u52:p414 + u52:p415 + u52:p416 + u52:p417 + u52:p418 + u52:p419 + u52:p420 + u52:p421 + u52:p422 + u52:p423 + u52:p424 + u52:p425 + u52:p426 + u52:p427 + u52:p428 + u52:p429 + u52:p430 + u52:p431 + u52:p432 + u52:p433 + u52:p434 + u52:p435 + u52:p436 + u52:p437 + u52:p438 + u52:p439 + u52:p440 + u52:p441 + u61:p0 = 1
invariant :u39:p105 + u39:p106 + u61:p0 = 1
invariant :u50:p124 + u50:p125 + u61:p0 = 1
invariant :u48:p122 + u61:p0 = 1
invariant :u49:p123 + u61:p0 = 1
invariant :u5:p9 + u5:p10 + u61:p0 = 1
invariant :-1'u52:p190 + -1'u52:p245 + -1'u52:p248 + -1'u52:p250 + -1'u52:p303 + -1'u52:p306 + -1'u52:p438 + u59:p481 + -1'u60:p484 + -1'u61:p0 = -1
invariant :u17:p48 + u17:p49 + u17:p53 + u17:p54 + u17:p55 + u17:p56 + u55:p446 + u61:p0 = 1
invariant :u60:p483 + u60:p484 + u61:p0 = 1
invariant :u38:p103 + u38:p104 + u61:p0 = 1
invariant :u13:p25 + u13:p26 + u61:p0 = 1
invariant :u9:p17 + u9:p18 + u61:p0 = 1
invariant :u37:p101 + u37:p102 + u61:p0 = 1
invariant :u19:p59 + u19:p60 + u19:p61 + u61:p0 = 1
invariant :u16:p39 + u16:p40 + u16:p41 + u16:p42 + u16:p43 + u16:p44 + u61:p0 = 1
Reverse transition relation is NOT exact ! Due to transitions u41.t10, u41.t11, u42.t8, u42.t9, u43.t6, u43.t7, u52.t564, u52.t565, u52.t566, u52.t567, u52.t568, u52.t569, u52.t570, u52.t571, u52.t572, u52.t573, u52.t576, u52.t577, u52.t597, u52.t598, u52.t601, u52.t602, u52.t643, u52.t644, u52.t666, u52.t667, u52.t668, u52.t669, u52.t670, u52.t671, u52.t672, u52.t673, u57.t68, u58.t77, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :24/721/31/776
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O2, model.c], workingDir=/home/mcc/execution]
Compilation finished in 8725 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 113 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, [](X(X(((LTLAP0==true))U((LTLAP1==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
5 unique states visited
5 strongly connected components in search stack
6 transitions explored
5 items max in DFS search stack
5443 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,54.5086,827132,1,0,1.38369e+06,385023,6701,2.70354e+06,8344,2.28054e+06,200296
an accepting run exists (use option '-e' to print it)
Formula 0 is FALSE accepting run found.
FORMULA Vasy2003-PT-none-LTLFireability-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 1 : !((F(F("((u33.p94>=1)&&(u42.p114>=1))"))))
Formula 1 simplified : !F"((u33.p94>=1)&&(u42.p114>=1))"
1 unique states visited
0 strongly connected components in search stack
0 transitions explored
1 items max in DFS search stack
0 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,54.5164,827556,1,0,1.38369e+06,385023,6781,2.70354e+06,8344,2.28054e+06,200444
no accepting run found
Formula 1 is TRUE no accepting run found.
FORMULA Vasy2003-PT-none-LTLFireability-01 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 2 : !((G(F(F(F(G("((u58.p476>=1)&&(u59.p482>=1))")))))))
Formula 2 simplified : !GFG"((u58.p476>=1)&&(u59.p482>=1))"
LTSmin run took 18393 ms.
FORMULA Vasy2003-PT-none-LTLFireability-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, [](<>(<>(<>([]((LTLAP3==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 13034 ms.
FORMULA Vasy2003-PT-none-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X(<>((LTLAP4==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 4689 ms.
FORMULA Vasy2003-PT-none-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, ((<>((LTLAP5==true)))U(<>((LTLAP6==true))))U([]([]((LTLAP7==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 13935 ms.
FORMULA Vasy2003-PT-none-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, <>(<>(<>(X((LTLAP7==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 3495 ms.
FORMULA Vasy2003-PT-none-LTLFireability-05 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, [](<>((LTLAP8==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 13610 ms.
FORMULA Vasy2003-PT-none-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X(<>(<>(X((LTLAP9==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 3883 ms.
FORMULA Vasy2003-PT-none-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X(<>([](X(X((LTLAP10==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 4334 ms.
FORMULA Vasy2003-PT-none-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, <>((LTLAP11==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 14613 ms.
FORMULA Vasy2003-PT-none-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, ([](((LTLAP12==true))U((LTLAP13==true))))U(<>((LTLAP14==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 13101 ms.
FORMULA Vasy2003-PT-none-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, (X((LTLAP15==true)))U([](<>(<>((LTLAP16==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 2903 ms.
FORMULA Vasy2003-PT-none-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X((LTLAP17==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 23477 ms.
FORMULA Vasy2003-PT-none-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, (LTLAP18==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 12304 ms.
FORMULA Vasy2003-PT-none-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, []((LTLAP19==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 14474 ms.
FORMULA Vasy2003-PT-none-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, [](X(X(((LTLAP20==true))U((LTLAP21==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 3009 ms.
FORMULA Vasy2003-PT-none-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1553240391464

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ LTLFireability = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Mar 22, 2019 7:36:17 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Mar 22, 2019 7:36:17 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Mar 22, 2019 7:36:17 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 142 ms
Mar 22, 2019 7:36:17 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 485 places.
Mar 22, 2019 7:36:17 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 776 transitions.
Mar 22, 2019 7:36:17 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
Mar 22, 2019 7:36:17 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 44 ms
Mar 22, 2019 7:36:18 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Mar 22, 2019 7:36:18 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 535 ms
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 408 ms
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 2 events :t697,t697,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 1 events :t562,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 18 events :t32,t93,t87,t87,t87,t87,t87,t81,t81,t81,t81,t81,t32,t32,t32,t33,t33,t33,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 33 events :t555,t555,t555,t555,t555,t555,t548,t548,t548,t548,t548,t548,t526,t526,t526,t526,t526,t526,t526,t526,t526,t526,t526,t526,t526,t526,t526,t526,t526,t526,t526,t526,t526,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 1 events :t27,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 126 events :t525,t524,t523,t522,t521,t520,t519,t518,t517,t516,t515,t514,t513,t512,t503,t502,t491,t490,t481,t481,t478,t478,t197,t196,t195,t194,t193,t192,t191,t190,t189,t188,t187,t186,t185,t184,t183,t182,t181,t180,t179,t178,t177,t176,t175,t174,t173,t172,t171,t170,t169,t168,t167,t166,t165,t164,t163,t162,t161,t160,t159,t158,t157,t156,t155,t154,t153,t152,t151,t150,t149,t148,t147,t146,t145,t144,t143,t142,t141,t140,t139,t138,t137,t136,t135,t134,t133,t132,t131,t130,t129,t128,t127,t126,t125,t124,t123,t122,t121,t120,t119,t118,t117,t116,t115,t114,t113,t112,t111,t110,t109,t108,t107,t106,t105,t104,t103,t102,t101,t100,t99,t98,t97,t96,t95,t94,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 33 events :t519,t519,t519,t519,t519,t519,t512,t512,t512,t512,t512,t512,t490,t490,t490,t490,t490,t490,t490,t490,t490,t490,t490,t490,t490,t490,t490,t490,t490,t490,t490,t490,t490,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 8 events :t51,t51,t51,t51,t51,t475,t474,t480,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 3 events :t29,t29,t29,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 1 events :t26,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 41 events :t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t737,t32,t32,t32,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 1 events :t28,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 7 events :t763,t763,t763,t763,t728,t728,t728,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 8 events :t50,t50,t50,t50,t50,t473,t472,t479,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 110 events :t507,t506,t505,t504,t497,t496,t495,t494,t492,t196,t194,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t113,t93,t93,t93,t93,t93,t93,t93,t93,t93,t93,t93,t93,t93,t93,t93,t93,t93,t93,t93,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 1 events :t718,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 7 events :t737,t737,t737,t737,t720,t720,t720,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 110 events :t511,t510,t509,t508,t501,t500,t499,t498,t493,t301,t299,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t218,t198,t198,t198,t198,t198,t198,t198,t198,t198,t198,t198,t198,t198,t198,t198,t198,t198,t198,t198,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 100 events :t469,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,t305,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 4 events :t33,t33,t35,t33,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 7 events :t750,t750,t750,t750,t724,t724,t724,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 1 events :t25,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 3 events :t22,t22,t22,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 62 events :t465,t465,t465,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,t306,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 8 events :t49,t49,t49,t49,t49,t477,t476,t478,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator dropEvents
INFO: Dropping 6 events :t732,t732,t732,t714,t714,t714,
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 702 redundant transitions.
Mar 22, 2019 7:36:19 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 461 ms
Mar 22, 2019 7:36:19 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 7 ms
Mar 22, 2019 7:36:19 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 1 ms
Mar 22, 2019 7:36:20 AM fr.lip6.move.gal.semantics.CompositeNextBuilder getNextForLabel
INFO: Semantic construction discarded 24 identical transitions.
Mar 22, 2019 7:36:20 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 752 transitions.
Mar 22, 2019 7:36:21 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 66 place invariants in 297 ms
Mar 22, 2019 7:36:22 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 485 variables to be positive in 2217 ms
Mar 22, 2019 7:36:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 752 transitions.
Mar 22, 2019 7:36:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/752 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 22, 2019 7:36:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 63 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 22, 2019 7:36:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 752 transitions.
Mar 22, 2019 7:36:23 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 41 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 22, 2019 7:36:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 752 transitions.
Mar 22, 2019 7:36:34 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/752) took 1931 ms. Total solver calls (SAT/UNSAT): 751(0/751)
Mar 22, 2019 7:36:37 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(34/752) took 4953 ms. Total solver calls (SAT/UNSAT): 1151(109/1042)
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown' twice, overapproximating result to 1.
Mar 22, 2019 7:36:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(45/752) took 15759 ms. Total solver calls (SAT/UNSAT): 1536(255/1281)
Mar 22, 2019 7:36:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 15827 ms. Total solver calls (SAT/UNSAT): 1536(255/1281)
Mar 22, 2019 7:36:49 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 752 transitions.
Mar 22, 2019 7:37:02 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 13377 ms. Total solver calls (SAT/UNSAT): 5388(0/5388)
Mar 22, 2019 7:37:02 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 42649ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Vasy2003-PT-none"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3954"
echo " Executing tool itstools"
echo " Input is Vasy2003-PT-none, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r173-oct2-155297753700457"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Vasy2003-PT-none.tgz
mv Vasy2003-PT-none execution
cd execution
if [ "LTLFireability" = "GlobalProperties" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
if [ "LTLFireability" = "UpperBounds" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;