Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fko/mcc2019-input.r107-oct2-155272231200610.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fko/mcc2019-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................
=====================================================================
Generated by BenchKit 2-3954
Executing tool itstools
Input is PhaseVariation-PT-D05CS100, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r107-oct2-155272231200610
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 808K
-rw-r--r-- 1 mcc users 4.6K Feb 12 04:24 CTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 12 04:24 CTLCardinality.xml
-rw-r--r-- 1 mcc users 3.5K Feb 8 03:37 CTLFireability.txt
-rw-r--r-- 1 mcc users 15K Feb 8 03:37 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 10 17:31 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.6K Mar 10 17:31 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 113 Feb 24 15:05 GlobalProperties.txt
-rw-r--r-- 1 mcc users 351 Feb 24 15:05 GlobalProperties.xml
-rw-r--r-- 1 mcc users 2.8K Feb 5 00:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K Feb 5 00:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 4 22:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.2K Feb 4 22:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K Feb 4 08:09 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 16K Feb 4 08:09 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 4.7K Feb 1 02:34 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 20K Feb 1 02:34 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 4 22:22 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 4 22:22 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jan 29 09:34 equiv_col
-rw-r--r-- 1 mcc users 9 Jan 29 09:34 instance
-rw-r--r-- 1 mcc users 6 Jan 29 09:34 iscolored
-rw-r--r-- 1 mcc users 633K Mar 10 17:31 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-00
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-01
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-02
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-03
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-04
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-05
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-06
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-07
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-08
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-09
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-10
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-11
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-12
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-13
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-14
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1552941452893

Working with output stream class java.io.PrintStream
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903111103/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903111103/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((("(((pool__2_4_>=1)&&(cell___1_5__A_>=1))&&(run_dot>=1))")U(F(G(X("(((pool__4_1_>=1)&&(cell___4_1__A_>=1))&&(run_dot>=1))"))))))
Formula 0 simplified : !("(((pool__2_4_>=1)&&(cell___1_5__A_>=1))&&(run_dot>=1))" U FGX"(((pool__4_1_>=1)&&(cell___4_1__A_>=1))&&(run_dot>=1))")
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 51
// Phase 1: matrix 51 rows 77 cols
invariant :cell___4_4__A_ + cell___4_4__B_ + pool__4_4_ = 5
invariant :cell___1_3__A_ + cell___1_3__B_ + pool__1_3_ = 5
invariant :cell___5_4__A_ + cell___5_4__B_ + pool__5_4_ = 5
invariant :cell___3_4__A_ + cell___3_4__B_ + pool__3_4_ = 5
invariant :cell___5_1__A_ + cell___5_1__B_ + pool__5_1_ = 5
invariant :cell___1_4__A_ + cell___1_4__B_ + pool__1_4_ = 5
invariant :pool__1_1_ + pool__1_2_ + pool__1_3_ + pool__1_4_ + pool__1_5_ + pool__2_1_ + pool__2_2_ + pool__2_3_ + pool__2_4_ + pool__2_5_ + pool__3_1_ + pool__3_2_ + pool__3_3_ + pool__3_4_ + pool__3_5_ + pool__4_1_ + pool__4_2_ + pool__4_3_ + pool__4_4_ + pool__4_5_ + pool__5_1_ + pool__5_2_ + pool__5_3_ + pool__5_4_ + pool__5_5_ + size_dot = 125
invariant :cell___5_3__A_ + cell___5_3__B_ + pool__5_3_ = 5
invariant :cell___3_5__A_ + cell___3_5__B_ + pool__3_5_ = 5
invariant :cell___3_2__A_ + cell___3_2__B_ + pool__3_2_ = 5
invariant :cell___5_5__A_ + cell___5_5__B_ + pool__5_5_ = 5
invariant :cell___2_4__A_ + cell___2_4__B_ + pool__2_4_ = 5
invariant :cell___2_1__A_ + cell___2_1__B_ + pool__2_1_ = 5
invariant :cell___1_2__A_ + cell___1_2__B_ + pool__1_2_ = 5
invariant :cell___2_5__A_ + cell___2_5__B_ + pool__2_5_ = 5
invariant :cell___4_5__A_ + cell___4_5__B_ + pool__4_5_ = 5
invariant :cell___2_3__A_ + cell___2_3__B_ + pool__2_3_ = 5
invariant :cell___4_3__A_ + cell___4_3__B_ + pool__4_3_ = 5
invariant :cell___3_3__A_ + cell___3_3__B_ + pool__3_3_ = 5
invariant :cell___5_2__A_ + cell___5_2__B_ + pool__5_2_ = 5
invariant :cell___1_5__A_ + cell___1_5__B_ + pool__1_5_ = 5
invariant :cell___4_2__A_ + cell___4_2__B_ + pool__4_2_ = 5
invariant :cell___3_1__A_ + cell___3_1__B_ + pool__3_1_ = 5
invariant :cell___1_1__A_ + cell___1_1__B_ + -1'pool__1_2_ + -1'pool__1_3_ + -1'pool__1_4_ + -1'pool__1_5_ + -1'pool__2_1_ + -1'pool__2_2_ + -1'pool__2_3_ + -1'pool__2_4_ + -1'pool__2_5_ + -1'pool__3_1_ + -1'pool__3_2_ + -1'pool__3_3_ + -1'pool__3_4_ + -1'pool__3_5_ + -1'pool__4_1_ + -1'pool__4_2_ + -1'pool__4_3_ + -1'pool__4_4_ + -1'pool__4_5_ + -1'pool__5_1_ + -1'pool__5_2_ + -1'pool__5_3_ + -1'pool__5_4_ + -1'pool__5_5_ + -1'size_dot = -120
invariant :cell___2_2__A_ + cell___2_2__B_ + pool__2_2_ = 5
invariant :cell___4_1__A_ + cell___4_1__B_ + pool__4_1_ = 5
Reverse transition relation is NOT exact ! Due to transitions division2_mutate_1_3_A_1_2, division2_mutate_1_3_A_1_4, division2_mutate_1_3_A_2_2, division2_mutate_1_3_A_2_4, division2_mutate_1_3_B_1_2, division2_mutate_1_3_B_1_4, division2_mutate_1_3_B_2_2, division2_mutate_1_3_B_2_4, division2_mutate_1_4_A_1_3, division2_mutate_1_4_A_1_5, division2_mutate_1_4_A_2_3, division2_mutate_1_4_A_2_5, division2_mutate_1_4_B_1_3, division2_mutate_1_4_B_1_5, division2_mutate_1_4_B_2_3, division2_mutate_1_4_B_2_5, division2_mutate_2_3_A_1_2, division2_mutate_2_3_A_1_3, division2_mutate_2_3_A_1_4, division2_mutate_2_3_A_2_2, division2_mutate_2_3_A_2_4, division2_mutate_2_3_A_3_2, division2_mutate_2_3_A_3_3, division2_mutate_2_3_A_3_4, division2_mutate_2_3_B_1_2, division2_mutate_2_3_B_1_3, division2_mutate_2_3_B_1_4, division2_mutate_2_3_B_2_2, division2_mutate_2_3_B_2_4, division2_mutate_2_3_B_3_2, division2_mutate_2_3_B_3_3, division2_mutate_2_3_B_3_4, division2_mutate_2_4_A_1_3, division2_mutate_2_4_A_1_4, division2_mutate_2_4_A_1_5, division2_mutate_2_4_A_2_3, division2_mutate_2_4_A_2_5, division2_mutate_2_4_A_3_3, division2_mutate_2_4_A_3_4, division2_mutate_2_4_A_3_5, division2_mutate_2_4_B_1_3, division2_mutate_2_4_B_1_4, division2_mutate_2_4_B_1_5, division2_mutate_2_4_B_2_3, division2_mutate_2_4_B_2_5, division2_mutate_2_4_B_3_3, division2_mutate_2_4_B_3_4, division2_mutate_2_4_B_3_5, division2_mutate_2_5_A_1_4, division2_mutate_2_5_A_1_5, division2_mutate_2_5_A_3_4, division2_mutate_2_5_A_3_5, division2_mutate_2_5_B_1_4, division2_mutate_2_5_B_1_5, division2_mutate_2_5_B_3_4, division2_mutate_2_5_B_3_5, division2_mutate_3_1_A_2_1, division2_mutate_3_1_A_2_2, division2_mutate_3_1_A_4_1, division2_mutate_3_1_A_4_2, division2_mutate_3_1_B_2_1, division2_mutate_3_1_B_2_2, division2_mutate_3_1_B_4_1, division2_mutate_3_1_B_4_2, division2_mutate_3_2_A_2_1, division2_mutate_3_2_A_2_2, division2_mutate_3_2_A_2_3, division2_mutate_3_2_A_3_1, division2_mutate_3_2_A_3_3, division2_mutate_3_2_A_4_1, division2_mutate_3_2_A_4_2, division2_mutate_3_2_A_4_3, division2_mutate_3_2_B_2_1, division2_mutate_3_2_B_2_2, division2_mutate_3_2_B_2_3, division2_mutate_3_2_B_3_1, division2_mutate_3_2_B_3_3, division2_mutate_3_2_B_4_1, division2_mutate_3_2_B_4_2, division2_mutate_3_2_B_4_3, division2_mutate_3_3_A_2_2, division2_mutate_3_3_A_2_3, division2_mutate_3_3_A_2_4, division2_mutate_3_3_A_3_2, division2_mutate_3_3_A_3_4, division2_mutate_3_3_A_4_2, division2_mutate_3_3_A_4_3, division2_mutate_3_3_A_4_4, division2_mutate_3_3_B_2_2, division2_mutate_3_3_B_2_3, division2_mutate_3_3_B_2_4, division2_mutate_3_3_B_3_2, division2_mutate_3_3_B_3_4, division2_mutate_3_3_B_4_2, division2_mutate_3_3_B_4_3, division2_mutate_3_3_B_4_4, division2_mutate_3_4_A_2_3, division2_mutate_3_4_A_2_4, division2_mutate_3_4_A_2_5, division2_mutate_3_4_A_3_3, division2_mutate_3_4_A_3_5, division2_mutate_3_4_A_4_3, division2_mutate_3_4_A_4_4, division2_mutate_3_4_A_4_5, division2_mutate_3_4_B_2_3, division2_mutate_3_4_B_2_4, division2_mutate_3_4_B_2_5, division2_mutate_3_4_B_3_3, division2_mutate_3_4_B_3_5, division2_mutate_3_4_B_4_3, division2_mutate_3_4_B_4_4, division2_mutate_3_4_B_4_5, division2_mutate_3_5_A_2_4, division2_mutate_3_5_A_2_5, division2_mutate_3_5_A_4_4, division2_mutate_3_5_A_4_5, division2_mutate_3_5_B_2_4, division2_mutate_3_5_B_2_5, division2_mutate_3_5_B_4_4, division2_mutate_3_5_B_4_5, division2_mutate_4_1_A_3_1, division2_mutate_4_1_A_3_2, division2_mutate_4_1_A_5_1, division2_mutate_4_1_A_5_2, division2_mutate_4_1_B_3_1, division2_mutate_4_1_B_3_2, division2_mutate_4_1_B_5_1, division2_mutate_4_1_B_5_2, division2_mutate_4_2_A_3_1, division2_mutate_4_2_A_3_2, division2_mutate_4_2_A_3_3, division2_mutate_4_2_A_4_1, division2_mutate_4_2_A_4_3, division2_mutate_4_2_A_5_1, division2_mutate_4_2_A_5_2, division2_mutate_4_2_A_5_3, division2_mutate_4_2_B_3_1, division2_mutate_4_2_B_3_2, division2_mutate_4_2_B_3_3, division2_mutate_4_2_B_4_1, division2_mutate_4_2_B_4_3, division2_mutate_4_2_B_5_1, division2_mutate_4_2_B_5_2, division2_mutate_4_2_B_5_3, division2_mutate_4_3_A_3_2, division2_mutate_4_3_A_3_3, division2_mutate_4_3_A_3_4, division2_mutate_4_3_A_4_2, division2_mutate_4_3_A_4_4, division2_mutate_4_3_A_5_2, division2_mutate_4_3_A_5_3, division2_mutate_4_3_A_5_4, division2_mutate_4_3_B_3_2, division2_mutate_4_3_B_3_3, division2_mutate_4_3_B_3_4, division2_mutate_4_3_B_4_2, division2_mutate_4_3_B_4_4, division2_mutate_4_3_B_5_2, division2_mutate_4_3_B_5_3, division2_mutate_4_3_B_5_4, division2_mutate_4_4_A_3_3, division2_mutate_4_4_A_3_4, division2_mutate_4_4_A_3_5, division2_mutate_4_4_A_4_3, division2_mutate_4_4_A_4_5, division2_mutate_4_4_A_5_3, division2_mutate_4_4_A_5_4, division2_mutate_4_4_A_5_5, division2_mutate_4_4_B_3_3, division2_mutate_4_4_B_3_4, division2_mutate_4_4_B_3_5, division2_mutate_4_4_B_4_3, division2_mutate_4_4_B_4_5, division2_mutate_4_4_B_5_3, division2_mutate_4_4_B_5_4, division2_mutate_4_4_B_5_5, division2_mutate_4_5_A_3_4, division2_mutate_4_5_A_3_5, division2_mutate_4_5_A_5_4, division2_mutate_4_5_A_5_5, division2_mutate_4_5_B_3_4, division2_mutate_4_5_B_3_5, division2_mutate_4_5_B_5_4, division2_mutate_4_5_B_5_5, division2_mutate_5_2_A_4_1, division2_mutate_5_2_A_4_3, division2_mutate_5_2_A_5_1, division2_mutate_5_2_A_5_3, division2_mutate_5_2_B_4_1, division2_mutate_5_2_B_4_3, division2_mutate_5_2_B_5_1, division2_mutate_5_2_B_5_3, division2_mutate_5_3_A_4_2, division2_mutate_5_3_A_4_4, division2_mutate_5_3_A_5_2, division2_mutate_5_3_A_5_4, division2_mutate_5_3_B_4_2, division2_mutate_5_3_B_4_4, division2_mutate_5_3_B_5_2, division2_mutate_5_3_B_5_4, division2_mutate_5_4_A_4_3, division2_mutate_5_4_A_4_5, division2_mutate_5_4_A_5_3, division2_mutate_5_4_A_5_5, division2_mutate_5_4_B_4_3, division2_mutate_5_4_B_4_5, division2_mutate_5_4_B_5_3, division2_mutate_5_4_B_5_5, division2_replicate_1_3_A_1_2, division2_replicate_1_3_A_1_4, division2_replicate_1_3_A_2_2, division2_replicate_1_3_A_2_4, division2_replicate_1_3_B_1_2, division2_replicate_1_3_B_1_4, division2_replicate_1_3_B_2_2, division2_replicate_1_3_B_2_4, division2_replicate_1_4_A_1_3, division2_replicate_1_4_A_1_5, division2_replicate_1_4_A_2_3, division2_replicate_1_4_A_2_5, division2_replicate_1_4_B_1_3, division2_replicate_1_4_B_1_5, division2_replicate_1_4_B_2_3, division2_replicate_1_4_B_2_5, division2_replicate_2_3_A_1_2, division2_replicate_2_3_A_1_3, division2_replicate_2_3_A_1_4, division2_replicate_2_3_A_2_2, division2_replicate_2_3_A_2_4, division2_replicate_2_3_A_3_2, division2_replicate_2_3_A_3_3, division2_replicate_2_3_A_3_4, division2_replicate_2_3_B_1_2, division2_replicate_2_3_B_1_3, division2_replicate_2_3_B_1_4, division2_replicate_2_3_B_2_2, division2_replicate_2_3_B_2_4, division2_replicate_2_3_B_3_2, division2_replicate_2_3_B_3_3, division2_replicate_2_3_B_3_4, division2_replicate_2_4_A_1_3, division2_replicate_2_4_A_1_4, division2_replicate_2_4_A_1_5, division2_replicate_2_4_A_2_3, division2_replicate_2_4_A_2_5, division2_replicate_2_4_A_3_3, division2_replicate_2_4_A_3_4, division2_replicate_2_4_A_3_5, division2_replicate_2_4_B_1_3, division2_replicate_2_4_B_1_4, division2_replicate_2_4_B_1_5, division2_replicate_2_4_B_2_3, division2_replicate_2_4_B_2_5, division2_replicate_2_4_B_3_3, division2_replicate_2_4_B_3_4, division2_replicate_2_4_B_3_5, division2_replicate_2_5_A_1_4, division2_replicate_2_5_A_1_5, division2_replicate_2_5_A_3_4, division2_replicate_2_5_A_3_5, division2_replicate_2_5_B_1_4, division2_replicate_2_5_B_1_5, division2_replicate_2_5_B_3_4, division2_replicate_2_5_B_3_5, division2_replicate_3_1_A_2_1, division2_replicate_3_1_A_2_2, division2_replicate_3_1_A_4_1, division2_replicate_3_1_A_4_2, division2_replicate_3_1_B_2_1, division2_replicate_3_1_B_2_2, division2_replicate_3_1_B_4_1, division2_replicate_3_1_B_4_2, division2_replicate_3_2_A_2_1, division2_replicate_3_2_A_2_2, division2_replicate_3_2_A_2_3, division2_replicate_3_2_A_3_1, division2_replicate_3_2_A_3_3, division2_replicate_3_2_A_4_1, division2_replicate_3_2_A_4_2, division2_replicate_3_2_A_4_3, division2_replicate_3_2_B_2_1, division2_replicate_3_2_B_2_2, division2_replicate_3_2_B_2_3, division2_replicate_3_2_B_3_1, division2_replicate_3_2_B_3_3, division2_replicate_3_2_B_4_1, division2_replicate_3_2_B_4_2, division2_replicate_3_2_B_4_3, division2_replicate_3_3_A_2_2, division2_replicate_3_3_A_2_3, division2_replicate_3_3_A_2_4, division2_replicate_3_3_A_3_2, division2_replicate_3_3_A_3_4, division2_replicate_3_3_A_4_2, division2_replicate_3_3_A_4_3, division2_replicate_3_3_A_4_4, division2_replicate_3_3_B_2_2, division2_replicate_3_3_B_2_3, division2_replicate_3_3_B_2_4, division2_replicate_3_3_B_3_2, division2_replicate_3_3_B_3_4, division2_replicate_3_3_B_4_2, division2_replicate_3_3_B_4_3, division2_replicate_3_3_B_4_4, division2_replicate_3_4_A_2_3, division2_replicate_3_4_A_2_4, division2_replicate_3_4_A_2_5, division2_replicate_3_4_A_3_3, division2_replicate_3_4_A_3_5, division2_replicate_3_4_A_4_3, division2_replicate_3_4_A_4_4, division2_replicate_3_4_A_4_5, division2_replicate_3_4_B_2_3, division2_replicate_3_4_B_2_4, division2_replicate_3_4_B_2_5, division2_replicate_3_4_B_3_3, division2_replicate_3_4_B_3_5, division2_replicate_3_4_B_4_3, division2_replicate_3_4_B_4_4, division2_replicate_3_4_B_4_5, division2_replicate_3_5_A_2_4, division2_replicate_3_5_A_2_5, division2_replicate_3_5_A_4_4, division2_replicate_3_5_A_4_5, division2_replicate_3_5_B_2_4, division2_replicate_3_5_B_2_5, division2_replicate_3_5_B_4_4, division2_replicate_3_5_B_4_5, division2_replicate_4_1_A_3_1, division2_replicate_4_1_A_3_2, division2_replicate_4_1_A_5_1, division2_replicate_4_1_A_5_2, division2_replicate_4_1_B_3_1, division2_replicate_4_1_B_3_2, division2_replicate_4_1_B_5_1, division2_replicate_4_1_B_5_2, division2_replicate_4_2_A_3_1, division2_replicate_4_2_A_3_2, division2_replicate_4_2_A_3_3, division2_replicate_4_2_A_4_1, division2_replicate_4_2_A_4_3, division2_replicate_4_2_A_5_1, division2_replicate_4_2_A_5_2, division2_replicate_4_2_A_5_3, division2_replicate_4_2_B_3_1, division2_replicate_4_2_B_3_2, division2_replicate_4_2_B_3_3, division2_replicate_4_2_B_4_1, division2_replicate_4_2_B_4_3, division2_replicate_4_2_B_5_1, division2_replicate_4_2_B_5_2, division2_replicate_4_2_B_5_3, division2_replicate_4_3_A_3_2, division2_replicate_4_3_A_3_3, division2_replicate_4_3_A_3_4, division2_replicate_4_3_A_4_2, division2_replicate_4_3_A_4_4, division2_replicate_4_3_A_5_2, division2_replicate_4_3_A_5_3, division2_replicate_4_3_A_5_4, division2_replicate_4_3_B_3_2, division2_replicate_4_3_B_3_3, division2_replicate_4_3_B_3_4, division2_replicate_4_3_B_4_2, division2_replicate_4_3_B_4_4, division2_replicate_4_3_B_5_2, division2_replicate_4_3_B_5_3, division2_replicate_4_3_B_5_4, division2_replicate_4_4_A_3_3, division2_replicate_4_4_A_3_4, division2_replicate_4_4_A_3_5, division2_replicate_4_4_A_4_3, division2_replicate_4_4_A_4_5, division2_replicate_4_4_A_5_3, division2_replicate_4_4_A_5_4, division2_replicate_4_4_A_5_5, division2_replicate_4_4_B_3_3, division2_replicate_4_4_B_3_4, division2_replicate_4_4_B_3_5, division2_replicate_4_4_B_4_3, division2_replicate_4_4_B_4_5, division2_replicate_4_4_B_5_3, division2_replicate_4_4_B_5_4, division2_replicate_4_4_B_5_5, division2_replicate_4_5_A_3_4, division2_replicate_4_5_A_3_5, division2_replicate_4_5_A_5_4, division2_replicate_4_5_A_5_5, division2_replicate_4_5_B_3_4, division2_replicate_4_5_B_3_5, division2_replicate_4_5_B_5_4, division2_replicate_4_5_B_5_5, division2_replicate_5_2_A_4_1, division2_replicate_5_2_A_4_3, division2_replicate_5_2_A_5_1, division2_replicate_5_2_A_5_3, division2_replicate_5_2_B_4_1, division2_replicate_5_2_B_4_3, division2_replicate_5_2_B_5_1, division2_replicate_5_2_B_5_3, division2_replicate_5_3_A_4_2, division2_replicate_5_3_A_4_4, division2_replicate_5_3_A_5_2, division2_replicate_5_3_A_5_4, division2_replicate_5_3_B_4_2, division2_replicate_5_3_B_4_4, division2_replicate_5_3_B_5_2, division2_replicate_5_3_B_5_4, division2_replicate_5_4_A_4_3, division2_replicate_5_4_A_4_5, division2_replicate_5_4_A_5_3, division2_replicate_5_4_A_5_5, division2_replicate_5_4_B_4_3, division2_replicate_5_4_B_4_5, division2_replicate_5_4_B_5_3, division2_replicate_5_4_B_5_5, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :0/261/416/677
Computing Next relation with stutter on 1.05588e+31 deadlock states
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O2, model.c], workingDir=/home/mcc/execution]
Compilation finished in 6048 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 82 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, ((LTLAP0==true))U(<>([](X((LTLAP1==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1720 ms.
FORMULA PhaseVariation-PT-D05CS100-LTLFireability-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X(X((LTLAP2==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 4032 ms.
FORMULA PhaseVariation-PT-D05CS100-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X((LTLAP3==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 2236 ms.
FORMULA PhaseVariation-PT-D05CS100-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, <>((<>(<>((LTLAP4==true))))U((LTLAP5==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 6162 ms.
FORMULA PhaseVariation-PT-D05CS100-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, [](([](X((LTLAP6==true))))U((LTLAP7==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 2397 ms.
FORMULA PhaseVariation-PT-D05CS100-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, ((LTLAP8==true))U([]((LTLAP9==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 5326 ms.
FORMULA PhaseVariation-PT-D05CS100-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, [](((LTLAP10==true))U(<>([]((LTLAP11==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 4698 ms.
FORMULA PhaseVariation-PT-D05CS100-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, <>(<>((LTLAP12==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 5229 ms.
FORMULA PhaseVariation-PT-D05CS100-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, (LTLAP13==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 4972 ms.
FORMULA PhaseVariation-PT-D05CS100-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, [](((LTLAP14==true))U([]((LTLAP15==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 5176 ms.
FORMULA PhaseVariation-PT-D05CS100-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, (LTLAP16==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 4933 ms.
FORMULA PhaseVariation-PT-D05CS100-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, (LTLAP17==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 4693 ms.
FORMULA PhaseVariation-PT-D05CS100-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X((LTLAP18==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 11686 ms.
FORMULA PhaseVariation-PT-D05CS100-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, (LTLAP19==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 4666 ms.
FORMULA PhaseVariation-PT-D05CS100-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, <>((LTLAP20==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 5146 ms.
FORMULA PhaseVariation-PT-D05CS100-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, []((((LTLAP21==true))U((LTLAP22==true)))U(X((LTLAP23==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 2126 ms.
FORMULA PhaseVariation-PT-D05CS100-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1552943605605

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ LTLFireability = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Mar 18, 2019 8:37:34 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Mar 18, 2019 8:37:34 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Mar 18, 2019 8:37:34 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 93 ms
Mar 18, 2019 8:37:34 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 77 places.
Mar 18, 2019 8:37:34 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 677 transitions.
Mar 18, 2019 8:37:34 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 25 ms
Mar 18, 2019 8:37:34 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 184 ms
Mar 18, 2019 8:37:34 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 6 ms
Mar 18, 2019 8:37:34 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 1 ms
Mar 18, 2019 8:37:35 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 677 transitions.
Mar 18, 2019 8:37:35 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 26 place invariants in 20 ms
Mar 18, 2019 8:37:35 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 77 variables to be positive in 227 ms
Mar 18, 2019 8:37:35 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 677 transitions.
Mar 18, 2019 8:37:35 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/677 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 18, 2019 8:37:35 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 48 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 18, 2019 8:37:35 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 677 transitions.
Mar 18, 2019 8:37:35 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 20 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 18, 2019 8:37:37 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 677 transitions.
Mar 18, 2019 8:37:39 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(2/677) took 1713 ms. Total solver calls (SAT/UNSAT): 2025(2025/0)
Mar 18, 2019 8:37:42 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(8/677) took 5238 ms. Total solver calls (SAT/UNSAT): 6048(6048/0)
Mar 18, 2019 8:37:46 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(14/677) took 8821 ms. Total solver calls (SAT/UNSAT): 10035(10035/0)
Mar 18, 2019 8:37:49 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(20/677) took 12220 ms. Total solver calls (SAT/UNSAT): 13986(13986/0)
Mar 18, 2019 8:37:53 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(26/677) took 15621 ms. Total solver calls (SAT/UNSAT): 17901(17901/0)
Mar 18, 2019 8:37:56 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(32/677) took 19019 ms. Total solver calls (SAT/UNSAT): 21780(21780/0)
Mar 18, 2019 8:37:59 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(38/677) took 22272 ms. Total solver calls (SAT/UNSAT): 25623(25623/0)
Mar 18, 2019 8:38:03 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(44/677) took 25563 ms. Total solver calls (SAT/UNSAT): 29430(29430/0)
Mar 18, 2019 8:38:06 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(50/677) took 28886 ms. Total solver calls (SAT/UNSAT): 33201(33201/0)
Mar 18, 2019 8:38:09 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(56/677) took 32097 ms. Total solver calls (SAT/UNSAT): 36936(36936/0)
Mar 18, 2019 8:38:12 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(62/677) took 35323 ms. Total solver calls (SAT/UNSAT): 40635(40635/0)
Mar 18, 2019 8:38:16 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(68/677) took 38569 ms. Total solver calls (SAT/UNSAT): 44298(44298/0)
Mar 18, 2019 8:38:19 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(74/677) took 41777 ms. Total solver calls (SAT/UNSAT): 47925(47925/0)
Mar 18, 2019 8:38:22 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(80/677) took 44973 ms. Total solver calls (SAT/UNSAT): 51516(51516/0)
Mar 18, 2019 8:38:25 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(86/677) took 48119 ms. Total solver calls (SAT/UNSAT): 55071(55071/0)
Mar 18, 2019 8:38:28 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(92/677) took 51228 ms. Total solver calls (SAT/UNSAT): 58590(58590/0)
Mar 18, 2019 8:38:31 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(98/677) took 54250 ms. Total solver calls (SAT/UNSAT): 62073(62073/0)
Mar 18, 2019 8:38:34 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(104/677) took 57347 ms. Total solver calls (SAT/UNSAT): 65520(65520/0)
Mar 18, 2019 8:38:38 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(110/677) took 60577 ms. Total solver calls (SAT/UNSAT): 68931(68931/0)
Mar 18, 2019 8:38:41 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(116/677) took 63980 ms. Total solver calls (SAT/UNSAT): 72306(72306/0)
Mar 18, 2019 8:38:44 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(122/677) took 67007 ms. Total solver calls (SAT/UNSAT): 75645(75645/0)
Mar 18, 2019 8:38:47 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(128/677) took 70108 ms. Total solver calls (SAT/UNSAT): 78948(78948/0)
Mar 18, 2019 8:38:50 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(134/677) took 73149 ms. Total solver calls (SAT/UNSAT): 82215(82215/0)
Mar 18, 2019 8:38:53 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(140/677) took 76214 ms. Total solver calls (SAT/UNSAT): 85446(85446/0)
Mar 18, 2019 8:38:56 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(146/677) took 79298 ms. Total solver calls (SAT/UNSAT): 88641(88641/0)
Mar 18, 2019 8:39:00 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(153/677) took 82703 ms. Total solver calls (SAT/UNSAT): 92323(92323/0)
Mar 18, 2019 8:39:03 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(159/677) took 85746 ms. Total solver calls (SAT/UNSAT): 95440(95440/0)
Mar 18, 2019 8:39:06 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(166/677) took 89119 ms. Total solver calls (SAT/UNSAT): 99031(99031/0)
Mar 18, 2019 8:39:09 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(173/677) took 92431 ms. Total solver calls (SAT/UNSAT): 102573(102573/0)
Mar 18, 2019 8:39:13 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(180/677) took 95642 ms. Total solver calls (SAT/UNSAT): 106066(106066/0)
Mar 18, 2019 8:39:16 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(187/677) took 98834 ms. Total solver calls (SAT/UNSAT): 109510(109510/0)
Mar 18, 2019 8:39:19 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(194/677) took 101940 ms. Total solver calls (SAT/UNSAT): 112905(112905/0)
Mar 18, 2019 8:39:22 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(201/677) took 105088 ms. Total solver calls (SAT/UNSAT): 116251(116251/0)
Mar 18, 2019 8:39:25 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(208/677) took 108267 ms. Total solver calls (SAT/UNSAT): 119548(119548/0)
Mar 18, 2019 8:39:28 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(215/677) took 111303 ms. Total solver calls (SAT/UNSAT): 122796(122796/0)
Mar 18, 2019 8:39:32 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(223/677) took 114690 ms. Total solver calls (SAT/UNSAT): 126448(126448/0)
Mar 18, 2019 8:39:35 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(231/677) took 118046 ms. Total solver calls (SAT/UNSAT): 130036(130036/0)
Mar 18, 2019 8:39:38 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(239/677) took 121413 ms. Total solver calls (SAT/UNSAT): 133560(133560/0)
Mar 18, 2019 8:39:42 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(247/677) took 124578 ms. Total solver calls (SAT/UNSAT): 137020(137020/0)
Mar 18, 2019 8:39:45 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(255/677) took 127630 ms. Total solver calls (SAT/UNSAT): 140416(140416/0)
Mar 18, 2019 8:39:48 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(263/677) took 130683 ms. Total solver calls (SAT/UNSAT): 143748(143748/0)
Mar 18, 2019 8:39:51 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(272/677) took 133963 ms. Total solver calls (SAT/UNSAT): 147420(147420/0)
Mar 18, 2019 8:39:54 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(281/677) took 137294 ms. Total solver calls (SAT/UNSAT): 151011(151011/0)
Mar 18, 2019 8:39:58 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(290/677) took 140603 ms. Total solver calls (SAT/UNSAT): 154521(154521/0)
Mar 18, 2019 8:40:01 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(299/677) took 143763 ms. Total solver calls (SAT/UNSAT): 157950(157950/0)
Mar 18, 2019 8:40:04 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(308/677) took 146917 ms. Total solver calls (SAT/UNSAT): 161298(161298/0)
Mar 18, 2019 8:40:07 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(318/677) took 150263 ms. Total solver calls (SAT/UNSAT): 164923(164923/0)
Mar 18, 2019 8:40:11 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(328/677) took 153488 ms. Total solver calls (SAT/UNSAT): 168448(168448/0)
Mar 18, 2019 8:40:14 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(338/677) took 156622 ms. Total solver calls (SAT/UNSAT): 171873(171873/0)
Mar 18, 2019 8:40:17 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(348/677) took 159707 ms. Total solver calls (SAT/UNSAT): 175198(175198/0)
Mar 18, 2019 8:40:20 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(358/677) took 162853 ms. Total solver calls (SAT/UNSAT): 178423(178423/0)
Mar 18, 2019 8:40:23 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(369/677) took 166026 ms. Total solver calls (SAT/UNSAT): 181855(181855/0)
Mar 18, 2019 8:40:26 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(380/677) took 169157 ms. Total solver calls (SAT/UNSAT): 185166(185166/0)
Mar 18, 2019 8:40:29 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(392/677) took 172391 ms. Total solver calls (SAT/UNSAT): 188640(188640/0)
Mar 18, 2019 8:40:33 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(404/677) took 175546 ms. Total solver calls (SAT/UNSAT): 191970(191970/0)
Mar 18, 2019 8:40:36 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(416/677) took 178625 ms. Total solver calls (SAT/UNSAT): 195156(195156/0)
Mar 18, 2019 8:40:39 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(429/677) took 181894 ms. Total solver calls (SAT/UNSAT): 198445(198445/0)
Mar 18, 2019 8:40:42 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(442/677) took 184930 ms. Total solver calls (SAT/UNSAT): 201565(201565/0)
Mar 18, 2019 8:40:45 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(456/677) took 188072 ms. Total solver calls (SAT/UNSAT): 204736(204736/0)
Mar 18, 2019 8:40:48 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(471/677) took 191167 ms. Total solver calls (SAT/UNSAT): 207916(207916/0)
Mar 18, 2019 8:40:51 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(487/677) took 194342 ms. Total solver calls (SAT/UNSAT): 211060(211060/0)
Mar 18, 2019 8:40:55 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(504/677) took 197460 ms. Total solver calls (SAT/UNSAT): 214120(214120/0)
Mar 18, 2019 8:40:58 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(523/677) took 200589 ms. Total solver calls (SAT/UNSAT): 217198(217198/0)
Mar 18, 2019 8:41:01 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(544/677) took 203717 ms. Total solver calls (SAT/UNSAT): 220180(220180/0)
Mar 18, 2019 8:41:04 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(568/677) took 206812 ms. Total solver calls (SAT/UNSAT): 223048(223048/0)
Mar 18, 2019 8:41:07 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(598/677) took 209840 ms. Total solver calls (SAT/UNSAT): 225823(225823/0)
Mar 18, 2019 8:41:10 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(646/677) took 212863 ms. Total solver calls (SAT/UNSAT): 228391(228391/0)
Mar 18, 2019 8:41:11 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 213645 ms. Total solver calls (SAT/UNSAT): 228826(228826/0)
Mar 18, 2019 8:41:11 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 677 transitions.
Mar 18, 2019 9:12:03 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 1852436 ms. Total solver calls (SAT/UNSAT): 218688(0/218688)
Mar 18, 2019 9:12:03 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 2068751ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PhaseVariation-PT-D05CS100"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3954"
echo " Executing tool itstools"
echo " Input is PhaseVariation-PT-D05CS100, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r107-oct2-155272231200610"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/PhaseVariation-PT-D05CS100.tgz
mv PhaseVariation-PT-D05CS100 execution
cd execution
if [ "LTLFireability" = "GlobalProperties" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
if [ "LTLFireability" = "UpperBounds" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;