About the Execution of ITS-Tools for PermAdmissibility-PT-01
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
2310.370 | 84108.00 | 94346.00 | 187.00 | FTTFTFFTFFFFTFTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fko/mcc2019-input.r107-oct2-155272230900418.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fko/mcc2019-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.......................
=====================================================================
Generated by BenchKit 2-3954
Executing tool itstools
Input is PermAdmissibility-PT-01, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r107-oct2-155272230900418
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 844K
-rw-r--r-- 1 mcc users 4.8K Feb 12 04:10 CTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 12 04:10 CTLCardinality.xml
-rw-r--r-- 1 mcc users 20K Feb 8 03:11 CTLFireability.txt
-rw-r--r-- 1 mcc users 75K Feb 8 03:11 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 10 17:31 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K Mar 10 17:31 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 110 Feb 24 15:05 GlobalProperties.txt
-rw-r--r-- 1 mcc users 348 Feb 24 15:05 GlobalProperties.xml
-rw-r--r-- 1 mcc users 2.9K Feb 5 00:22 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K Feb 5 00:22 LTLCardinality.xml
-rw-r--r-- 1 mcc users 6.1K Feb 4 22:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 22K Feb 4 22:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 5.5K Feb 4 07:55 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 4 07:55 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 22K Feb 1 02:07 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 79K Feb 1 02:07 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 4 22:22 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.7K Feb 4 22:22 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Jan 29 09:34 equiv_col
-rw-r--r-- 1 mcc users 3 Jan 29 09:34 instance
-rw-r--r-- 1 mcc users 6 Jan 29 09:34 iscolored
-rw-r--r-- 1 mcc users 484K Mar 10 17:31 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-PT-01-CTLCardinality-00
FORMULA_NAME PermAdmissibility-PT-01-CTLCardinality-01
FORMULA_NAME PermAdmissibility-PT-01-CTLCardinality-02
FORMULA_NAME PermAdmissibility-PT-01-CTLCardinality-03
FORMULA_NAME PermAdmissibility-PT-01-CTLCardinality-04
FORMULA_NAME PermAdmissibility-PT-01-CTLCardinality-05
FORMULA_NAME PermAdmissibility-PT-01-CTLCardinality-06
FORMULA_NAME PermAdmissibility-PT-01-CTLCardinality-07
FORMULA_NAME PermAdmissibility-PT-01-CTLCardinality-08
FORMULA_NAME PermAdmissibility-PT-01-CTLCardinality-09
FORMULA_NAME PermAdmissibility-PT-01-CTLCardinality-10
FORMULA_NAME PermAdmissibility-PT-01-CTLCardinality-11
FORMULA_NAME PermAdmissibility-PT-01-CTLCardinality-12
FORMULA_NAME PermAdmissibility-PT-01-CTLCardinality-13
FORMULA_NAME PermAdmissibility-PT-01-CTLCardinality-14
FORMULA_NAME PermAdmissibility-PT-01-CTLCardinality-15
=== Now, execution of the tool begins
BK_START 1552929148637
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903111103/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/CTLCardinality.pnml.gal, -t, CGAL, -ctl, /home/mcc/execution/CTLCardinality.ctl], workingDir=/home/mcc/execution]
its-ctl command run as :
/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903111103/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/CTLCardinality.pnml.gal -t CGAL -ctl /home/mcc/execution/CTLCardinality.ctl
No direction supplied, using forward translation only.
Parsed 16 CTL formulae.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,52537,6.97433,243540,2,49937,5,147174,6,0,1098,59698,0
Converting to forward existential form...Done !
original formula: AF((((((((((((aux10_0+aux10_2)+aux10_1)+aux10_4)+aux10_3)+aux10_5)+aux10_6)+aux10_7)<=(((((((aux9_4+aux9_5)+aux9_6)+aux9_7)+aux9_0)+aux9_1)+aux9_2)+aux9_3))&&(c14>=1))&&((((((((aux12_6+aux12_5)+aux12_4)+aux12_3)+aux12_2)+aux12_1)+aux12_0)+aux12_7)>=1))&&((((((aux6_0+aux6_5)+aux6_1)+aux6_4)<=(((((((out8_1+out8_0)+out8_3)+out8_2)+out8_6)+out8_7)+out8_4)+out8_5))||(c13>=3))||(((((((((aux15_2+aux15_1)+aux15_0)+aux15_6)+aux15_5)+aux15_4)+aux15_3)+aux15_7)>=3)&&(c13<=(((((((out6_1+out6_2)+out6_0)+out6_6)+out6_5)+out6_4)+out6_3)+out6_7))))))
=> equivalent forward existential formula: [FwdG(Init,!((((((((((((aux10_0+aux10_2)+aux10_1)+aux10_4)+aux10_3)+aux10_5)+aux10_6)+aux10_7)<=(((((((aux9_4+aux9_5)+aux9_6)+aux9_7)+aux9_0)+aux9_1)+aux9_2)+aux9_3))&&(c14>=1))&&((((((((aux12_6+aux12_5)+aux12_4)+aux12_3)+aux12_2)+aux12_1)+aux12_0)+aux12_7)>=1))&&((((((aux6_0+aux6_5)+aux6_1)+aux6_4)<=(((((((out8_1+out8_0)+out8_3)+out8_2)+out8_6)+out8_7)+out8_4)+out8_5))||(c13>=3))||(((((((((aux15_2+aux15_1)+aux15_0)+aux15_6)+aux15_5)+aux15_4)+aux15_3)+aux15_7)>=3)&&(c13<=(((((((out6_1+out6_2)+out6_0)+out6_6)+out6_5)+out6_4)+out6_3)+out6_7)))))))] = FALSE
(forward)formula 0,0,39.1016,1088480,1,0,22,3.1999e+06,14,3,12220,611327,23
FORMULA PermAdmissibility-PT-01-CTLCardinality-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !
***************************************
original formula: AG(((c20<=c12)||((in1_1+in1_0)<=(in4_6+in4_7))))
=> equivalent forward existential formula: [(FwdU(Init,TRUE) * !(((c20<=c12)||((in1_1+in1_0)<=(in4_6+in4_7)))))] = FALSE
(forward)formula 1,1,39.1322,1089800,1,0,22,3.1999e+06,16,3,12235,611327,23
FORMULA PermAdmissibility-PT-01-CTLCardinality-01 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !
***************************************
original formula: !(EF(((in4_6+in4_7)>=3)))
=> equivalent forward existential formula: [(FwdU(Init,TRUE) * ((in4_6+in4_7)>=3))] = FALSE
(forward)formula 2,1,39.1776,1091120,1,0,22,3.1999e+06,17,3,12238,611327,23
FORMULA PermAdmissibility-PT-01-CTLCardinality-02 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !
***************************************
original formula: E(AX(((((((((aux16_0+aux16_1)+aux16_2)+aux16_3)+aux16_4)+aux16_5)+aux16_6)+aux16_7)<=(((((((out7_1+out7_0)+out7_3)+out7_2)+out7_5)+out7_4)+out7_7)+out7_6))) U ((!((((((((out3_0+out3_1)+out3_6)+out3_7)+out3_2)+out3_3)+out3_4)+out3_5)>=3))&&(c5>=2)))
=> equivalent forward existential formula: [(FwdU(Init,!(EX(!(((((((((aux16_0+aux16_1)+aux16_2)+aux16_3)+aux16_4)+aux16_5)+aux16_6)+aux16_7)<=(((((((out7_1+out7_0)+out7_3)+out7_2)+out7_5)+out7_4)+out7_7)+out7_6)))))) * ((!((((((((out3_0+out3_1)+out3_6)+out3_7)+out3_2)+out3_3)+out3_4)+out3_5)>=3))&&(c5>=2)))] != FALSE
(forward)formula 3,0,39.2427,1091384,1,0,22,3.19992e+06,18,3,12248,611328,23
FORMULA PermAdmissibility-PT-01-CTLCardinality-03 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !
***************************************
original formula: EF(AX((((((((((aux15_2+aux15_1)+aux15_0)+aux15_6)+aux15_5)+aux15_4)+aux15_3)+aux15_7)>=1)&&((((aux7_7+aux7_6)+aux7_3)+aux7_2)<=(((((((aux15_2+aux15_1)+aux15_0)+aux15_6)+aux15_5)+aux15_4)+aux15_3)+aux15_7)))))
=> equivalent forward existential formula: [(FwdU(Init,TRUE) * !(EX(!((((((((((aux15_2+aux15_1)+aux15_0)+aux15_6)+aux15_5)+aux15_4)+aux15_3)+aux15_7)>=1)&&((((aux7_7+aux7_6)+aux7_3)+aux7_2)<=(((((((aux15_2+aux15_1)+aux15_0)+aux15_6)+aux15_5)+aux15_4)+aux15_3)+aux15_7)))))))] != FALSE
Reverse transition relation is NOT exact ! Due to transitions switch9_2_0, switch9_3_0, switch9_4_0, switch9_3_5, switch9_1_5, switch9_2_5, switch9_7_4, switch9_0_5, switch9_6_4, switch9_3_6, switch9_4_6, switch9_1_6, switch9_2_6, switch9_7_5, switch9_0_6, switch9_6_5, switch9_4_7, switch9_3_7, switch9_2_7, switch9_1_7, switch9_0_7, switch9_5_6, switch10_4_0, switch10_3_0, switch10_2_0, switch9_5_7, switch9_2_1, switch9_3_1, switch9_4_1, switch9_5_0, switch9_6_0, switch9_7_0, switch9_1_2, switch9_4_2, switch9_5_1, switch9_6_1, switch9_7_1, switch9_0_2, switch9_1_3, switch9_4_3, switch9_6_2, switch9_5_2, switch9_0_3, switch9_7_2, switch9_2_4, switch9_1_4, switch9_3_4, switch9_6_3, switch9_5_3, switch9_0_4, switch9_7_3, switch10_7_4, switch10_0_5, switch10_6_4, switch10_3_5, switch10_1_5, switch10_2_5, switch10_7_5, switch10_0_6, switch10_6_5, switch10_3_6, switch10_4_6, switch10_1_6, switch10_2_6, switch10_0_7, switch10_5_6, switch10_4_7, switch10_3_7, switch10_2_7, switch10_1_7, switch10_5_7, switch11_4_0, switch11_3_0, switch11_2_0, switch10_5_0, switch10_6_0, switch10_7_0, switch10_2_1, switch10_3_1, switch10_4_1, switch10_5_1, switch10_6_1, switch10_7_1, switch10_0_2, switch10_1_2, switch10_4_2, switch10_6_2, switch10_5_2, switch10_0_3, switch10_7_2, switch10_1_3, switch10_4_3, switch10_6_3, switch10_5_3, switch10_0_4, switch10_7_3, switch10_2_4, switch10_1_4, switch10_3_4, switch11_4_6, switch11_3_6, switch11_2_6, switch11_1_6, switch11_0_6, switch11_7_5, switch11_6_5, switch11_3_5, switch11_2_5, switch11_1_5, switch11_0_5, switch11_7_4, switch11_6_4, switch11_5_7, switch11_3_7, switch11_4_7, switch11_1_7, switch11_2_7, switch11_0_7, switch11_5_6, switch11_1_2, switch11_4_2, switch11_6_1, switch11_5_1, switch11_0_2, switch11_7_1, switch11_2_1, switch11_4_1, switch11_3_1, switch11_6_0, switch11_5_0, switch11_7_0, switch11_1_4, switch11_2_4, switch11_3_4, switch11_5_3, switch11_6_3, switch11_7_3, switch11_0_4, switch11_1_3, switch11_4_3, switch11_5_2, switch11_6_2, switch11_7_2, switch11_0_3, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :64/384/144/592
(forward)formula 4,1,60.2087,1790244,1,0,1174,3.65726e+06,1146,530,19075,1.04994e+06,1148
FORMULA PermAdmissibility-PT-01-CTLCardinality-04 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !
***************************************
original formula: (EG(((((((((out2_0+out2_7)+out2_5)+out2_6)+out2_3)+out2_4)+out2_1)+out2_2)<=(((((((out3_0+out3_1)+out3_6)+out3_7)+out3_2)+out3_3)+out3_4)+out3_5))) + ((((((((out5_1+out5_2)+out5_0)+out5_5)+out5_6)+out5_3)+out5_4)+out5_7)>=3))
=> equivalent forward existential formula: ([FwdG(Init,((((((((out2_0+out2_7)+out2_5)+out2_6)+out2_3)+out2_4)+out2_1)+out2_2)<=(((((((out3_0+out3_1)+out3_6)+out3_7)+out3_2)+out3_3)+out3_4)+out3_5)))] != FALSE + [(Init * ((((((((out5_1+out5_2)+out5_0)+out5_5)+out5_6)+out5_3)+out5_4)+out5_7)>=3))] != FALSE)
Hit Full ! (commute/partial/dont) 464/0/128
(forward)formula 5,0,60.315,1790772,1,0,1176,3.65838e+06,1154,533,19188,1.05078e+06,1151
FORMULA PermAdmissibility-PT-01-CTLCardinality-05 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !
***************************************
original formula: AF((AF((c110>=3)) * AG(((in2_2+in2_3)<=(((((((aux10_0+aux10_2)+aux10_1)+aux10_4)+aux10_3)+aux10_5)+aux10_6)+aux10_7)))))
=> equivalent forward existential formula: [FwdG(Init,!((!(EG(!((c110>=3)))) * !(E(TRUE U !(((in2_2+in2_3)<=(((((((aux10_0+aux10_2)+aux10_1)+aux10_4)+aux10_3)+aux10_5)+aux10_6)+aux10_7))))))))] = FALSE
(forward)formula 6,0,70.089,1891816,1,0,1189,4.44388e+06,1163,541,19358,1.33061e+06,1178
FORMULA PermAdmissibility-PT-01-CTLCardinality-06 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !
***************************************
original formula: EF(EX(!(((((((((aux15_2+aux15_1)+aux15_0)+aux15_6)+aux15_5)+aux15_4)+aux15_3)+aux15_7)<=c13))))
=> equivalent forward existential formula: [(EY(FwdU(Init,TRUE)) * !(((((((((aux15_2+aux15_1)+aux15_0)+aux15_6)+aux15_5)+aux15_4)+aux15_3)+aux15_7)<=c13)))] != FALSE
(forward)formula 7,1,70.1661,1891816,1,0,1191,4.44394e+06,1165,543,19403,1.33068e+06,1180
FORMULA PermAdmissibility-PT-01-CTLCardinality-07 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !
***************************************
original formula: (((c15>=2) + E((out6_5<=aux12_0) U (aux15_2>=2))) * E((out6_2>=2) U !((aux11_5>=1))))
=> equivalent forward existential formula: [(FwdU((Init * ((c15>=2) + E((out6_5<=aux12_0) U (aux15_2>=2)))),(out6_2>=2)) * !((aux11_5>=1)))] != FALSE
(forward)formula 8,0,70.3091,1891816,1,0,1195,4.44946e+06,1179,544,19412,1.33509e+06,1185
FORMULA PermAdmissibility-PT-01-CTLCardinality-08 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !
***************************************
original formula: AF(((aux16_4<=out6_4)&&(aux11_0>=3)))
=> equivalent forward existential formula: [FwdG(Init,!(((aux16_4<=out6_4)&&(aux11_0>=3))))] = FALSE
(forward)formula 9,0,70.4232,1891816,1,0,1195,4.44973e+06,1181,544,19421,1.33815e+06,1186
FORMULA PermAdmissibility-PT-01-CTLCardinality-09 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !
***************************************
original formula: (((aux6_4<=out7_5) + (AX((aux11_2>=1)) * (out8_1<=in4_7))) * AF((out2_2>=1)))
=> equivalent forward existential formula: (([(EY((Init * !((aux6_4<=out7_5)))) * !((aux11_2>=1)))] = FALSE * [((Init * !((aux6_4<=out7_5))) * !((out8_1<=in4_7)))] = FALSE) * [FwdG(Init,!((out2_2>=1)))] = FALSE)
Hit Full ! (commute/partial/dont) 584/0/8
(forward)formula 10,0,70.6074,1891816,1,0,1197,4.45373e+06,1189,547,19463,1.34265e+06,1189
FORMULA PermAdmissibility-PT-01-CTLCardinality-10 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !
***************************************
original formula: (AF((((aux5_1>=1)||(c8<=in3_4))||(!(out5_2>=1)))) * AF(AG((aux9_5>=1))))
=> equivalent forward existential formula: ([FwdG(Init,!((((aux5_1>=1)||(c8<=in3_4))||(!(out5_2>=1)))))] = FALSE * [FwdG(Init,!(!(E(TRUE U !((aux9_5>=1))))))] = FALSE)
(forward)formula 11,0,71.181,1892608,1,0,1200,4.55948e+06,1191,549,19464,1.37042e+06,1195
FORMULA PermAdmissibility-PT-01-CTLCardinality-11 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !
***************************************
original formula: !((AG((out2_1>=3)) + AG(((aux10_0>=2)||(aux16_1<=out6_6)))))
=> equivalent forward existential formula: [(FwdU((Init * !(!(E(TRUE U !((out2_1>=3)))))),TRUE) * !(((aux10_0>=2)||(aux16_1<=out6_6))))] != FALSE
(forward)formula 12,1,71.3497,1892872,1,0,1203,4.56794e+06,1195,551,19475,1.39224e+06,1198
FORMULA PermAdmissibility-PT-01-CTLCardinality-12 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !
***************************************
original formula: EF((((!(c14<=aux9_7))||(!(aux11_4<=aux13_2)))&&(aux14_4>=3)))
=> equivalent forward existential formula: [(FwdU(Init,TRUE) * (((!(c14<=aux9_7))||(!(aux11_4<=aux13_2)))&&(aux14_4>=3)))] != FALSE
(forward)formula 13,0,71.4467,1892872,1,0,1203,4.56817e+06,1196,551,19488,1.39225e+06,1198
FORMULA PermAdmissibility-PT-01-CTLCardinality-13 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !
***************************************
original formula: A(!((aux11_6>=2)) U EG((out4_3<=aux10_6)))
=> equivalent forward existential formula: [((Init * !(EG(!(EG((out4_3<=aux10_6)))))) * !(E(!(EG((out4_3<=aux10_6))) U (!(!((aux11_6>=2))) * !(EG((out4_3<=aux10_6)))))))] != FALSE
(forward)formula 14,1,77.017,2035960,1,0,1260,5.39466e+06,1204,594,19492,1.65388e+06,1323
FORMULA PermAdmissibility-PT-01-CTLCardinality-14 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !
***************************************
original formula: EG((((aux15_2>=1)||(!(out8_0>=2)))||(!((aux14_1<=c18)&&(aux14_6>=1)))))
=> equivalent forward existential formula: [FwdG(Init,(((aux15_2>=1)||(!(out8_0>=2)))||(!((aux14_1<=c18)&&(aux14_6>=1)))))] != FALSE
(forward)formula 15,1,77.1746,2039656,1,0,1260,5.39466e+06,1205,594,19502,1.66386e+06,1324
FORMULA PermAdmissibility-PT-01-CTLCardinality-15 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !
***************************************
BK_STOP 1552929232745
--------------------
content from stderr:
+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ CTLCardinality = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution CTLCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination CTLCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Mar 18, 2019 5:12:32 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Mar 18, 2019 5:12:32 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Mar 18, 2019 5:12:32 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 158 ms
Mar 18, 2019 5:12:32 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 168 places.
Mar 18, 2019 5:12:33 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 592 transitions.
Mar 18, 2019 5:12:33 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 91 ms
Mar 18, 2019 5:12:33 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 336 ms
Mar 18, 2019 5:12:33 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/CTLCardinality.pnml.gal : 5 ms
Mar 18, 2019 5:12:33 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSCTLTools
INFO: Time to serialize properties into /home/mcc/execution/CTLCardinality.ctl : 1 ms
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-PT-01"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3954"
echo " Executing tool itstools"
echo " Input is PermAdmissibility-PT-01, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r107-oct2-155272230900418"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-PT-01.tgz
mv PermAdmissibility-PT-01 execution
cd execution
if [ "CTLCardinality" = "GlobalProperties" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
if [ "CTLCardinality" = "UpperBounds" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;