Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fko/mcc2019-input.r107-oct2-155272230900413.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fko/mcc2019-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................
=====================================================================
Generated by BenchKit 2-3954
Executing tool itstools
Input is PermAdmissibility-COL-50, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r107-oct2-155272230900413
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 216K
-rw-r--r-- 1 mcc users 3.6K Feb 12 04:12 CTLCardinality.txt
-rw-r--r-- 1 mcc users 20K Feb 12 04:11 CTLCardinality.xml
-rw-r--r-- 1 mcc users 3.0K Feb 8 03:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 8 03:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 10 17:31 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K Mar 10 17:31 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 111 Feb 24 15:05 GlobalProperties.txt
-rw-r--r-- 1 mcc users 349 Feb 24 15:05 GlobalProperties.xml
-rw-r--r-- 1 mcc users 2.4K Feb 5 00:24 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K Feb 5 00:24 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 4 22:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 9.1K Feb 4 22:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.2K Feb 4 07:56 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 15K Feb 4 07:56 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.0K Feb 1 02:12 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 1 02:12 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 4 22:22 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 4 22:22 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Jan 29 09:34 equiv_pt
-rw-r--r-- 1 mcc users 3 Jan 29 09:34 instance
-rw-r--r-- 1 mcc users 5 Jan 29 09:34 iscolored
-rw-r--r-- 1 mcc users 54K Mar 10 17:31 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-00
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-01
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-02
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-03
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-04
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-05
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-06
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-07
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-08
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-09
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-10
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-11
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-12
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-13
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-14
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1552929061505

17:11:27.841 [main] ERROR PNML validation - The rng grammar file can't be accessed : www.pnml.org
17:11:27.846 [main] ERROR import - Grammar file errors have been raised, the validation can't be done, process will continue without Grammar validation
Working with output stream class java.io.PrintStream
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903111103/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903111103/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Read [reachable] property : PermAdmissibility-COL-50-ReachabilityCardinality-00 with value :((!(c15_0<=(((((((in2_0+in2_1)+in2_2)+in2_3)+in2_4)+in2_5)+in2_6)+in2_7)))&&((((((((in1_0+in1_1)+in1_2)+in1_3)+in1_4)+in1_5)+in1_6)+in1_7)>=2))
Read [invariant] property : PermAdmissibility-COL-50-ReachabilityCardinality-01 with value :(c16_0<=(((((((in1_0+in1_1)+in1_2)+in1_3)+in1_4)+in1_5)+in1_6)+in1_7))
Read [reachable] property : PermAdmissibility-COL-50-ReachabilityCardinality-02 with value :(c13_0>=3)
Read [reachable] property : PermAdmissibility-COL-50-ReachabilityCardinality-03 with value :(!((((((((out1_0+out1_1)+out1_2)+out1_3)+out1_4)+out1_5)+out1_6)+out1_7)<=(((((((out8_0+out8_1)+out8_2)+out8_3)+out8_4)+out8_5)+out8_6)+out8_7)))
Read [invariant] property : PermAdmissibility-COL-50-ReachabilityCardinality-04 with value :((((((((in4_0+in4_1)+in4_2)+in4_3)+in4_4)+in4_5)+in4_6)+in4_7)>=1)
Read [invariant] property : PermAdmissibility-COL-50-ReachabilityCardinality-05 with value :((((((((out3_0+out3_1)+out3_2)+out3_3)+out3_4)+out3_5)+out3_6)+out3_7)<=c12_0)
Read [reachable] property : PermAdmissibility-COL-50-ReachabilityCardinality-06 with value :((!(((((((((aux13_0+aux13_1)+aux13_2)+aux13_3)+aux13_4)+aux13_5)+aux13_6)+aux13_7)<=c11_0)||((((((((aux16_0+aux16_1)+aux16_2)+aux16_3)+aux16_4)+aux16_5)+aux16_6)+aux16_7)>=3)))&&(!(((((((((out8_0+out8_1)+out8_2)+out8_3)+out8_4)+out8_5)+out8_6)+out8_7)<=(((((((out2_0+out2_1)+out2_2)+out2_3)+out2_4)+out2_5)+out2_6)+out2_7))&&(c5_0>=2))))
Read [invariant] property : PermAdmissibility-COL-50-ReachabilityCardinality-07 with value :((c12_0<=c18_0)||((((((((out8_0+out8_1)+out8_2)+out8_3)+out8_4)+out8_5)+out8_6)+out8_7)<=(((((((out7_0+out7_1)+out7_2)+out7_3)+out7_4)+out7_5)+out7_6)+out7_7)))
Read [reachable] property : PermAdmissibility-COL-50-ReachabilityCardinality-08 with value :(((((((((((out6_0+out6_1)+out6_2)+out6_3)+out6_4)+out6_5)+out6_6)+out6_7)<=(((((((aux6_0+aux6_1)+aux6_2)+aux6_3)+aux6_4)+aux6_5)+aux6_6)+aux6_7))&&((((((((out4_0+out4_1)+out4_2)+out4_3)+out4_4)+out4_5)+out4_6)+out4_7)<=c12_0))&&(((((((((out2_0+out2_1)+out2_2)+out2_3)+out2_4)+out2_5)+out2_6)+out2_7)>=3)&&((((((((aux14_0+aux14_1)+aux14_2)+aux14_3)+aux14_4)+aux14_5)+aux14_6)+aux14_7)>=3)))&&((((((((((aux5_0+aux5_1)+aux5_2)+aux5_3)+aux5_4)+aux5_5)+aux5_6)+aux5_7)<=c7_0)&&(c6_0>=3))&&(!(c13_0<=(((((((aux7_0+aux7_1)+aux7_2)+aux7_3)+aux7_4)+aux7_5)+aux7_6)+aux7_7)))))
Read [reachable] property : PermAdmissibility-COL-50-ReachabilityCardinality-09 with value :(c13_0>=1)
Read [reachable] property : PermAdmissibility-COL-50-ReachabilityCardinality-10 with value :(((((((((aux9_0+aux9_1)+aux9_2)+aux9_3)+aux9_4)+aux9_5)+aux9_6)+aux9_7)>=2)&&((c15_0>=1)&&(((((((((aux15_0+aux15_1)+aux15_2)+aux15_3)+aux15_4)+aux15_5)+aux15_6)+aux15_7)<=c6_0)||((((((((in4_0+in4_1)+in4_2)+in4_3)+in4_4)+in4_5)+in4_6)+in4_7)<=(((((((aux6_0+aux6_1)+aux6_2)+aux6_3)+aux6_4)+aux6_5)+aux6_6)+aux6_7)))))
Read [invariant] property : PermAdmissibility-COL-50-ReachabilityCardinality-11 with value :((((((((aux8_0+aux8_1)+aux8_2)+aux8_3)+aux8_4)+aux8_5)+aux8_6)+aux8_7)<=(((((((in2_0+in2_1)+in2_2)+in2_3)+in2_4)+in2_5)+in2_6)+in2_7))
Read [invariant] property : PermAdmissibility-COL-50-ReachabilityCardinality-12 with value :(!((c7_0>=3)||(((((((((out7_0+out7_1)+out7_2)+out7_3)+out7_4)+out7_5)+out7_6)+out7_7)<=c13_0)&&(c12_0>=1))))
Read [reachable] property : PermAdmissibility-COL-50-ReachabilityCardinality-13 with value :((((((((aux15_0+aux15_1)+aux15_2)+aux15_3)+aux15_4)+aux15_5)+aux15_6)+aux15_7)>=1)
Read [invariant] property : PermAdmissibility-COL-50-ReachabilityCardinality-14 with value :(!((((((((((aux9_0+aux9_1)+aux9_2)+aux9_3)+aux9_4)+aux9_5)+aux9_6)+aux9_7)>=3)&&(c8_0<=(((((((out1_0+out1_1)+out1_2)+out1_3)+out1_4)+out1_5)+out1_6)+out1_7)))&&((c20_0>=1)||((((((((out3_0+out3_1)+out3_2)+out3_3)+out3_4)+out3_5)+out3_6)+out3_7)<=(((((((aux9_0+aux9_1)+aux9_2)+aux9_3)+aux9_4)+aux9_5)+aux9_6)+aux9_7)))))
Read [invariant] property : PermAdmissibility-COL-50-ReachabilityCardinality-15 with value :((((c19_0<=c5_0)&&((((((((out7_0+out7_1)+out7_2)+out7_3)+out7_4)+out7_5)+out7_6)+out7_7)<=(((((((aux9_0+aux9_1)+aux9_2)+aux9_3)+aux9_4)+aux9_5)+aux9_6)+aux9_7)))||(((((((((aux8_0+aux8_1)+aux8_2)+aux8_3)+aux8_4)+aux8_5)+aux8_6)+aux8_7)>=1)||(c9_0>=1)))&&((((((((aux14_0+aux14_1)+aux14_2)+aux14_3)+aux14_4)+aux14_5)+aux14_6)+aux14_7)<=c5_0))
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 1024 rows 208 cols
invariant :2'c15_0 + aux15_0 + aux15_1 + aux15_2 + aux15_3 + aux15_4 + aux15_5 + aux15_6 + aux15_7 + -1'aux14_0 + -1'aux14_1 + -1'aux14_2 + -1'aux14_3 + -1'aux14_4 + -1'aux14_5 + -1'aux14_6 + -1'aux14_7 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + out4_0 + out4_1 + out4_2 + out4_3 + out4_4 + out4_5 + out4_6 + out4_7 + -1'out6_0 + -1'out6_1 + -1'out6_2 + -1'out6_3 + -1'out6_4 + -1'out6_5 + -1'out6_6 + -1'out6_7 + -1'out8_0 + -1'out8_1 + -1'out8_2 + -1'out8_3 + -1'out8_4 + -1'out8_5 + -1'out8_6 + -1'out8_7 = 0
invariant :4'c13_0 + -2'aux9_0 + -2'aux9_2 + -2'aux9_4 + -2'aux10_0 + -2'aux10_2 + -2'aux10_4 + 2'aux11_1 + 2'aux11_3 + 2'aux11_5 + 2'aux11_6 + 2'aux11_7 + -2'aux12_0 + -2'aux12_2 + -2'aux12_4 + 2'in1_1 + 2'in1_3 + 2'in1_5 + 2'in1_6 + 2'in1_7 + -2'in2_0 + -2'in2_2 + -2'in2_4 + 2'in3_1 + 2'in3_3 + 2'in3_5 + 2'in3_6 + 2'in3_7 + -2'in4_0 + -2'in4_2 + -2'in4_4 + 2'aux8_1 + 2'aux8_3 + 2'aux8_5 + 2'aux8_6 + 2'aux8_7 + -2'aux7_0 + -2'aux7_2 + -2'aux7_4 + 2'aux6_1 + 2'aux6_3 + 2'aux6_5 + 2'aux6_6 + 2'aux6_7 + 2'aux5_1 + 2'aux5_3 + 2'aux5_5 + 2'aux5_6 + 2'aux5_7 + -4'c9_0 + -2'c110_0 + -2'aux16_0 + -2'aux16_2 + -2'aux16_4 + -2'aux15_0 + -2'aux15_2 + -2'aux15_4 + -1'aux14_0 + aux14_1 + -1'aux14_2 + aux14_3 + -1'aux14_4 + aux14_5 + aux14_6 + aux14_7 + aux13_0 + 3'aux13_1 + aux13_2 + 3'aux13_3 + aux13_4 + 3'aux13_5 + 3'aux13_6 + 3'aux13_7 + -2'out1_0 + -2'out1_2 + -2'out1_4 + out2_0 + 3'out2_1 + out2_2 + 3'out2_3 + out2_4 + 3'out2_5 + 3'out2_6 + 3'out2_7 + -2'out3_0 + -2'out3_2 + -2'out3_4 + out4_0 + 3'out4_1 + out4_2 + 3'out4_3 + out4_4 + 3'out4_5 + 3'out4_6 + 3'out4_7 + -2'out5_0 + -2'out5_2 + -2'out5_4 + -1'out6_0 + out6_1 + -1'out6_2 + out6_3 + -1'out6_4 + out6_5 + out6_6 + out6_7 + -2'out7_0 + -2'out7_2 + -2'out7_4 + -1'out8_0 + out8_1 + -1'out8_2 + out8_3 + -1'out8_4 + out8_5 + out8_6 + out8_7 = 100
invariant :c18_0 + -1'out2_0 + -1'out2_1 + -1'out2_2 + -1'out2_3 + -1'out2_4 + -1'out2_5 + -1'out2_6 + -1'out2_7 + out4_0 + out4_1 + out4_2 + out4_3 + out4_4 + out4_5 + out4_6 + out4_7 = 0
invariant :in1_0 + in1_1 + in1_2 + in1_3 + in1_4 + in1_5 + in1_6 + in1_7 + -1'in3_0 + -1'in3_1 + -1'in3_2 + -1'in3_3 + -1'in3_4 + -1'in3_5 + -1'in3_6 + -1'in3_7 = 0
invariant :c20_0 + -1'out6_0 + -1'out6_1 + -1'out6_2 + -1'out6_3 + -1'out6_4 + -1'out6_5 + -1'out6_6 + -1'out6_7 + out8_0 + out8_1 + out8_2 + out8_3 + out8_4 + out8_5 + out8_6 + out8_7 = 0
invariant :2'c16_0 + -1'aux15_0 + -1'aux15_1 + -1'aux15_2 + -1'aux15_3 + -1'aux15_4 + -1'aux15_5 + -1'aux15_6 + -1'aux15_7 + 2'c17_0 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 = 0
invariant :-2'c5_0 + c8_0 + in4_0 + in4_1 + in4_2 + in4_3 + in4_4 + in4_5 + in4_6 + in4_7 + -1'aux5_0 + -1'aux5_1 + -1'aux5_2 + -1'aux5_3 + -1'aux5_4 + -1'aux5_5 + -1'aux5_6 + -1'aux5_7 + 2'c9_0 + c110_0 = 0
invariant :-4'c13_0 + 2'aux12_0 + 2'aux12_1 + 2'aux12_2 + 2'aux12_3 + 2'aux12_4 + 2'aux12_5 + 2'aux12_6 + 2'aux12_7 + aux15_0 + aux15_1 + aux15_2 + aux15_3 + aux15_4 + aux15_5 + aux15_6 + aux15_7 + -2'aux13_0 + -2'aux13_1 + -2'aux13_2 + -2'aux13_3 + -2'aux13_4 + -2'aux13_5 + -2'aux13_6 + -2'aux13_7 + 2'c17_0 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 = 0
invariant :aux16_0 + aux16_1 + aux16_2 + aux16_3 + aux16_4 + aux16_5 + aux16_6 + aux16_7 + -2'c17_0 + -2'out2_0 + -2'out2_1 + -2'out2_2 + -2'out2_3 + -2'out2_4 + -2'out2_5 + -2'out2_6 + -2'out2_7 + out6_0 + out6_1 + out6_2 + out6_3 + out6_4 + out6_5 + out6_6 + out6_7 + out8_0 + out8_1 + out8_2 + out8_3 + out8_4 + out8_5 + out8_6 + out8_7 = 0
invariant :2'aux9_0 + 2'aux9_2 + 2'aux9_4 + 2'aux10_0 + 2'aux10_2 + 2'aux10_4 + -2'aux11_1 + -2'aux11_3 + -2'aux11_5 + -2'aux11_6 + -2'aux11_7 + 2'aux12_0 + 2'aux12_2 + 2'aux12_4 + -2'in1_1 + -2'in1_3 + -2'in1_5 + -2'in1_6 + -2'in1_7 + 4'c5_0 + 2'in2_0 + 2'in2_2 + 2'in2_4 + -2'in3_1 + -2'in3_3 + -2'in3_5 + -2'in3_6 + -2'in3_7 + 2'in4_0 + 2'in4_2 + 2'in4_4 + 2'aux8_0 + 2'aux8_2 + 2'aux8_4 + 2'aux7_0 + 2'aux7_2 + 2'aux7_4 + -2'aux6_1 + -2'aux6_3 + -2'aux6_5 + -2'aux6_6 + -2'aux6_7 + 2'aux5_0 + 2'aux5_2 + 2'aux5_4 + 2'c12_0 + 2'aux16_0 + 2'aux16_2 + 2'aux16_4 + 2'aux15_0 + 2'aux15_2 + 2'aux15_4 + aux14_0 + -1'aux14_1 + aux14_2 + -1'aux14_3 + aux14_4 + -1'aux14_5 + -1'aux14_6 + -1'aux14_7 + aux13_0 + -1'aux13_1 + aux13_2 + -1'aux13_3 + aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'aux13_7 + 2'out1_0 + 2'out1_2 + 2'out1_4 + out2_0 + -1'out2_1 + out2_2 + -1'out2_3 + out2_4 + -1'out2_5 + -1'out2_6 + -1'out2_7 + 2'out3_0 + 2'out3_2 + 2'out3_4 + out4_0 + -1'out4_1 + out4_2 + -1'out4_3 + out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 + 2'out5_0 + 2'out5_2 + 2'out5_4 + out6_0 + -1'out6_1 + out6_2 + -1'out6_3 + out6_4 + -1'out6_5 + -1'out6_6 + -1'out6_7 + 2'out7_0 + 2'out7_2 + 2'out7_4 + out8_0 + -1'out8_1 + out8_2 + -1'out8_3 + out8_4 + -1'out8_5 + -1'out8_6 + -1'out8_7 = 100
invariant :2'c5_0 + c6_0 + -1'in3_0 + -1'in3_1 + -1'in3_2 + -1'in3_3 + -1'in3_4 + -1'in3_5 + -1'in3_6 + -1'in3_7 = 0
invariant :c19_0 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 + out6_0 + out6_1 + out6_2 + out6_3 + out6_4 + out6_5 + out6_6 + out6_7 = 0
invariant :2'c13_0 + -2'c5_0 + 2'in3_0 + 2'in3_1 + 2'in3_2 + 2'in3_3 + 2'in3_4 + 2'in3_5 + 2'in3_6 + 2'in3_7 + aux6_0 + aux6_1 + aux6_2 + aux6_3 + aux6_4 + aux6_5 + aux6_6 + aux6_7 + c12_0 + aux13_0 + aux13_1 + aux13_2 + aux13_3 + aux13_4 + aux13_5 + aux13_6 + aux13_7 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + out4_0 + out4_1 + out4_2 + out4_3 + out4_4 + out4_5 + out4_6 + out4_7 = 100
invariant :2'aux9_0 + 2'aux9_1 + 2'aux9_2 + 2'aux9_3 + 2'aux9_4 + 2'aux9_7 + -2'aux10_5 + -2'aux10_6 + -2'aux11_5 + -2'aux11_6 + -2'aux12_5 + -2'aux12_6 + -2'in1_5 + -2'in1_6 + 4'c5_0 + -2'in2_5 + -2'in2_6 + -2'in3_5 + -2'in3_6 + -2'in4_5 + -2'in4_6 + -2'aux8_5 + -2'aux8_6 + -2'aux7_5 + -2'aux7_6 + -2'aux6_5 + -2'aux6_6 + 2'aux5_0 + 2'aux5_1 + 2'aux5_2 + 2'aux5_3 + 2'aux5_4 + 2'aux5_7 + -2'c110_0 + -2'aux16_5 + -2'aux16_6 + -2'aux15_5 + -2'aux15_6 + aux14_0 + aux14_1 + aux14_2 + aux14_3 + aux14_4 + -1'aux14_5 + -1'aux14_6 + aux14_7 + aux13_0 + aux13_1 + aux13_2 + aux13_3 + aux13_4 + -1'aux13_5 + -1'aux13_6 + aux13_7 + -2'out1_5 + -2'out1_6 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + -1'out2_5 + -1'out2_6 + out2_7 + -2'out3_5 + -2'out3_6 + out4_0 + out4_1 + out4_2 + out4_3 + out4_4 + -1'out4_5 + -1'out4_6 + out4_7 + -2'out5_5 + -2'out5_6 + out6_0 + out6_1 + out6_2 + out6_3 + out6_4 + -1'out6_5 + -1'out6_6 + out6_7 + -2'out7_5 + -2'out7_6 + out8_0 + out8_1 + out8_2 + out8_3 + out8_4 + -1'out8_5 + -1'out8_6 + out8_7 = 0
invariant :aux9_5 + aux10_5 + aux11_5 + aux12_5 + in1_5 + in2_5 + in3_5 + in4_5 + aux8_5 + aux7_5 + aux6_5 + aux5_5 + aux16_5 + aux15_5 + aux14_5 + aux13_5 + out1_5 + out2_5 + out3_5 + out4_5 + out5_5 + out6_5 + out7_5 + out8_5 = 50
invariant :aux9_6 + aux10_6 + aux11_6 + aux12_6 + in1_6 + in2_6 + in3_6 + in4_6 + aux8_6 + aux7_6 + aux6_6 + aux5_6 + aux16_6 + aux15_6 + aux14_6 + aux13_6 + out1_6 + out2_6 + out3_6 + out4_6 + out5_6 + out6_6 + out7_6 + out8_6 = 50
invariant :in2_0 + in2_1 + in2_2 + in2_3 + in2_4 + in2_5 + in2_6 + in2_7 + -1'in4_0 + -1'in4_1 + -1'in4_2 + -1'in4_3 + -1'in4_4 + -1'in4_5 + -1'in4_6 + -1'in4_7 = 0
invariant :2'c13_0 + 2'c5_0 + aux5_0 + aux5_1 + aux5_2 + aux5_3 + aux5_4 + aux5_5 + aux5_6 + aux5_7 + c110_0 + 2'c11_0 + 2'c12_0 + aux13_0 + aux13_1 + aux13_2 + aux13_3 + aux13_4 + aux13_5 + aux13_6 + aux13_7 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + out4_0 + out4_1 + out4_2 + out4_3 + out4_4 + out4_5 + out4_6 + out4_7 = 100
invariant :2'c14_0 + aux14_0 + aux14_1 + aux14_2 + aux14_3 + aux14_4 + aux14_5 + aux14_6 + aux14_7 + -1'aux13_0 + -1'aux13_1 + -1'aux13_2 + -1'aux13_3 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'aux13_7 + -1'out2_0 + -1'out2_1 + -1'out2_2 + -1'out2_3 + -1'out2_4 + -1'out2_5 + -1'out2_6 + -1'out2_7 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 + out6_0 + out6_1 + out6_2 + out6_3 + out6_4 + out6_5 + out6_6 + out6_7 + out8_0 + out8_1 + out8_2 + out8_3 + out8_4 + out8_5 + out8_6 + out8_7 = 0
invariant :2'aux9_0 + 2'aux9_1 + 2'aux9_2 + 2'aux9_4 + 2'aux10_0 + 2'aux10_1 + 2'aux10_2 + 2'aux10_4 + -2'aux11_3 + -2'aux11_5 + -2'aux11_6 + -2'aux11_7 + -2'aux12_3 + -2'aux12_5 + -2'aux12_6 + -2'aux12_7 + -2'in1_3 + -2'in1_5 + -2'in1_6 + -2'in1_7 + 8'c5_0 + 2'in2_0 + 2'in2_1 + 2'in2_2 + 2'in2_4 + -2'in3_3 + -2'in3_5 + -2'in3_6 + -2'in3_7 + -2'in4_0 + -2'in4_1 + -2'in4_2 + -4'in4_3 + -2'in4_4 + -4'in4_5 + -4'in4_6 + -4'in4_7 + -2'aux8_3 + -2'aux8_5 + -2'aux8_6 + -2'aux8_7 + -2'aux7_3 + -2'aux7_5 + -2'aux7_6 + -2'aux7_7 + -2'aux6_3 + -2'aux6_5 + -2'aux6_6 + -2'aux6_7 + 4'aux5_0 + 4'aux5_1 + 4'aux5_2 + 2'aux5_3 + 4'aux5_4 + 2'aux5_5 + 2'aux5_6 + 2'aux5_7 + -2'aux16_3 + -2'aux16_5 + -2'aux16_6 + -2'aux16_7 + aux15_0 + aux15_1 + aux15_2 + -1'aux15_3 + aux15_4 + -1'aux15_5 + -1'aux15_6 + -1'aux15_7 + aux14_0 + aux14_1 + aux14_2 + -1'aux14_3 + aux14_4 + -1'aux14_5 + -1'aux14_6 + -1'aux14_7 + aux13_0 + aux13_1 + aux13_2 + -1'aux13_3 + aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'aux13_7 + 2'c17_0 + 2'out1_0 + 2'out1_1 + 2'out1_2 + 2'out1_4 + 2'out2_0 + 2'out2_1 + 2'out2_2 + 2'out2_4 + -2'out3_3 + -2'out3_5 + -2'out3_6 + -2'out3_7 + 2'out4_0 + 2'out4_1 + 2'out4_2 + 2'out4_4 + -2'out5_3 + -2'out5_5 + -2'out5_6 + -2'out5_7 + out6_0 + out6_1 + out6_2 + -1'out6_3 + out6_4 + -1'out6_5 + -1'out6_6 + -1'out6_7 + -2'out7_3 + -2'out7_5 + -2'out7_6 + -2'out7_7 + out8_0 + out8_1 + out8_2 + -1'out8_3 + out8_4 + -1'out8_5 + -1'out8_6 + -1'out8_7 = 0
invariant :aux9_3 + aux10_3 + aux11_3 + aux12_3 + in1_3 + -1'in2_0 + -1'in2_1 + -1'in2_2 + -1'in2_4 + -1'in2_5 + -1'in2_6 + -1'in2_7 + in3_3 + in4_0 + in4_1 + in4_2 + 2'in4_3 + in4_4 + in4_5 + in4_6 + in4_7 + aux8_3 + aux7_3 + aux6_3 + aux5_3 + aux16_3 + aux15_3 + aux14_3 + aux13_3 + -1'out1_0 + -1'out1_1 + -1'out1_2 + -1'out1_4 + -1'out1_5 + -1'out1_6 + -1'out1_7 + out2_0 + out2_1 + out2_2 + 2'out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + out3_3 + out4_3 + out5_3 + out6_3 + out7_3 + out8_3 = 50
invariant :-4'c13_0 + -2'aux9_2 + -2'aux9_4 + -2'aux10_2 + -2'aux10_4 + 2'aux11_0 + 2'aux11_1 + 2'aux11_3 + 2'aux11_5 + 2'aux11_6 + 2'aux11_7 + -2'aux12_2 + -2'aux12_4 + -2'in1_2 + -2'in1_4 + -2'in2_2 + -2'in2_4 + -2'in3_2 + -2'in3_4 + -2'in4_2 + -2'in4_4 + -2'aux8_2 + -2'aux8_4 + -2'aux7_2 + -2'aux7_4 + -2'aux6_2 + -2'aux6_4 + -2'aux5_2 + -2'aux5_4 + -4'c12_0 + -2'aux16_2 + -2'aux16_4 + -2'aux15_2 + -2'aux15_4 + aux14_0 + aux14_1 + -1'aux14_2 + aux14_3 + -1'aux14_4 + aux14_5 + aux14_6 + aux14_7 + -1'aux13_0 + -1'aux13_1 + -3'aux13_2 + -1'aux13_3 + -3'aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'aux13_7 + -2'out1_2 + -2'out1_4 + -1'out2_0 + -1'out2_1 + -3'out2_2 + -1'out2_3 + -3'out2_4 + -1'out2_5 + -1'out2_6 + -1'out2_7 + -2'out3_2 + -2'out3_4 + -1'out4_0 + -1'out4_1 + -3'out4_2 + -1'out4_3 + -3'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 + -2'out5_2 + -2'out5_4 + out6_0 + out6_1 + -1'out6_2 + out6_3 + -1'out6_4 + out6_5 + out6_6 + out6_7 + -2'out7_2 + -2'out7_4 + out8_0 + out8_1 + -1'out8_2 + out8_3 + -1'out8_4 + out8_5 + out8_6 + out8_7 = -200
invariant :aux9_4 + aux10_4 + aux11_4 + aux12_4 + in1_4 + in2_4 + in3_4 + in4_4 + aux8_4 + aux7_4 + aux6_4 + aux5_4 + aux16_4 + aux15_4 + aux14_4 + aux13_4 + out1_4 + out2_4 + out3_4 + out4_4 + out5_4 + out6_4 + out7_4 + out8_4 = 50
invariant :aux9_2 + aux10_2 + aux11_2 + aux12_2 + in1_2 + in2_2 + in3_2 + in4_2 + aux8_2 + aux7_2 + aux6_2 + aux5_2 + aux16_2 + aux15_2 + aux14_2 + aux13_2 + out1_2 + out2_2 + out3_2 + out4_2 + out5_2 + out6_2 + out7_2 + out8_2 = 50
invariant :2'c7_0 + 2'in3_0 + 2'in3_1 + 2'in3_2 + 2'in3_3 + 2'in3_4 + 2'in3_5 + 2'in3_6 + 2'in3_7 + -2'in4_0 + -2'in4_1 + -2'in4_2 + -2'in4_3 + -2'in4_4 + -2'in4_5 + -2'in4_6 + -2'in4_7 + aux5_0 + aux5_1 + aux5_2 + aux5_3 + aux5_4 + aux5_5 + aux5_6 + aux5_7 + -2'c9_0 + -1'c110_0 = 0
invariant :-2'aux9_0 + -2'aux9_1 + -2'aux9_2 + -2'aux9_3 + -2'aux9_4 + 2'aux10_5 + 2'aux10_6 + 2'aux10_7 + 2'aux11_5 + 2'aux11_6 + 2'aux11_7 + 2'aux12_5 + 2'aux12_6 + 2'aux12_7 + 2'in1_5 + 2'in1_6 + 2'in1_7 + -4'c5_0 + 2'in2_5 + 2'in2_6 + 2'in2_7 + 2'in3_5 + 2'in3_6 + 2'in3_7 + 2'in4_5 + 2'in4_6 + 2'in4_7 + 2'aux8_5 + 2'aux8_6 + 2'aux8_7 + 2'aux7_5 + 2'aux7_6 + 2'aux7_7 + 2'aux6_5 + 2'aux6_6 + 2'aux6_7 + -2'aux5_0 + -2'aux5_1 + -2'aux5_2 + -2'aux5_3 + -2'aux5_4 + 2'c110_0 + 2'aux16_5 + 2'aux16_6 + 2'aux16_7 + 2'aux15_5 + 2'aux15_6 + 2'aux15_7 + -1'aux14_0 + -1'aux14_1 + -1'aux14_2 + -1'aux14_3 + -1'aux14_4 + aux14_5 + aux14_6 + aux14_7 + -1'aux13_0 + -1'aux13_1 + -1'aux13_2 + -1'aux13_3 + -1'aux13_4 + aux13_5 + aux13_6 + aux13_7 + 2'out1_5 + 2'out1_6 + 2'out1_7 + -1'out2_0 + -1'out2_1 + -1'out2_2 + -1'out2_3 + -1'out2_4 + out2_5 + out2_6 + out2_7 + 2'out3_5 + 2'out3_6 + 2'out3_7 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + out4_5 + out4_6 + out4_7 + 2'out5_5 + 2'out5_6 + 2'out5_7 + -1'out6_0 + -1'out6_1 + -1'out6_2 + -1'out6_3 + -1'out6_4 + out6_5 + out6_6 + out6_7 + 2'out7_5 + 2'out7_6 + 2'out7_7 + -1'out8_0 + -1'out8_1 + -1'out8_2 + -1'out8_3 + -1'out8_4 + out8_5 + out8_6 + out8_7 = 100
invariant :out1_0 + out1_1 + out1_2 + out1_3 + out1_4 + out1_5 + out1_6 + out1_7 + -1'out2_0 + -1'out2_1 + -1'out2_2 + -1'out2_3 + -1'out2_4 + -1'out2_5 + -1'out2_6 + -1'out2_7 = 0
invariant :out3_0 + out3_1 + out3_2 + out3_3 + out3_4 + out3_5 + out3_6 + out3_7 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 = 0
invariant :out5_0 + out5_1 + out5_2 + out5_3 + out5_4 + out5_5 + out5_6 + out5_7 + -1'out6_0 + -1'out6_1 + -1'out6_2 + -1'out6_3 + -1'out6_4 + -1'out6_5 + -1'out6_6 + -1'out6_7 = 0
invariant :out7_0 + out7_1 + out7_2 + out7_3 + out7_4 + out7_5 + out7_6 + out7_7 + -1'out8_0 + -1'out8_1 + -1'out8_2 + -1'out8_3 + -1'out8_4 + -1'out8_5 + -1'out8_6 + -1'out8_7 = 0
invariant :-4'c5_0 + 2'in4_0 + 2'in4_1 + 2'in4_2 + 2'in4_3 + 2'in4_4 + 2'in4_5 + 2'in4_6 + 2'in4_7 + aux7_0 + aux7_1 + aux7_2 + aux7_3 + aux7_4 + aux7_5 + aux7_6 + aux7_7 + -2'aux5_0 + -2'aux5_1 + -2'aux5_2 + -2'aux5_3 + -2'aux5_4 + -2'aux5_5 + -2'aux5_6 + -2'aux5_7 + 2'c9_0 + c110_0 = 0
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 1024 rows 208 cols
invariant :2'c15_0 + aux15_0 + aux15_1 + aux15_2 + aux15_3 + aux15_4 + aux15_5 + aux15_6 + aux15_7 + -1'aux14_0 + -1'aux14_1 + -1'aux14_2 + -1'aux14_3 + -1'aux14_4 + -1'aux14_5 + -1'aux14_6 + -1'aux14_7 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + out4_0 + out4_1 + out4_2 + out4_3 + out4_4 + out4_5 + out4_6 + out4_7 + -1'out6_0 + -1'out6_1 + -1'out6_2 + -1'out6_3 + -1'out6_4 + -1'out6_5 + -1'out6_6 + -1'out6_7 + -1'out8_0 + -1'out8_1 + -1'out8_2 + -1'out8_3 + -1'out8_4 + -1'out8_5 + -1'out8_6 + -1'out8_7 = 0
invariant :4'c13_0 + -2'aux9_0 + -2'aux9_2 + -2'aux9_4 + -2'aux10_0 + -2'aux10_2 + -2'aux10_4 + 2'aux11_1 + 2'aux11_3 + 2'aux11_5 + 2'aux11_6 + 2'aux11_7 + -2'aux12_0 + -2'aux12_2 + -2'aux12_4 + 2'in1_1 + 2'in1_3 + 2'in1_5 + 2'in1_6 + 2'in1_7 + -2'in2_0 + -2'in2_2 + -2'in2_4 + 2'in3_1 + 2'in3_3 + 2'in3_5 + 2'in3_6 + 2'in3_7 + -2'in4_0 + -2'in4_2 + -2'in4_4 + 2'aux8_1 + 2'aux8_3 + 2'aux8_5 + 2'aux8_6 + 2'aux8_7 + -2'aux7_0 + -2'aux7_2 + -2'aux7_4 + 2'aux6_1 + 2'aux6_3 + 2'aux6_5 + 2'aux6_6 + 2'aux6_7 + 2'aux5_1 + 2'aux5_3 + 2'aux5_5 + 2'aux5_6 + 2'aux5_7 + -4'c9_0 + -2'c110_0 + -2'aux16_0 + -2'aux16_2 + -2'aux16_4 + -2'aux15_0 + -2'aux15_2 + -2'aux15_4 + -1'aux14_0 + aux14_1 + -1'aux14_2 + aux14_3 + -1'aux14_4 + aux14_5 + aux14_6 + aux14_7 + aux13_0 + 3'aux13_1 + aux13_2 + 3'aux13_3 + aux13_4 + 3'aux13_5 + 3'aux13_6 + 3'aux13_7 + -2'out1_0 + -2'out1_2 + -2'out1_4 + out2_0 + 3'out2_1 + out2_2 + 3'out2_3 + out2_4 + 3'out2_5 + 3'out2_6 + 3'out2_7 + -2'out3_0 + -2'out3_2 + -2'out3_4 + out4_0 + 3'out4_1 + out4_2 + 3'out4_3 + out4_4 + 3'out4_5 + 3'out4_6 + 3'out4_7 + -2'out5_0 + -2'out5_2 + -2'out5_4 + -1'out6_0 + out6_1 + -1'out6_2 + out6_3 + -1'out6_4 + out6_5 + out6_6 + out6_7 + -2'out7_0 + -2'out7_2 + -2'out7_4 + -1'out8_0 + out8_1 + -1'out8_2 + out8_3 + -1'out8_4 + out8_5 + out8_6 + out8_7 = 100
invariant :c18_0 + -1'out2_0 + -1'out2_1 + -1'out2_2 + -1'out2_3 + -1'out2_4 + -1'out2_5 + -1'out2_6 + -1'out2_7 + out4_0 + out4_1 + out4_2 + out4_3 + out4_4 + out4_5 + out4_6 + out4_7 = 0
invariant :in1_0 + in1_1 + in1_2 + in1_3 + in1_4 + in1_5 + in1_6 + in1_7 + -1'in3_0 + -1'in3_1 + -1'in3_2 + -1'in3_3 + -1'in3_4 + -1'in3_5 + -1'in3_6 + -1'in3_7 = 0
invariant :c20_0 + -1'out6_0 + -1'out6_1 + -1'out6_2 + -1'out6_3 + -1'out6_4 + -1'out6_5 + -1'out6_6 + -1'out6_7 + out8_0 + out8_1 + out8_2 + out8_3 + out8_4 + out8_5 + out8_6 + out8_7 = 0
invariant :2'c16_0 + -1'aux15_0 + -1'aux15_1 + -1'aux15_2 + -1'aux15_3 + -1'aux15_4 + -1'aux15_5 + -1'aux15_6 + -1'aux15_7 + 2'c17_0 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 = 0
invariant :-2'c5_0 + c8_0 + in4_0 + in4_1 + in4_2 + in4_3 + in4_4 + in4_5 + in4_6 + in4_7 + -1'aux5_0 + -1'aux5_1 + -1'aux5_2 + -1'aux5_3 + -1'aux5_4 + -1'aux5_5 + -1'aux5_6 + -1'aux5_7 + 2'c9_0 + c110_0 = 0
invariant :-4'c13_0 + 2'aux12_0 + 2'aux12_1 + 2'aux12_2 + 2'aux12_3 + 2'aux12_4 + 2'aux12_5 + 2'aux12_6 + 2'aux12_7 + aux15_0 + aux15_1 + aux15_2 + aux15_3 + aux15_4 + aux15_5 + aux15_6 + aux15_7 + -2'aux13_0 + -2'aux13_1 + -2'aux13_2 + -2'aux13_3 + -2'aux13_4 + -2'aux13_5 + -2'aux13_6 + -2'aux13_7 + 2'c17_0 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 = 0
invariant :aux16_0 + aux16_1 + aux16_2 + aux16_3 + aux16_4 + aux16_5 + aux16_6 + aux16_7 + -2'c17_0 + -2'out2_0 + -2'out2_1 + -2'out2_2 + -2'out2_3 + -2'out2_4 + -2'out2_5 + -2'out2_6 + -2'out2_7 + out6_0 + out6_1 + out6_2 + out6_3 + out6_4 + out6_5 + out6_6 + out6_7 + out8_0 + out8_1 + out8_2 + out8_3 + out8_4 + out8_5 + out8_6 + out8_7 = 0
invariant :2'aux9_0 + 2'aux9_2 + 2'aux9_4 + 2'aux10_0 + 2'aux10_2 + 2'aux10_4 + -2'aux11_1 + -2'aux11_3 + -2'aux11_5 + -2'aux11_6 + -2'aux11_7 + 2'aux12_0 + 2'aux12_2 + 2'aux12_4 + -2'in1_1 + -2'in1_3 + -2'in1_5 + -2'in1_6 + -2'in1_7 + 4'c5_0 + 2'in2_0 + 2'in2_2 + 2'in2_4 + -2'in3_1 + -2'in3_3 + -2'in3_5 + -2'in3_6 + -2'in3_7 + 2'in4_0 + 2'in4_2 + 2'in4_4 + 2'aux8_0 + 2'aux8_2 + 2'aux8_4 + 2'aux7_0 + 2'aux7_2 + 2'aux7_4 + -2'aux6_1 + -2'aux6_3 + -2'aux6_5 + -2'aux6_6 + -2'aux6_7 + 2'aux5_0 + 2'aux5_2 + 2'aux5_4 + 2'c12_0 + 2'aux16_0 + 2'aux16_2 + 2'aux16_4 + 2'aux15_0 + 2'aux15_2 + 2'aux15_4 + aux14_0 + -1'aux14_1 + aux14_2 + -1'aux14_3 + aux14_4 + -1'aux14_5 + -1'aux14_6 + -1'aux14_7 + aux13_0 + -1'aux13_1 + aux13_2 + -1'aux13_3 + aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'aux13_7 + 2'out1_0 + 2'out1_2 + 2'out1_4 + out2_0 + -1'out2_1 + out2_2 + -1'out2_3 + out2_4 + -1'out2_5 + -1'out2_6 + -1'out2_7 + 2'out3_0 + 2'out3_2 + 2'out3_4 + out4_0 + -1'out4_1 + out4_2 + -1'out4_3 + out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 + 2'out5_0 + 2'out5_2 + 2'out5_4 + out6_0 + -1'out6_1 + out6_2 + -1'out6_3 + out6_4 + -1'out6_5 + -1'out6_6 + -1'out6_7 + 2'out7_0 + 2'out7_2 + 2'out7_4 + out8_0 + -1'out8_1 + out8_2 + -1'out8_3 + out8_4 + -1'out8_5 + -1'out8_6 + -1'out8_7 = 100
invariant :2'c5_0 + c6_0 + -1'in3_0 + -1'in3_1 + -1'in3_2 + -1'in3_3 + -1'in3_4 + -1'in3_5 + -1'in3_6 + -1'in3_7 = 0
invariant :c19_0 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 + out6_0 + out6_1 + out6_2 + out6_3 + out6_4 + out6_5 + out6_6 + out6_7 = 0
invariant :2'c13_0 + -2'c5_0 + 2'in3_0 + 2'in3_1 + 2'in3_2 + 2'in3_3 + 2'in3_4 + 2'in3_5 + 2'in3_6 + 2'in3_7 + aux6_0 + aux6_1 + aux6_2 + aux6_3 + aux6_4 + aux6_5 + aux6_6 + aux6_7 + c12_0 + aux13_0 + aux13_1 + aux13_2 + aux13_3 + aux13_4 + aux13_5 + aux13_6 + aux13_7 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + out4_0 + out4_1 + out4_2 + out4_3 + out4_4 + out4_5 + out4_6 + out4_7 = 100
invariant :2'aux9_0 + 2'aux9_1 + 2'aux9_2 + 2'aux9_3 + 2'aux9_4 + 2'aux9_7 + -2'aux10_5 + -2'aux10_6 + -2'aux11_5 + -2'aux11_6 + -2'aux12_5 + -2'aux12_6 + -2'in1_5 + -2'in1_6 + 4'c5_0 + -2'in2_5 + -2'in2_6 + -2'in3_5 + -2'in3_6 + -2'in4_5 + -2'in4_6 + -2'aux8_5 + -2'aux8_6 + -2'aux7_5 + -2'aux7_6 + -2'aux6_5 + -2'aux6_6 + 2'aux5_0 + 2'aux5_1 + 2'aux5_2 + 2'aux5_3 + 2'aux5_4 + 2'aux5_7 + -2'c110_0 + -2'aux16_5 + -2'aux16_6 + -2'aux15_5 + -2'aux15_6 + aux14_0 + aux14_1 + aux14_2 + aux14_3 + aux14_4 + -1'aux14_5 + -1'aux14_6 + aux14_7 + aux13_0 + aux13_1 + aux13_2 + aux13_3 + aux13_4 + -1'aux13_5 + -1'aux13_6 + aux13_7 + -2'out1_5 + -2'out1_6 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + -1'out2_5 + -1'out2_6 + out2_7 + -2'out3_5 + -2'out3_6 + out4_0 + out4_1 + out4_2 + out4_3 + out4_4 + -1'out4_5 + -1'out4_6 + out4_7 + -2'out5_5 + -2'out5_6 + out6_0 + out6_1 + out6_2 + out6_3 + out6_4 + -1'out6_5 + -1'out6_6 + out6_7 + -2'out7_5 + -2'out7_6 + out8_0 + out8_1 + out8_2 + out8_3 + out8_4 + -1'out8_5 + -1'out8_6 + out8_7 = 0
invariant :aux9_5 + aux10_5 + aux11_5 + aux12_5 + in1_5 + in2_5 + in3_5 + in4_5 + aux8_5 + aux7_5 + aux6_5 + aux5_5 + aux16_5 + aux15_5 + aux14_5 + aux13_5 + out1_5 + out2_5 + out3_5 + out4_5 + out5_5 + out6_5 + out7_5 + out8_5 = 50
invariant :aux9_6 + aux10_6 + aux11_6 + aux12_6 + in1_6 + in2_6 + in3_6 + in4_6 + aux8_6 + aux7_6 + aux6_6 + aux5_6 + aux16_6 + aux15_6 + aux14_6 + aux13_6 + out1_6 + out2_6 + out3_6 + out4_6 + out5_6 + out6_6 + out7_6 + out8_6 = 50
invariant :in2_0 + in2_1 + in2_2 + in2_3 + in2_4 + in2_5 + in2_6 + in2_7 + -1'in4_0 + -1'in4_1 + -1'in4_2 + -1'in4_3 + -1'in4_4 + -1'in4_5 + -1'in4_6 + -1'in4_7 = 0
invariant :2'c13_0 + 2'c5_0 + aux5_0 + aux5_1 + aux5_2 + aux5_3 + aux5_4 + aux5_5 + aux5_6 + aux5_7 + c110_0 + 2'c11_0 + 2'c12_0 + aux13_0 + aux13_1 + aux13_2 + aux13_3 + aux13_4 + aux13_5 + aux13_6 + aux13_7 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + out4_0 + out4_1 + out4_2 + out4_3 + out4_4 + out4_5 + out4_6 + out4_7 = 100
invariant :2'c14_0 + aux14_0 + aux14_1 + aux14_2 + aux14_3 + aux14_4 + aux14_5 + aux14_6 + aux14_7 + -1'aux13_0 + -1'aux13_1 + -1'aux13_2 + -1'aux13_3 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'aux13_7 + -1'out2_0 + -1'out2_1 + -1'out2_2 + -1'out2_3 + -1'out2_4 + -1'out2_5 + -1'out2_6 + -1'out2_7 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 + out6_0 + out6_1 + out6_2 + out6_3 + out6_4 + out6_5 + out6_6 + out6_7 + out8_0 + out8_1 + out8_2 + out8_3 + out8_4 + out8_5 + out8_6 + out8_7 = 0
invariant :2'aux9_0 + 2'aux9_1 + 2'aux9_2 + 2'aux9_4 + 2'aux10_0 + 2'aux10_1 + 2'aux10_2 + 2'aux10_4 + -2'aux11_3 + -2'aux11_5 + -2'aux11_6 + -2'aux11_7 + -2'aux12_3 + -2'aux12_5 + -2'aux12_6 + -2'aux12_7 + -2'in1_3 + -2'in1_5 + -2'in1_6 + -2'in1_7 + 8'c5_0 + 2'in2_0 + 2'in2_1 + 2'in2_2 + 2'in2_4 + -2'in3_3 + -2'in3_5 + -2'in3_6 + -2'in3_7 + -2'in4_0 + -2'in4_1 + -2'in4_2 + -4'in4_3 + -2'in4_4 + -4'in4_5 + -4'in4_6 + -4'in4_7 + -2'aux8_3 + -2'aux8_5 + -2'aux8_6 + -2'aux8_7 + -2'aux7_3 + -2'aux7_5 + -2'aux7_6 + -2'aux7_7 + -2'aux6_3 + -2'aux6_5 + -2'aux6_6 + -2'aux6_7 + 4'aux5_0 + 4'aux5_1 + 4'aux5_2 + 2'aux5_3 + 4'aux5_4 + 2'aux5_5 + 2'aux5_6 + 2'aux5_7 + -2'aux16_3 + -2'aux16_5 + -2'aux16_6 + -2'aux16_7 + aux15_0 + aux15_1 + aux15_2 + -1'aux15_3 + aux15_4 + -1'aux15_5 + -1'aux15_6 + -1'aux15_7 + aux14_0 + aux14_1 + aux14_2 + -1'aux14_3 + aux14_4 + -1'aux14_5 + -1'aux14_6 + -1'aux14_7 + aux13_0 + aux13_1 + aux13_2 + -1'aux13_3 + aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'aux13_7 + 2'c17_0 + 2'out1_0 + 2'out1_1 + 2'out1_2 + 2'out1_4 + 2'out2_0 + 2'out2_1 + 2'out2_2 + 2'out2_4 + -2'out3_3 + -2'out3_5 + -2'out3_6 + -2'out3_7 + 2'out4_0 + 2'out4_1 + 2'out4_2 + 2'out4_4 + -2'out5_3 + -2'out5_5 + -2'out5_6 + -2'out5_7 + out6_0 + out6_1 + out6_2 + -1'out6_3 + out6_4 + -1'out6_5 + -1'out6_6 + -1'out6_7 + -2'out7_3 + -2'out7_5 + -2'out7_6 + -2'out7_7 + out8_0 + out8_1 + out8_2 + -1'out8_3 + out8_4 + -1'out8_5 + -1'out8_6 + -1'out8_7 = 0
invariant :aux9_3 + aux10_3 + aux11_3 + aux12_3 + in1_3 + -1'in2_0 + -1'in2_1 + -1'in2_2 + -1'in2_4 + -1'in2_5 + -1'in2_6 + -1'in2_7 + in3_3 + in4_0 + in4_1 + in4_2 + 2'in4_3 + in4_4 + in4_5 + in4_6 + in4_7 + aux8_3 + aux7_3 + aux6_3 + aux5_3 + aux16_3 + aux15_3 + aux14_3 + aux13_3 + -1'out1_0 + -1'out1_1 + -1'out1_2 + -1'out1_4 + -1'out1_5 + -1'out1_6 + -1'out1_7 + out2_0 + out2_1 + out2_2 + 2'out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + out3_3 + out4_3 + out5_3 + out6_3 + out7_3 + out8_3 = 50
invariant :-4'c13_0 + -2'aux9_2 + -2'aux9_4 + -2'aux10_2 + -2'aux10_4 + 2'aux11_0 + 2'aux11_1 + 2'aux11_3 + 2'aux11_5 + 2'aux11_6 + 2'aux11_7 + -2'aux12_2 + -2'aux12_4 + -2'in1_2 + -2'in1_4 + -2'in2_2 + -2'in2_4 + -2'in3_2 + -2'in3_4 + -2'in4_2 + -2'in4_4 + -2'aux8_2 + -2'aux8_4 + -2'aux7_2 + -2'aux7_4 + -2'aux6_2 + -2'aux6_4 + -2'aux5_2 + -2'aux5_4 + -4'c12_0 + -2'aux16_2 + -2'aux16_4 + -2'aux15_2 + -2'aux15_4 + aux14_0 + aux14_1 + -1'aux14_2 + aux14_3 + -1'aux14_4 + aux14_5 + aux14_6 + aux14_7 + -1'aux13_0 + -1'aux13_1 + -3'aux13_2 + -1'aux13_3 + -3'aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'aux13_7 + -2'out1_2 + -2'out1_4 + -1'out2_0 + -1'out2_1 + -3'out2_2 + -1'out2_3 + -3'out2_4 + -1'out2_5 + -1'out2_6 + -1'out2_7 + -2'out3_2 + -2'out3_4 + -1'out4_0 + -1'out4_1 + -3'out4_2 + -1'out4_3 + -3'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 + -2'out5_2 + -2'out5_4 + out6_0 + out6_1 + -1'out6_2 + out6_3 + -1'out6_4 + out6_5 + out6_6 + out6_7 + -2'out7_2 + -2'out7_4 + out8_0 + out8_1 + -1'out8_2 + out8_3 + -1'out8_4 + out8_5 + out8_6 + out8_7 = -200
invariant :aux9_4 + aux10_4 + aux11_4 + aux12_4 + in1_4 + in2_4 + in3_4 + in4_4 + aux8_4 + aux7_4 + aux6_4 + aux5_4 + aux16_4 + aux15_4 + aux14_4 + aux13_4 + out1_4 + out2_4 + out3_4 + out4_4 + out5_4 + out6_4 + out7_4 + out8_4 = 50
invariant :aux9_2 + aux10_2 + aux11_2 + aux12_2 + in1_2 + in2_2 + in3_2 + in4_2 + aux8_2 + aux7_2 + aux6_2 + aux5_2 + aux16_2 + aux15_2 + aux14_2 + aux13_2 + out1_2 + out2_2 + out3_2 + out4_2 + out5_2 + out6_2 + out7_2 + out8_2 = 50
invariant :2'c7_0 + 2'in3_0 + 2'in3_1 + 2'in3_2 + 2'in3_3 + 2'in3_4 + 2'in3_5 + 2'in3_6 + 2'in3_7 + -2'in4_0 + -2'in4_1 + -2'in4_2 + -2'in4_3 + -2'in4_4 + -2'in4_5 + -2'in4_6 + -2'in4_7 + aux5_0 + aux5_1 + aux5_2 + aux5_3 + aux5_4 + aux5_5 + aux5_6 + aux5_7 + -2'c9_0 + -1'c110_0 = 0
invariant :-2'aux9_0 + -2'aux9_1 + -2'aux9_2 + -2'aux9_3 + -2'aux9_4 + 2'aux10_5 + 2'aux10_6 + 2'aux10_7 + 2'aux11_5 + 2'aux11_6 + 2'aux11_7 + 2'aux12_5 + 2'aux12_6 + 2'aux12_7 + 2'in1_5 + 2'in1_6 + 2'in1_7 + -4'c5_0 + 2'in2_5 + 2'in2_6 + 2'in2_7 + 2'in3_5 + 2'in3_6 + 2'in3_7 + 2'in4_5 + 2'in4_6 + 2'in4_7 + 2'aux8_5 + 2'aux8_6 + 2'aux8_7 + 2'aux7_5 + 2'aux7_6 + 2'aux7_7 + 2'aux6_5 + 2'aux6_6 + 2'aux6_7 + -2'aux5_0 + -2'aux5_1 + -2'aux5_2 + -2'aux5_3 + -2'aux5_4 + 2'c110_0 + 2'aux16_5 + 2'aux16_6 + 2'aux16_7 + 2'aux15_5 + 2'aux15_6 + 2'aux15_7 + -1'aux14_0 + -1'aux14_1 + -1'aux14_2 + -1'aux14_3 + -1'aux14_4 + aux14_5 + aux14_6 + aux14_7 + -1'aux13_0 + -1'aux13_1 + -1'aux13_2 + -1'aux13_3 + -1'aux13_4 + aux13_5 + aux13_6 + aux13_7 + 2'out1_5 + 2'out1_6 + 2'out1_7 + -1'out2_0 + -1'out2_1 + -1'out2_2 + -1'out2_3 + -1'out2_4 + out2_5 + out2_6 + out2_7 + 2'out3_5 + 2'out3_6 + 2'out3_7 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + out4_5 + out4_6 + out4_7 + 2'out5_5 + 2'out5_6 + 2'out5_7 + -1'out6_0 + -1'out6_1 + -1'out6_2 + -1'out6_3 + -1'out6_4 + out6_5 + out6_6 + out6_7 + 2'out7_5 + 2'out7_6 + 2'out7_7 + -1'out8_0 + -1'out8_1 + -1'out8_2 + -1'out8_3 + -1'out8_4 + out8_5 + out8_6 + out8_7 = 100
invariant :out1_0 + out1_1 + out1_2 + out1_3 + out1_4 + out1_5 + out1_6 + out1_7 + -1'out2_0 + -1'out2_1 + -1'out2_2 + -1'out2_3 + -1'out2_4 + -1'out2_5 + -1'out2_6 + -1'out2_7 = 0
invariant :out3_0 + out3_1 + out3_2 + out3_3 + out3_4 + out3_5 + out3_6 + out3_7 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 = 0
invariant :out5_0 + out5_1 + out5_2 + out5_3 + out5_4 + out5_5 + out5_6 + out5_7 + -1'out6_0 + -1'out6_1 + -1'out6_2 + -1'out6_3 + -1'out6_4 + -1'out6_5 + -1'out6_6 + -1'out6_7 = 0
invariant :out7_0 + out7_1 + out7_2 + out7_3 + out7_4 + out7_5 + out7_6 + out7_7 + -1'out8_0 + -1'out8_1 + -1'out8_2 + -1'out8_3 + -1'out8_4 + -1'out8_5 + -1'out8_6 + -1'out8_7 = 0
invariant :-4'c5_0 + 2'in4_0 + 2'in4_1 + 2'in4_2 + 2'in4_3 + 2'in4_4 + 2'in4_5 + 2'in4_6 + 2'in4_7 + aux7_0 + aux7_1 + aux7_2 + aux7_3 + aux7_4 + aux7_5 + aux7_6 + aux7_7 + -2'aux5_0 + -2'aux5_1 + -2'aux5_2 + -2'aux5_3 + -2'aux5_4 + -2'aux5_5 + -2'aux5_6 + -2'aux5_7 + 2'c9_0 + c110_0 = 0
FORMULA PermAdmissibility-COL-50-ReachabilityCardinality-07 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA PermAdmissibility-COL-50-ReachabilityCardinality-08 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O2, model.c], workingDir=/home/mcc/execution]
Compilation finished in 11148 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 74 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality00==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality00==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality01==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality01==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality02==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality02==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality03==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality03==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality04==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality04==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality05==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality05==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality06==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality06==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality09==true], workingDir=/home/mcc/execution]
LTSmin run took 133843 ms.
Found Violation
FORMULA PermAdmissibility-COL-50-ReachabilityCardinality-09 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality10==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality10==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality11==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality11==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality12==true], workingDir=/home/mcc/execution]
LTSmin run took 27031 ms.
Found Violation
FORMULA PermAdmissibility-COL-50-ReachabilityCardinality-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality13==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality13==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality14==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality14==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality15==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality15==true], workingDir=/home/mcc/execution]
Retrying LTSmin with larger timeout 1800 s
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality00==true], workingDir=/home/mcc/execution]

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ ReachabilityCardinality = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Mar 18, 2019 5:11:03 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Mar 18, 2019 5:11:03 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Mar 18, 2019 5:11:03 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
Mar 18, 2019 5:11:28 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Load time of PNML (colored model parsed with PNMLFW) : 24764 ms
Mar 18, 2019 5:11:28 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 40 places.
Mar 18, 2019 5:11:28 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Computed order using colors.
Mar 18, 2019 5:11:28 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: sort/places :input->aux9,aux10,aux11,aux12,in1,in2,in3,in4,aux8,aux7,aux6,aux5,aux16,aux15,aux14,aux13,out1,out2,out3,out4,out5,out6,out7,out8,
Dot->c16,c15,c14,c13,c5,c6,c7,c8,c9,c110,c11,c12,c17,c18,c19,c20,

Mar 18, 2019 5:11:28 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 16 transitions.
Mar 18, 2019 5:11:28 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Computed order based on color domains.
Mar 18, 2019 5:11:28 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 5 ms
Mar 18, 2019 5:11:28 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 111 ms
Mar 18, 2019 5:11:30 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 173 ms
Mar 18, 2019 5:11:30 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 197 ms
Mar 18, 2019 5:11:30 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 18 ms
Mar 18, 2019 5:11:30 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 2 ms
Mar 18, 2019 5:11:30 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 16 transitions. Expanding to a total of 1200 deterministic transitions.
Mar 18, 2019 5:11:30 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 16 transitions. Expanding to a total of 1200 deterministic transitions.
Mar 18, 2019 5:11:30 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 8 ms.
Mar 18, 2019 5:11:30 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 27 ms.
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 16 in 959 ms.
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-00(UNSAT) depth K=0 took 32 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-01(UNSAT) depth K=0 took 26 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-02(UNSAT) depth K=0 took 14 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-03(UNSAT) depth K=0 took 16 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-04(UNSAT) depth K=0 took 16 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 16 transitions. Expanding to a total of 1200 deterministic transitions.
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 3 ms.
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-05(UNSAT) depth K=0 took 16 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-06(UNSAT) depth K=0 took 16 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-07(UNSAT) depth K=0 took 16 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 31 place invariants in 253 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-08(UNSAT) depth K=0 took 16 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-09(UNSAT) depth K=0 took 19 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-10(UNSAT) depth K=0 took 16 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-11(UNSAT) depth K=0 took 16 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-12(UNSAT) depth K=0 took 14 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-13(UNSAT) depth K=0 took 13 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-14(UNSAT) depth K=0 took 3 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-15(UNSAT) depth K=0 took 1 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-00(UNSAT) depth K=1 took 7 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-01(UNSAT) depth K=1 took 6 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-02(UNSAT) depth K=1 took 12 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-03(UNSAT) depth K=1 took 7 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-04(UNSAT) depth K=1 took 13 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-05(UNSAT) depth K=1 took 7 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-06(UNSAT) depth K=1 took 9 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-07(UNSAT) depth K=1 took 7 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-08(UNSAT) depth K=1 took 7 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-09(UNSAT) depth K=1 took 6 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-10(UNSAT) depth K=1 took 7 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-11(UNSAT) depth K=1 took 17 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-12(UNSAT) depth K=1 took 15 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-13(UNSAT) depth K=1 took 12 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-14(UNSAT) depth K=1 took 11 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-15(UNSAT) depth K=1 took 13 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 31 place invariants in 81 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-00(UNSAT) depth K=2 took 315 ms
Mar 18, 2019 5:11:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-01(UNSAT) depth K=2 took 84 ms
Mar 18, 2019 5:11:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-02(UNSAT) depth K=2 took 120 ms
Mar 18, 2019 5:11:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-03(UNSAT) depth K=2 took 61 ms
Mar 18, 2019 5:11:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-04(UNSAT) depth K=2 took 88 ms
Mar 18, 2019 5:11:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-05(UNSAT) depth K=2 took 76 ms
Mar 18, 2019 5:11:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-06(UNSAT) depth K=2 took 80 ms
Mar 18, 2019 5:11:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-07(UNSAT) depth K=2 took 58 ms
Mar 18, 2019 5:11:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-08(UNSAT) depth K=2 took 47 ms
Mar 18, 2019 5:11:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-09(UNSAT) depth K=2 took 94 ms
Mar 18, 2019 5:11:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-10(UNSAT) depth K=2 took 94 ms
Mar 18, 2019 5:11:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-11(UNSAT) depth K=2 took 67 ms
Mar 18, 2019 5:11:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-12(UNSAT) depth K=2 took 113 ms
Mar 18, 2019 5:11:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-13(UNSAT) depth K=2 took 53 ms
Mar 18, 2019 5:11:33 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-14(UNSAT) depth K=2 took 51 ms
Mar 18, 2019 5:11:33 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-15(UNSAT) depth K=2 took 365 ms
Mar 18, 2019 5:11:33 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 208 variables to be positive in 2496 ms
Mar 18, 2019 5:11:33 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 1024 transitions.
Mar 18, 2019 5:11:33 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/1024 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 18, 2019 5:11:33 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 72 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 18, 2019 5:11:33 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 1024 transitions.
Mar 18, 2019 5:11:33 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 208 variables to be positive in 2090 ms
Mar 18, 2019 5:11:33 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 50 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 18, 2019 5:11:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-00(UNSAT) depth K=3 took 2686 ms
Mar 18, 2019 5:11:49 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-01(UNSAT) depth K=3 took 13139 ms
Mar 18, 2019 5:11:57 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-00
Mar 18, 2019 5:11:57 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-00(SAT) depth K=0 took 23385 ms
Mar 18, 2019 5:12:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-01
Mar 18, 2019 5:12:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-01(SAT) depth K=0 took 4059 ms
Mar 18, 2019 5:12:02 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-02(UNSAT) depth K=3 took 13281 ms
Mar 18, 2019 5:12:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-03(UNSAT) depth K=3 took 1636 ms
Mar 18, 2019 5:12:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-04(UNSAT) depth K=3 took 754 ms
Mar 18, 2019 5:12:05 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-05(UNSAT) depth K=3 took 981 ms
Mar 18, 2019 5:12:09 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-06(UNSAT) depth K=3 took 4054 ms
Mar 18, 2019 5:12:10 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-02
Mar 18, 2019 5:12:10 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-02(SAT) depth K=0 took 9045 ms
Mar 18, 2019 5:12:15 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-03
Mar 18, 2019 5:12:15 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-03(SAT) depth K=0 took 4979 ms
Mar 18, 2019 5:12:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-07(UNSAT) depth K=3 took 10056 ms
Mar 18, 2019 5:12:25 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-04
Mar 18, 2019 5:12:25 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-04(SAT) depth K=0 took 10488 ms
Mar 18, 2019 5:12:29 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-08(UNSAT) depth K=3 took 9213 ms
Mar 18, 2019 5:12:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-09(UNSAT) depth K=3 took 5832 ms
Mar 18, 2019 5:12:37 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-10(UNSAT) depth K=3 took 2536 ms
Mar 18, 2019 5:12:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-05
Mar 18, 2019 5:12:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-05(SAT) depth K=0 took 19580 ms
Mar 18, 2019 5:12:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-11(UNSAT) depth K=3 took 10239 ms
Mar 18, 2019 5:12:49 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-12(UNSAT) depth K=3 took 1352 ms
Mar 18, 2019 5:12:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-13(UNSAT) depth K=3 took 3771 ms
Mar 18, 2019 5:12:54 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-14(UNSAT) depth K=3 took 1157 ms
Mar 18, 2019 5:12:58 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-06
Mar 18, 2019 5:12:58 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-06(SAT) depth K=0 took 13029 ms
Mar 18, 2019 5:13:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-15(UNSAT) depth K=3 took 7744 ms
Mar 18, 2019 5:13:28 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant PermAdmissibility-COL-50-ReachabilityCardinality-07
Mar 18, 2019 5:13:28 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for PermAdmissibility-COL-50-ReachabilityCardinality-07
Mar 18, 2019 5:13:28 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-07(TRUE) depth K=0 took 30193 ms
Mar 18, 2019 5:13:39 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 1024 transitions.
Mar 18, 2019 5:13:50 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-00(UNSAT) depth K=4 took 48437 ms
Mar 18, 2019 5:13:51 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/1024) took 11928 ms. Total solver calls (SAT/UNSAT): 1002(1002/0)
Mar 18, 2019 5:14:03 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(1/1024) took 24166 ms. Total solver calls (SAT/UNSAT): 2003(2003/0)
Mar 18, 2019 5:14:30 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(2/1024) took 51189 ms. Total solver calls (SAT/UNSAT): 3019(3019/0)
Mar 18, 2019 5:14:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate PermAdmissibility-COL-50-ReachabilityCardinality-08
Mar 18, 2019 5:14:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for PermAdmissibility-COL-50-ReachabilityCardinality-08
Mar 18, 2019 5:14:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-08(FALSE) depth K=0 took 73834 ms
Mar 18, 2019 5:14:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-09
Mar 18, 2019 5:14:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-09(SAT) depth K=0 took 1601 ms
Mar 18, 2019 5:14:49 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-10
Mar 18, 2019 5:14:49 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-10(SAT) depth K=0 took 5751 ms
Mar 18, 2019 5:14:56 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(3/1024) took 76654 ms. Total solver calls (SAT/UNSAT): 4021(4021/0)
Mar 18, 2019 5:14:59 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-11
Mar 18, 2019 5:14:59 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-11(SAT) depth K=0 took 10238 ms
Mar 18, 2019 5:15:06 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-12
Mar 18, 2019 5:15:06 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-12(SAT) depth K=0 took 6554 ms
Mar 18, 2019 5:15:09 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(4/1024) took 89921 ms. Total solver calls (SAT/UNSAT): 5035(5035/0)
Mar 18, 2019 5:15:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-13
Mar 18, 2019 5:15:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-13(SAT) depth K=0 took 13137 ms
Mar 18, 2019 5:15:20 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(5/1024) took 101301 ms. Total solver calls (SAT/UNSAT): 6041(6041/0)
SMT solver raised 'unknown', retrying with same input.
Mar 18, 2019 5:15:33 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(6/1024) took 113936 ms. Total solver calls (SAT/UNSAT): 7046(7046/0)
Mar 18, 2019 5:15:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-14
Mar 18, 2019 5:15:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-14(SAT) depth K=0 took 17021 ms
Mar 18, 2019 5:15:45 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(7/1024) took 125696 ms. Total solver calls (SAT/UNSAT): 8044(8044/0)
Mar 18, 2019 5:15:56 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(8/1024) took 137184 ms. Total solver calls (SAT/UNSAT): 9038(9038/0)
Mar 18, 2019 5:15:58 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-01(UNSAT) depth K=4 took 127724 ms
Mar 18, 2019 5:16:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-15
Mar 18, 2019 5:16:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-15(SAT) depth K=0 took 24556 ms
Mar 18, 2019 5:16:07 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(9/1024) took 148300 ms. Total solver calls (SAT/UNSAT): 9988(9988/0)
Mar 18, 2019 5:16:19 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(10/1024) took 159903 ms. Total solver calls (SAT/UNSAT): 10996(10996/0)
Mar 18, 2019 5:16:31 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(11/1024) took 171828 ms. Total solver calls (SAT/UNSAT): 11948(11948/0)
Mar 18, 2019 5:16:43 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(12/1024) took 184331 ms. Total solver calls (SAT/UNSAT): 12954(12954/0)
Mar 18, 2019 5:16:55 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(13/1024) took 195874 ms. Total solver calls (SAT/UNSAT): 13912(13912/0)
Mar 18, 2019 5:17:06 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(14/1024) took 207072 ms. Total solver calls (SAT/UNSAT): 14869(14869/0)
Mar 18, 2019 5:17:17 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(15/1024) took 217669 ms. Total solver calls (SAT/UNSAT): 15817(15817/0)
Mar 18, 2019 5:17:28 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(16/1024) took 229188 ms. Total solver calls (SAT/UNSAT): 16819(16819/0)
Mar 18, 2019 5:17:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(17/1024) took 241294 ms. Total solver calls (SAT/UNSAT): 17820(17820/0)
Mar 18, 2019 5:17:52 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(18/1024) took 253233 ms. Total solver calls (SAT/UNSAT): 18820(18820/0)
Mar 18, 2019 5:18:04 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(19/1024) took 264999 ms. Total solver calls (SAT/UNSAT): 19820(19820/0)
Mar 18, 2019 5:18:19 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(20/1024) took 279854 ms. Total solver calls (SAT/UNSAT): 20822(20822/0)
Mar 18, 2019 5:18:25 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-02(UNSAT) depth K=4 took 147657 ms
Mar 18, 2019 5:18:33 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(21/1024) took 294471 ms. Total solver calls (SAT/UNSAT): 21822(21822/0)
Mar 18, 2019 5:18:49 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(22/1024) took 309706 ms. Total solver calls (SAT/UNSAT): 22821(22821/0)
Mar 18, 2019 5:19:01 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(23/1024) took 321564 ms. Total solver calls (SAT/UNSAT): 23817(23817/0)
Mar 18, 2019 5:19:12 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(24/1024) took 332715 ms. Total solver calls (SAT/UNSAT): 24795(24795/0)
Mar 18, 2019 5:19:18 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(25/1024) took 339130 ms. Total solver calls (SAT/UNSAT): 25352(25352/0)
Mar 18, 2019 5:19:30 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(26/1024) took 350737 ms. Total solver calls (SAT/UNSAT): 26344(26344/0)
Mar 18, 2019 5:19:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(27/1024) took 361270 ms. Total solver calls (SAT/UNSAT): 27280(27280/0)
SMT solver raised 'unknown', retrying with same input.
Mar 18, 2019 5:20:05 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(28/1024) took 386032 ms. Total solver calls (SAT/UNSAT): 28270(28270/0)
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown' twice, overapproximating result to 1.
Mar 18, 2019 5:20:23 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(29/1024) took 404247 ms. Total solver calls (SAT/UNSAT): 28846(28846/0)
Mar 18, 2019 5:20:24 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 404548 ms. Total solver calls (SAT/UNSAT): 28846(28846/0)
Mar 18, 2019 5:20:24 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 1024 transitions.
Mar 18, 2019 5:20:25 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Skipping mayMatrices nes/nds SMT solver raised an error :unknown
java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.computeDoNotAccord(NecessaryEnablingsolver.java:628)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:538)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
Mar 18, 2019 5:20:25 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 535777ms conformant to PINS in folder :/home/mcc/execution
Mar 18, 2019 5:22:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-00
Mar 18, 2019 5:22:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-00(SAT) depth K=1 took 386383 ms
Mar 18, 2019 5:26:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-03(UNSAT) depth K=4 took 462867 ms
Mar 18, 2019 5:30:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-01
Mar 18, 2019 5:30:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-01(SAT) depth K=1 took 489138 ms
Mar 18, 2019 5:35:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-04(UNSAT) depth K=4 took 567613 ms
Mar 18, 2019 5:35:57 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-02
Mar 18, 2019 5:35:57 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-02(SAT) depth K=1 took 320403 ms
Mar 18, 2019 5:39:39 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-05(UNSAT) depth K=4 took 243768 ms
Mar 18, 2019 5:42:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-06(UNSAT) depth K=4 took 141976 ms
Mar 18, 2019 5:44:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-07(UNSAT) depth K=4 took 160210 ms
Mar 18, 2019 5:50:03 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-08(UNSAT) depth K=4 took 321573 ms
Mar 18, 2019 5:50:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-03
Mar 18, 2019 5:50:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-03(SAT) depth K=1 took 846909 ms
Mar 18, 2019 5:51:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-09(UNSAT) depth K=4 took 92938 ms
Mar 18, 2019 5:59:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-10(UNSAT) depth K=4 took 462621 ms
ITS-tools command line returned an error code 137
Mar 18, 2019 6:08:29 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-11(UNSAT) depth K=4 took 550159 ms

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-COL-50"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3954"
echo " Executing tool itstools"
echo " Input is PermAdmissibility-COL-50, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r107-oct2-155272230900413"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-COL-50.tgz
mv PermAdmissibility-COL-50 execution
cd execution
if [ "ReachabilityCardinality" = "GlobalProperties" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;