Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fko/mcc2019-input.r107-oct2-155272230500259.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fko/mcc2019-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................................
=====================================================================
Generated by BenchKit 2-3954
Executing tool itstools
Input is ParamProductionCell-PT-0, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r107-oct2-155272230500259
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 308K
-rw-r--r-- 1 mcc users 3.9K Feb 12 03:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 19K Feb 12 03:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 3.3K Feb 8 02:14 CTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 8 02:14 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 10 17:31 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.8K Mar 10 17:31 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 111 Feb 24 15:05 GlobalProperties.txt
-rw-r--r-- 1 mcc users 349 Feb 24 15:05 GlobalProperties.xml
-rw-r--r-- 1 mcc users 2.8K Feb 5 00:20 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K Feb 5 00:20 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 4 22:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 9.3K Feb 4 22:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K Feb 4 07:17 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 16K Feb 4 07:17 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.6K Feb 1 01:25 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 1 01:25 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 4 22:22 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 4 22:22 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jan 29 09:34 equiv_col
-rw-r--r-- 1 mcc users 2 Jan 29 09:34 instance
-rw-r--r-- 1 mcc users 6 Jan 29 09:34 iscolored
-rw-r--r-- 1 mcc users 144K Mar 10 17:31 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ParamProductionCell-PT-0-LTLFireability-00
FORMULA_NAME ParamProductionCell-PT-0-LTLFireability-01
FORMULA_NAME ParamProductionCell-PT-0-LTLFireability-02
FORMULA_NAME ParamProductionCell-PT-0-LTLFireability-03
FORMULA_NAME ParamProductionCell-PT-0-LTLFireability-04
FORMULA_NAME ParamProductionCell-PT-0-LTLFireability-05
FORMULA_NAME ParamProductionCell-PT-0-LTLFireability-06
FORMULA_NAME ParamProductionCell-PT-0-LTLFireability-07
FORMULA_NAME ParamProductionCell-PT-0-LTLFireability-08
FORMULA_NAME ParamProductionCell-PT-0-LTLFireability-09
FORMULA_NAME ParamProductionCell-PT-0-LTLFireability-10
FORMULA_NAME ParamProductionCell-PT-0-LTLFireability-11
FORMULA_NAME ParamProductionCell-PT-0-LTLFireability-12
FORMULA_NAME ParamProductionCell-PT-0-LTLFireability-13
FORMULA_NAME ParamProductionCell-PT-0-LTLFireability-14
FORMULA_NAME ParamProductionCell-PT-0-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1552922387170

Working with output stream class java.io.PrintStream
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903111103/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903111103/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((X((G(G("((A2U_rot1_rs>=1)&&(robot_right>=1))")))U(X(X("((TU_lift_rs>=1)&&(table_upward>=1))"))))))
Formula 0 simplified : !X(G"((A2U_rot1_rs>=1)&&(robot_right>=1))" U XX"((TU_lift_rs>=1)&&(table_upward>=1))")
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 176 rows 198 cols
invariant :arm2_stop + A2U_ext_rs + A2U_ext_run + A2U_ret_rs + A2U_ret_run + A2L_ext_rs + A2L_ext_run + A2L_ret_rs + A2L_ret_run = 1
invariant :arm2_magnet_off + arm2_magnet_on = 1
invariant :press_stop + PU_lower_rs + PU_lower_run + forge_rs + forge_run + PL_lower_rs + PL_lower_run = 1
invariant :arm2_backward + -1'A2U_ret_rs + -1'A2U_ret_run + -1'A2L_ret_rs + -1'A2L_ret_run = 0
invariant :table_upward + -1'TL_lower_rs + -1'TL_lower_run + -1'TU_lift_rs + -1'TU_lift_run = 0
invariant :robot_stop + A2U_rot1_rs + A2U_rot1_run + A2U_rot2_rs + A2U_rot2_run + A2U_rot3_rs + A2U_rot3_run + A2L_rot1_rs + A2L_rot1_run + A2L_rot2_rs + A2L_rot2_run + A2L_rot3_rs + A2L_rot3_run + A1L_rot1_rs + A1L_rot1_run + A1L_rot2_rs + A1L_rot2_run + A1L_rot3_rs + A1L_rot3_run + A1U_rot1_rs + A1U_rot1_run + A1U_rot2_rs + A1U_rot2_run + A1U_rot3_rs + A1U_rot3_run = 1
invariant :belt1_light_barrier_true + belt1_light_barrier_false = 1
invariant :deposit_belt_idle + deposit_belt_occupied + deposit_belt_empty + DB_in + DB_at_end + DB_out + DB_trans_rs + DB_trans_run + DB_deliver_rs + DB_deliver_run = 1
invariant :arm2_storing + arm2_having_swivel_1 + arm2_waiting_for_swivel_2 + A2U_rotated + A2U_in + A2U_rot1_in + A2U_rot2_in + A2U_rot3_in + A2U_rot1_rs + A2U_rot1_run + A2U_rot2_rs + A2U_rot2_run + A2U_rot3_rs + A2U_rot3_run + A2U_extended + -1'arm2_magnet_on + A2U_ext_rs + A2U_ext_run + A2L_out + A2L_loaded + A2L_ret_rs + A2L_ret_run = 0
invariant :press_upward + -1'forge_rs + -1'forge_run = 0
invariant :arm1_storing + arm1_having_swivel_1 + arm1_waiting_for_swivel_2 + A1L_out + A1L_loaded + arm1_magnet_off + A1L_ret_rs + A1L_ret_run + A1U_rotated + A1U_in + A1U_rot1_in + A1U_rot2_in + A1U_rot3_in + A1U_rot1_rs + A1U_rot1_run + A1U_rot2_rs + A1U_rot2_run + A1U_rot3_rs + A1U_rot3_run + A1U_extendet + A1U_ext_rs + A1U_ext_run = 1
invariant :belt2_start + -1'DB_trans_rs + -1'DB_trans_run + -1'DB_deliver_rs + -1'DB_deliver_run = 0
invariant :c_p2 + c_p1 = 1
invariant :ch_FT_free + ch_FT_full + table_ready_for_unloading + TL_out + TL_in + table_at_load_angle + TL_rot_rs + TL_rot_run + TL_lower_rs + TL_lower_run + TU_in + TU_out + table_at_unload_angle + TU_lift_rs + TU_lift_run + TU_rot_rs + TU_rot_run + FB_in + FB_at_end + FB_out + FB_trans_rs + FB_trans_run + FB_deliver_rs + FB_deliver_run = 1
invariant :p_p2 + p_p1 = 1
invariant :press_up + -1'PL_lower_rs + -1'PL_lower_run = 0
invariant :arm2_release_ext + arm2_retract_ext + arm2_pick_up_ext = 1
invariant :ch_TA1_full + ch_TA1_free + -1'table_ready_for_unloading + -1'arm1_store_free + -1'arm1_having_swivel_2 + A1L_out + A1L_loaded + arm1_magnet_off + A1L_ret_rs + A1L_ret_run + -1'A1U_out + -1'A1U_unloadet + -1'A1U_ret_rs + -1'A1U_ret_run = 0
invariant :belt1_stop + FB_trans_rs + FB_trans_run + FB_deliver_rs + FB_deliver_run = 1
invariant :arm2_forward + -1'A2U_ext_rs + -1'A2U_ext_run + -1'A2L_ext_rs + -1'A2L_ext_run = 0
invariant :ch_CF_free + ch_CF_full + feed_belt_occupied + feed_belt_empty + FB_in + FB_at_end + FB_out + FB_trans_rs + FB_trans_run + FB_deliver_rs + FB_deliver_run = 1
invariant :arm1_magnet_on + arm1_magnet_off = 1
invariant :table_bottom_pos + table_top_pos = 1
invariant :robot_left + -1'A2U_rot2_rs + -1'A2U_rot2_run + -1'A2L_rot1_rs + -1'A2L_rot1_run + -1'A2L_rot2_rs + -1'A2L_rot2_run + -1'A2L_rot3_rs + -1'A2L_rot3_run + -1'A1L_rot1_rs + -1'A1L_rot1_run + -1'A1L_rot2_rs + -1'A1L_rot2_run + -1'A1L_rot3_rs + -1'A1L_rot3_run + -1'A1U_rot3_rs + -1'A1U_rot3_run = 0
invariant :arm1_store_free + arm1_waiting_for_swivel_1 + arm1_having_swivel_2 + A1L_rotated + A1L_in + A1L_rot1_in + A1L_rot2_in + A1L_rot3_in + A1L_rot1_rs + A1L_rot1_run + A1L_rot2_rs + A1L_rot2_run + A1L_rot3_rs + A1L_rot3_run + A1_extended + -1'arm1_magnet_off + A1L_ext_rs + A1L_ext_run + A1U_out + A1U_unloadet + A1U_ret_rs + A1U_ret_run = 0
invariant :arm1_forward + -1'A1L_ext_rs + -1'A1L_ext_run + -1'A1U_ext_rs + -1'A1U_ext_run = 0
invariant :table_ready_for_loading + table_ready_for_unloading + TL_out + TL_in + table_at_load_angle + TL_rot_rs + TL_rot_run + TL_lower_rs + TL_lower_run + TU_in + TU_out + table_at_unload_angle + TU_lift_rs + TU_lift_run + TU_rot_rs + TU_rot_run = 1
invariant :arm2_release_angle + arm1_pick_up_angle + arm1_release_angle + arm2_pick_up_angle = 1
invariant :table_load_angle + table_unload_angle = 1
invariant :arm1_pick_up_ext + arm1_retract_ext + arm1_release_ext = 1
invariant :ch_A1P_full + ch_A1P_free + press_ready_for_unloading + PU_out + blank_forged + PU_in + PU_lower_rs + PU_lower_run + forge_rs + forge_run + PL_in + PL_out + PL_lower_rs + PL_lower_run + -1'arm1_storing + -1'arm1_having_swivel_1 + -1'A1L_out + -1'A1L_loaded + -1'arm1_magnet_off + -1'A1L_ret_rs + -1'A1L_ret_run + A1U_out + A1U_unloadet + A1U_ret_rs + A1U_ret_run = 0
invariant :table_stop_v + TL_lower_rs + TL_lower_run + TU_lift_rs + TU_lift_run = 1
invariant :belt1_start + -1'FB_trans_rs + -1'FB_trans_run + -1'FB_deliver_rs + -1'FB_deliver_run = 0
invariant :press_at_upper_pos + press_at_lower_pos + press_at_middle_pos = 1
invariant :belt2_stop + DB_trans_rs + DB_trans_run + DB_deliver_rs + DB_deliver_run = 1
invariant :ch_A2D_full + ch_A2D_free + deposit_belt_occupied + deposit_belt_empty + DB_in + DB_at_end + DB_out + DB_trans_rs + DB_trans_run + DB_deliver_rs + DB_deliver_run + -1'arm2_storing + -1'arm2_having_swivel_1 + A2U_out + A2U_unloaded + arm2_magnet_on + A2U_ret_rs + A2U_ret_run + -1'A2L_out + -1'A2L_loaded + -1'A2L_ret_rs + -1'A2L_ret_run = 1
invariant :table_stop_h + TL_rot_rs + TL_rot_run + TU_rot_rs + TU_rot_run = 1
invariant :table_right + -1'TL_rot_rs + -1'TL_rot_run + -1'TU_rot_rs + -1'TU_rot_run = 0
invariant :arm1_backward + -1'A1L_ret_rs + -1'A1L_ret_run + -1'A1U_ret_rs + -1'A1U_ret_run = 0
invariant :swivel + -1'arm2_store_free + -1'arm2_waiting_for_swivel_1 + -1'arm2_storing + -1'arm2_waiting_for_swivel_2 + -1'arm1_store_free + -1'arm1_waiting_for_swivel_1 + -1'arm1_storing + -1'arm1_waiting_for_swivel_2 = -1
invariant :ch_DC_full + ch_DC_free + DB_in + DB_at_end + DB_out + DB_trans_rs + DB_trans_run + DB_deliver_rs + DB_deliver_run = 1
invariant :arm1_stop + A1L_ext_rs + A1L_ext_run + A1L_ret_rs + A1L_ret_run + A1U_ext_rs + A1U_ext_run + A1U_ret_rs + A1U_ret_run = 1
invariant :feed_belt_idle + feed_belt_occupied + feed_belt_empty + FB_in + FB_at_end + FB_out + FB_trans_rs + FB_trans_run + FB_deliver_rs + FB_deliver_run = 1
invariant :press_down + -1'PU_lower_rs + -1'PU_lower_run = 0
invariant :robot_right + -1'A2U_rot1_rs + -1'A2U_rot1_run + -1'A2U_rot3_rs + -1'A2U_rot3_run + -1'A1U_rot1_rs + -1'A1U_rot1_run + -1'A1U_rot2_rs + -1'A1U_rot2_run = 0
invariant :belt2_light_barrier_true + belt2_light_barrier_false = 1
invariant :arm2_store_free + arm2_waiting_for_swivel_1 + arm2_having_swivel_2 + A2U_out + A2U_unloaded + arm2_magnet_on + A2U_ret_rs + A2U_ret_run + A2L_rotated + A2L_in + A2L_rot1_in + A2L_rot2_in + A2L_rot3_in + A2L_rot1_rs + A2L_rot1_run + A2L_rot2_rs + A2L_rot2_run + A2L_rot3_rs + A2L_rot3_run + A2L_extended + A2L_ext_rs + A2L_ext_run = 1
invariant :ch_PA2_free + ch_PA2_full + -1'press_ready_for_unloading + -1'arm2_store_free + -1'arm2_having_swivel_2 + -1'A2U_out + -1'A2U_unloaded + -1'arm2_magnet_on + -1'A2U_ret_rs + -1'A2U_ret_run + A2L_out + A2L_loaded + A2L_ret_rs + A2L_ret_run = -1
invariant :press_ready_for_loading + press_ready_for_unloading + PU_out + blank_forged + PU_in + PU_lower_rs + PU_lower_run + forge_rs + forge_run + PL_in + PL_out + PL_lower_rs + PL_lower_run = 1
Reverse transition relation is NOT exact ! Due to transitions PU_lower_Pstart, forge_Pstart, PL_lower_Pstart, TL_rot_Pstart, TL_lower_Pstart, TU_lift_Pstart, TU_rot_Pstart, DB_trans_Pstart, DB_deliver_Pstart, FB_trans_Pstart, FB_deliver_Pstart, arm2_unlock_swivel_1, arm2_unlock_swivel_2, A2U_rot1_Pstop, A2U_rot1_Pstart, A2U_rot2_Pstop, A2U_rot2_Pstart, A2U_rot3_Pstop, A2U_rot3_Pstart, A2U_ext_Pstart, A2U_ret_Pstart, A2L_rot1_Pstop, A2L_rot1_Pstart, A2L_rot2_Pstop, A2L_rot2_Pstart, A2L_rot3_Pstart, A2L_ext_Pstart, A2L_ret_Pstart, arm1_unlock_swivel_1, arm1_unlock_swivel_2, A1L_rot1_Pstop, A1L_rot1_Pstart, A1L_rot2_Pstop, A1L_rot2_Pstart, A1L_rot3_Pstop, A1L_rot3_Pstart, A1L_ext_Pstart, A1L_ret_Pstart, A1U_rot1_Pstart, A1U_rot2_Pstop, A1U_rot2_Pstart, A1U_rot3_Pstop, A1U_rot3_Pstart, A1U_ext_Pstart, A1U_ret_Pstart, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :0/131/45/176
6 unique states visited
6 strongly connected components in search stack
6 transitions explored
6 items max in DFS search stack
516 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,5.20323,167012,1,0,314,545198,382,179,6309,405743,386
an accepting run exists (use option '-e' to print it)
Formula 0 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-0-LTLFireability-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 1 : !((F(F(G(("((A1U_ret_rs>=1)&&(arm1_backward>=1))")U("((arm1_release_angle>=1)&&(A1L_in>=1))"))))))
Formula 1 simplified : !FG("((A1U_ret_rs>=1)&&(arm1_backward>=1))" U "((arm1_release_angle>=1)&&(A1L_in>=1))")
2 unique states visited
2 strongly connected components in search stack
2 transitions explored
2 items max in DFS search stack
10 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,5.30188,170968,1,0,320,558394,398,180,6323,418458,413
an accepting run exists (use option '-e' to print it)
Formula 1 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-0-LTLFireability-01 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 2 : !(("((press_ready_for_loading>=1)&&(ch_A1P_full>=1))"))
Formula 2 simplified : !"((press_ready_for_loading>=1)&&(ch_A1P_full>=1))"
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
0 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,5.30241,170968,1,0,320,558394,401,180,6326,418458,415
an accepting run exists (use option '-e' to print it)
Formula 2 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-0-LTLFireability-02 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 3 : !((X("((A1U_ext_run>=1)&&(arm1_release_ext>=1))")))
Formula 3 simplified : !X"((A1U_ext_run>=1)&&(arm1_release_ext>=1))"
4 unique states visited
4 strongly connected components in search stack
4 transitions explored
4 items max in DFS search stack
1 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,5.30408,171232,1,0,320,558491,404,180,6329,418550,419
an accepting run exists (use option '-e' to print it)
Formula 3 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-0-LTLFireability-03 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 4 : !((("((A2L_rot2_run>=1)&&(arm2_pick_up_angle>=1))")U("((arm2_stop>=1)&&(A2U_rotated>=1))")))
Formula 4 simplified : !("((A2L_rot2_run>=1)&&(arm2_pick_up_angle>=1))" U "((arm2_stop>=1)&&(A2U_rotated>=1))")
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
0 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,5.30506,171496,1,0,320,558491,414,180,6340,418553,423
an accepting run exists (use option '-e' to print it)
Formula 4 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-0-LTLFireability-04 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 5 : !((("((arm1_release_angle>=1)&&(A1L_in>=1))")U(X("(A1L_out>=1)"))))
Formula 5 simplified : !("((arm1_release_angle>=1)&&(A1L_in>=1))" U X"(A1L_out>=1)")
4 unique states visited
4 strongly connected components in search stack
4 transitions explored
4 items max in DFS search stack
0 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,5.30595,171496,1,0,320,558491,419,180,6341,418554,429
an accepting run exists (use option '-e' to print it)
Formula 5 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-0-LTLFireability-05 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 6 : !((G((("(((A2L_rot1_run>=1)&&(arm1_pick_up_angle>=1))&&(robot_left>=1))")U("((A1U_rot1_run>=1)&&(arm1_release_angle>=1))"))U(("((A1U_rot1_in>=1)&&(robot_stop>=1))")U("((arm1_release_angle>=1)&&(A1L_in>=1))")))))
Formula 6 simplified : !G(("(((A2L_rot1_run>=1)&&(arm1_pick_up_angle>=1))&&(robot_left>=1))" U "((A1U_rot1_run>=1)&&(arm1_release_angle>=1))") U ("((A1U_rot1_in>=1)&&(robot_stop>=1))" U "((arm1_release_angle>=1)&&(A1L_in>=1))"))
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
0 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,5.31135,171812,1,0,320,558491,462,180,6389,418559,440
an accepting run exists (use option '-e' to print it)
Formula 6 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-0-LTLFireability-06 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 7 : !((F("((A1U_rot3_rs>=1)&&(robot_left>=1))")))
Formula 7 simplified : !F"((A1U_rot3_rs>=1)&&(robot_left>=1))"
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O2, model.c], workingDir=/home/mcc/execution]
Compilation finished in 1785 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 58 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, <>((LTLAP12==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 154 ms.
FORMULA ParamProductionCell-PT-0-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, (LTLAP13==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 152 ms.
FORMULA ParamProductionCell-PT-0-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, []([](X(((LTLAP14==true))U((LTLAP15==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 107 ms.
FORMULA ParamProductionCell-PT-0-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, <>(<>(<>(((LTLAP16==true))U((LTLAP17==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 237 ms.
FORMULA ParamProductionCell-PT-0-LTLFireability-10 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, [](X(<>([]((LTLAP18==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 189 ms.
FORMULA ParamProductionCell-PT-0-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, X(<>(X([](<>((LTLAP19==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 45850 ms.
FORMULA ParamProductionCell-PT-0-LTLFireability-12 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, [](<>([](X(X((LTLAP20==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 753 ms.
FORMULA ParamProductionCell-PT-0-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, --ltl, ((LTLAP21==true))U([]((LTLAP22==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 585 ms.
FORMULA ParamProductionCell-PT-0-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, --when, --ltl, <>((X([]((LTLAP23==true))))U(X([]((LTLAP24==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
2 unique states visited
2 strongly connected components in search stack
2 transitions explored
2 items max in DFS search stack
3036 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,35.6675,757680,1,0,1596,3.8071e+06,471,835,6391,4.19662e+06,3722
an accepting run exists (use option '-e' to print it)
Formula 7 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-0-LTLFireability-07 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 8 : !(("((PU_lower_run>=1)&&(press_at_lower_pos>=1))"))
Formula 8 simplified : !"((PU_lower_run>=1)&&(press_at_lower_pos>=1))"
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
0 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,35.668,757680,1,0,1596,3.8071e+06,474,835,6394,4.19662e+06,3724
an accepting run exists (use option '-e' to print it)
Formula 8 is FALSE accepting run found.
FORMULA ParamProductionCell-PT-0-LTLFireability-08 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 9 : !((G(G(X(("(((A1L_ext_run>=1)&&(arm1_retract_ext>=1))&&(arm1_forward>=1))")U("((arm1_pick_up_angle>=1)&&(A2L_in>=1))"))))))
Formula 9 simplified : !GX("(((A1L_ext_run>=1)&&(arm1_retract_ext>=1))&&(arm1_forward>=1))" U "((arm1_pick_up_angle>=1)&&(A2L_in>=1))")
LTSmin run took 591 ms.
FORMULA ParamProductionCell-PT-0-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1552922450789

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ LTLFireability = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Mar 18, 2019 3:19:48 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Mar 18, 2019 3:19:48 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Mar 18, 2019 3:19:48 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 47 ms
Mar 18, 2019 3:19:48 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 198 places.
Mar 18, 2019 3:19:48 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 176 transitions.
Mar 18, 2019 3:19:48 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 12 ms
Mar 18, 2019 3:19:48 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 52 ms
Mar 18, 2019 3:19:48 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 3 ms
Mar 18, 2019 3:19:48 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 1 ms
Mar 18, 2019 3:19:49 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 176 transitions.
Mar 18, 2019 3:19:49 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 49 place invariants in 43 ms
Mar 18, 2019 3:19:49 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 198 variables to be positive in 271 ms
Mar 18, 2019 3:19:49 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 176 transitions.
Mar 18, 2019 3:19:49 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/176 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 18, 2019 3:19:49 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 7 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 18, 2019 3:19:49 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 176 transitions.
Mar 18, 2019 3:19:49 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 7 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 18, 2019 3:19:52 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 176 transitions.
Mar 18, 2019 3:19:52 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/176) took 34 ms. Total solver calls (SAT/UNSAT): 28(13/15)
Mar 18, 2019 3:19:55 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(18/176) took 3091 ms. Total solver calls (SAT/UNSAT): 438(234/204)
Mar 18, 2019 3:19:58 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(127/176) took 6093 ms. Total solver calls (SAT/UNSAT): 3262(978/2284)
Mar 18, 2019 3:19:59 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 7028 ms. Total solver calls (SAT/UNSAT): 3968(1099/2869)
Mar 18, 2019 3:19:59 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 176 transitions.
Mar 18, 2019 3:19:59 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 52 ms. Total solver calls (SAT/UNSAT): 55(0/55)
Mar 18, 2019 3:19:59 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 10859ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ParamProductionCell-PT-0"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3954"
echo " Executing tool itstools"
echo " Input is ParamProductionCell-PT-0, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r107-oct2-155272230500259"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ParamProductionCell-PT-0.tgz
mv ParamProductionCell-PT-0 execution
cd execution
if [ "LTLFireability" = "GlobalProperties" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
if [ "LTLFireability" = "UpperBounds" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;