Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2019-input.r096-smll-155246587300215.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2019-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
....................
=====================================================================
Generated by BenchKit 2-3957
Executing tool itstools
Input is LamportFastMutEx-PT-5, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r096-smll-155246587300215
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 472K
-rw-r--r-- 1 mcc users 8.5K Feb 11 22:45 CTLCardinality.txt
-rw-r--r-- 1 mcc users 38K Feb 11 22:45 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.5K Feb 7 23:34 CTLFireability.txt
-rw-r--r-- 1 mcc users 40K Feb 7 23:34 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 10 17:31 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Mar 10 17:31 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 108 Feb 24 15:05 GlobalProperties.txt
-rw-r--r-- 1 mcc users 346 Feb 24 15:05 GlobalProperties.xml
-rw-r--r-- 1 mcc users 5.4K Feb 5 00:11 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Feb 5 00:11 LTLCardinality.xml
-rw-r--r-- 1 mcc users 6.1K Feb 4 22:36 LTLFireability.txt
-rw-r--r-- 1 mcc users 26K Feb 4 22:36 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.8K Feb 4 06:23 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 32K Feb 4 06:23 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Jan 31 23:53 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 51K Jan 31 23:53 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.7K Feb 4 22:21 UpperBounds.txt
-rw-r--r-- 1 mcc users 6.5K Feb 4 22:21 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Jan 29 09:34 equiv_col
-rw-r--r-- 1 mcc users 2 Jan 29 09:34 instance
-rw-r--r-- 1 mcc users 6 Jan 29 09:34 iscolored
-rw-r--r-- 1 mcc users 152K Mar 10 17:31 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-00
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-01
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-02
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-03
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-04
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-05
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-06
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-07
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-08
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-09
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-10
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-11
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-12
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-13
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-14
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1552787119417

Working with output stream class java.io.PrintStream
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-01 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903111103/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903111103/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Read [invariant] property : LamportFastMutEx-PT-5-ReachabilityCardinality-00 with value :((!((((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)+P_setx_3_5)>=3))||(!(((((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)+P_setbi_24_5)>=2)&&((((((((((((((((((((((((((((((((((((P_wait_0_0+P_wait_0_1)+P_wait_0_2)+P_wait_0_3)+P_wait_0_4)+P_wait_0_5)+P_wait_1_0)+P_wait_1_1)+P_wait_1_2)+P_wait_1_3)+P_wait_1_4)+P_wait_1_5)+P_wait_2_0)+P_wait_2_1)+P_wait_2_2)+P_wait_2_3)+P_wait_2_4)+P_wait_2_5)+P_wait_3_0)+P_wait_3_1)+P_wait_3_2)+P_wait_3_3)+P_wait_3_4)+P_wait_3_5)+P_wait_4_0)+P_wait_4_1)+P_wait_4_2)+P_wait_4_3)+P_wait_4_4)+P_wait_4_5)+P_wait_5_0)+P_wait_5_1)+P_wait_5_2)+P_wait_5_3)+P_wait_5_4)+P_wait_5_5)<=(((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)))))
Read [reachable] property : LamportFastMutEx-PT-5-ReachabilityCardinality-02 with value :((((((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)+P_awaity_5)>=3)&&(((((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)>=3)&&((((((P_await_13_0+P_await_13_1)+P_await_13_2)+P_await_13_3)+P_await_13_4)+P_await_13_5)>=1)))&&(((((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)+P_ify0_4_5)<=(((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)+P_setx_3_5))||((((((((((((((((((((((((((((((((((((P_wait_0_0+P_wait_0_1)+P_wait_0_2)+P_wait_0_3)+P_wait_0_4)+P_wait_0_5)+P_wait_1_0)+P_wait_1_1)+P_wait_1_2)+P_wait_1_3)+P_wait_1_4)+P_wait_1_5)+P_wait_2_0)+P_wait_2_1)+P_wait_2_2)+P_wait_2_3)+P_wait_2_4)+P_wait_2_5)+P_wait_3_0)+P_wait_3_1)+P_wait_3_2)+P_wait_3_3)+P_wait_3_4)+P_wait_3_5)+P_wait_4_0)+P_wait_4_1)+P_wait_4_2)+P_wait_4_3)+P_wait_4_4)+P_wait_4_5)+P_wait_5_0)+P_wait_5_1)+P_wait_5_2)+P_wait_5_3)+P_wait_5_4)+P_wait_5_5)<=(((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5))))
Read [invariant] property : LamportFastMutEx-PT-5-ReachabilityCardinality-03 with value :((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)<=(((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)+P_setbi_24_5))
Read [reachable] property : LamportFastMutEx-PT-5-ReachabilityCardinality-04 with value :(((((((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)+P_ify0_4_5)>=2)||((((((P_CS_21_0+P_CS_21_1)+P_CS_21_2)+P_CS_21_3)+P_CS_21_4)+P_CS_21_5)>=2))&&(((((((((((((((((((((((((((((((((((((P_done_0_0+P_done_0_1)+P_done_0_2)+P_done_0_3)+P_done_0_4)+P_done_0_5)+P_done_1_0)+P_done_1_1)+P_done_1_2)+P_done_1_3)+P_done_1_4)+P_done_1_5)+P_done_2_0)+P_done_2_1)+P_done_2_2)+P_done_2_3)+P_done_2_4)+P_done_2_5)+P_done_3_0)+P_done_3_1)+P_done_3_2)+P_done_3_3)+P_done_3_4)+P_done_3_5)+P_done_4_0)+P_done_4_1)+P_done_4_2)+P_done_4_3)+P_done_4_4)+P_done_4_5)+P_done_5_0)+P_done_5_1)+P_done_5_2)+P_done_5_3)+P_done_5_4)+P_done_5_5)<=(((((P_CS_21_0+P_CS_21_1)+P_CS_21_2)+P_CS_21_3)+P_CS_21_4)+P_CS_21_5))||((((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)>=1)))&&(((((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)<=(((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5))&&(!((((((((((((((((((((((((((((((((((((P_done_0_0+P_done_0_1)+P_done_0_2)+P_done_0_3)+P_done_0_4)+P_done_0_5)+P_done_1_0)+P_done_1_1)+P_done_1_2)+P_done_1_3)+P_done_1_4)+P_done_1_5)+P_done_2_0)+P_done_2_1)+P_done_2_2)+P_done_2_3)+P_done_2_4)+P_done_2_5)+P_done_3_0)+P_done_3_1)+P_done_3_2)+P_done_3_3)+P_done_3_4)+P_done_3_5)+P_done_4_0)+P_done_4_1)+P_done_4_2)+P_done_4_3)+P_done_4_4)+P_done_4_5)+P_done_5_0)+P_done_5_1)+P_done_5_2)+P_done_5_3)+P_done_5_4)+P_done_5_5)>=3))))
Read [reachable] property : LamportFastMutEx-PT-5-ReachabilityCardinality-05 with value :((((((((((((P_b_0_false+P_b_0_true)+P_b_1_false)+P_b_1_true)+P_b_2_false)+P_b_2_true)+P_b_3_false)+P_b_3_true)+P_b_4_false)+P_b_4_true)+P_b_5_false)+P_b_5_true)<=(((((((((((((((((((((((((((((((((((P_wait_0_0+P_wait_0_1)+P_wait_0_2)+P_wait_0_3)+P_wait_0_4)+P_wait_0_5)+P_wait_1_0)+P_wait_1_1)+P_wait_1_2)+P_wait_1_3)+P_wait_1_4)+P_wait_1_5)+P_wait_2_0)+P_wait_2_1)+P_wait_2_2)+P_wait_2_3)+P_wait_2_4)+P_wait_2_5)+P_wait_3_0)+P_wait_3_1)+P_wait_3_2)+P_wait_3_3)+P_wait_3_4)+P_wait_3_5)+P_wait_4_0)+P_wait_4_1)+P_wait_4_2)+P_wait_4_3)+P_wait_4_4)+P_wait_4_5)+P_wait_5_0)+P_wait_5_1)+P_wait_5_2)+P_wait_5_3)+P_wait_5_4)+P_wait_5_5))
Read [reachable] property : LamportFastMutEx-PT-5-ReachabilityCardinality-06 with value :((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)>=3)
Read [reachable] property : LamportFastMutEx-PT-5-ReachabilityCardinality-07 with value :((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)>=2)
Read [reachable] property : LamportFastMutEx-PT-5-ReachabilityCardinality-08 with value :((P_wait_1_4>=1)&&(P_awaity_2>=1))
Read [reachable] property : LamportFastMutEx-PT-5-ReachabilityCardinality-09 with value :(((!(P_wait_2_3>=3))||((P_done_5_1>=2)||(P_done_5_1<=P_done_2_5)))&&(P_b_0_true>=2))
Read [invariant] property : LamportFastMutEx-PT-5-ReachabilityCardinality-10 with value :(P_done_3_3<=P_ify0_4_0)
Read [invariant] property : LamportFastMutEx-PT-5-ReachabilityCardinality-11 with value :(!(P_ify0_4_5>=3))
Read [invariant] property : LamportFastMutEx-PT-5-ReachabilityCardinality-12 with value :((!((P_fordo_12_1>=2)&&(P_b_0_true>=3)))||(((P_ify0_4_1<=P_await_13_1)&&(P_done_5_3<=P_wait_5_2))&&(P_done_5_3>=2)))
Read [reachable] property : LamportFastMutEx-PT-5-ReachabilityCardinality-13 with value :(P_done_0_3>=3)
Read [reachable] property : LamportFastMutEx-PT-5-ReachabilityCardinality-14 with value :((P_wait_4_4>=1)&&(!((P_done_0_3<=P_fordo_12_5)||(P_CS_21_5>=3))))
Read [invariant] property : LamportFastMutEx-PT-5-ReachabilityCardinality-15 with value :((!((P_ify0_4_4>=2)||(P_b_5_true>=1)))||(!((P_CS_21_3>=2)&&(P_done_3_1>=2))))
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 246
// Phase 1: matrix 246 rows 174 cols
invariant :P_start_1_1 + P_setx_3_1 + P_setbi_5_1 + P_ify0_4_1 + P_sety_9_1 + P_ifxi_10_1 + P_setbi_11_1 + P_fordo_12_1 + P_await_13_1 + P_ifyi_15_1 + P_awaity_1 + P_CS_21_1 + P_setbi_24_1 = 1
invariant :P_wait_1_5 + -1'P_await_13_1 + P_done_1_5 = 0
invariant :P_wait_1_0 + P_done_1_0 = 0
invariant :P_wait_1_3 + -1'P_await_13_1 + P_done_1_3 = 0
invariant :P_wait_2_1 + -1'P_await_13_2 + P_done_2_1 = 0
invariant :P_wait_5_5 + -1'P_await_13_5 + P_done_5_5 = 0
invariant :P_wait_3_5 + -1'P_await_13_3 + P_done_3_5 = 0
invariant :P_wait_0_5 + -1'P_await_13_0 + P_done_0_5 = 0
invariant :P_wait_4_1 + -1'P_await_13_4 + P_done_4_1 = 0
invariant :P_wait_5_1 + -1'P_await_13_5 + P_done_5_1 = 0
invariant :P_wait_1_4 + -1'P_await_13_1 + P_done_1_4 = 0
invariant :y_0 + y_1 + y_2 + y_3 + y_4 + y_5 = 1
invariant :P_b_1_false + P_b_1_true = 1
invariant :P_wait_2_4 + -1'P_await_13_2 + P_done_2_4 = 0
invariant :P_wait_3_2 + -1'P_await_13_3 + P_done_3_2 = 0
invariant :P_wait_4_2 + -1'P_await_13_4 + P_done_4_2 = 0
invariant :P_wait_4_5 + -1'P_await_13_4 + P_done_4_5 = 0
invariant :P_start_1_5 + P_setx_3_5 + P_setbi_5_5 + P_ify0_4_5 + P_sety_9_5 + P_ifxi_10_5 + P_setbi_11_5 + P_fordo_12_5 + P_await_13_5 + P_ifyi_15_5 + P_awaity_5 + P_CS_21_5 + P_setbi_24_5 = 1
invariant :P_wait_5_0 + P_done_5_0 = 0
invariant :P_wait_3_4 + -1'P_await_13_3 + P_done_3_4 = 0
invariant :P_start_1_4 + P_setx_3_4 + P_setbi_5_4 + P_ify0_4_4 + P_sety_9_4 + P_ifxi_10_4 + P_setbi_11_4 + P_fordo_12_4 + P_await_13_4 + P_ifyi_15_4 + P_awaity_4 + P_CS_21_4 + P_setbi_24_4 = 1
invariant :P_wait_4_3 + -1'P_await_13_4 + P_done_4_3 = 0
invariant :P_wait_3_3 + -1'P_await_13_3 + P_done_3_3 = 0
invariant :P_wait_5_3 + -1'P_await_13_5 + P_done_5_3 = 0
invariant :x_0 + x_1 + x_2 + x_3 + x_4 + x_5 = 1
invariant :P_wait_0_1 + -1'P_await_13_0 + P_done_0_1 = 0
invariant :P_start_1_2 + P_setx_3_2 + P_setbi_5_2 + P_ify0_4_2 + P_sety_9_2 + P_ifxi_10_2 + P_setbi_11_2 + P_fordo_12_2 + P_await_13_2 + P_ifyi_15_2 + P_awaity_2 + P_CS_21_2 + P_setbi_24_2 = 1
invariant :P_wait_2_5 + -1'P_await_13_2 + P_done_2_5 = 0
invariant :P_wait_3_0 + P_done_3_0 = 0
invariant :P_start_1_3 + P_setx_3_3 + P_setbi_5_3 + P_ify0_4_3 + P_sety_9_3 + P_ifxi_10_3 + P_setbi_11_3 + P_fordo_12_3 + P_await_13_3 + P_ifyi_15_3 + P_awaity_3 + P_CS_21_3 + P_setbi_24_3 = 1
invariant :P_b_2_false + P_b_2_true = 1
invariant :P_wait_0_0 + P_done_0_0 = 0
invariant :P_b_5_false + P_b_5_true = 1
invariant :P_wait_1_2 + -1'P_await_13_1 + P_done_1_2 = 0
invariant :P_wait_1_1 + -1'P_await_13_1 + P_done_1_1 = 0
invariant :P_start_1_0 + P_setx_3_0 + P_setbi_5_0 + P_ify0_4_0 + P_sety_9_0 + P_ifxi_10_0 + P_setbi_11_0 + P_fordo_12_0 + P_await_13_0 + P_ifyi_15_0 + P_awaity_0 + P_CS_21_0 + P_setbi_24_0 = 0
invariant :P_wait_0_3 + -1'P_await_13_0 + P_done_0_3 = 0
invariant :P_wait_4_4 + -1'P_await_13_4 + P_done_4_4 = 0
invariant :P_wait_5_4 + -1'P_await_13_5 + P_done_5_4 = 0
invariant :P_b_4_false + P_b_4_true = 1
invariant :P_wait_3_1 + -1'P_await_13_3 + P_done_3_1 = 0
invariant :P_wait_2_2 + -1'P_await_13_2 + P_done_2_2 = 0
invariant :P_wait_4_0 + P_done_4_0 = 0
invariant :P_wait_0_4 + -1'P_await_13_0 + P_done_0_4 = 0
invariant :P_wait_5_2 + -1'P_await_13_5 + P_done_5_2 = 0
invariant :P_wait_2_0 + P_done_2_0 = 0
invariant :P_b_3_false + P_b_3_true = 1
invariant :P_b_0_false + P_b_0_true = 0
invariant :P_wait_0_2 + -1'P_await_13_0 + P_done_0_2 = 0
invariant :P_wait_2_3 + -1'P_await_13_2 + P_done_2_3 = 0
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 246
// Phase 1: matrix 246 rows 174 cols
invariant :P_start_1_1 + P_setx_3_1 + P_setbi_5_1 + P_ify0_4_1 + P_sety_9_1 + P_ifxi_10_1 + P_setbi_11_1 + P_fordo_12_1 + P_await_13_1 + P_ifyi_15_1 + P_awaity_1 + P_CS_21_1 + P_setbi_24_1 = 1
invariant :P_wait_1_5 + -1'P_await_13_1 + P_done_1_5 = 0
invariant :P_wait_1_0 + P_done_1_0 = 0
invariant :P_wait_1_3 + -1'P_await_13_1 + P_done_1_3 = 0
invariant :P_wait_2_1 + -1'P_await_13_2 + P_done_2_1 = 0
invariant :P_wait_5_5 + -1'P_await_13_5 + P_done_5_5 = 0
invariant :P_wait_3_5 + -1'P_await_13_3 + P_done_3_5 = 0
invariant :P_wait_0_5 + -1'P_await_13_0 + P_done_0_5 = 0
invariant :P_wait_4_1 + -1'P_await_13_4 + P_done_4_1 = 0
invariant :P_wait_5_1 + -1'P_await_13_5 + P_done_5_1 = 0
invariant :P_wait_1_4 + -1'P_await_13_1 + P_done_1_4 = 0
invariant :y_0 + y_1 + y_2 + y_3 + y_4 + y_5 = 1
invariant :P_b_1_false + P_b_1_true = 1
invariant :P_wait_2_4 + -1'P_await_13_2 + P_done_2_4 = 0
invariant :P_wait_3_2 + -1'P_await_13_3 + P_done_3_2 = 0
invariant :P_wait_4_2 + -1'P_await_13_4 + P_done_4_2 = 0
invariant :P_wait_4_5 + -1'P_await_13_4 + P_done_4_5 = 0
invariant :P_start_1_5 + P_setx_3_5 + P_setbi_5_5 + P_ify0_4_5 + P_sety_9_5 + P_ifxi_10_5 + P_setbi_11_5 + P_fordo_12_5 + P_await_13_5 + P_ifyi_15_5 + P_awaity_5 + P_CS_21_5 + P_setbi_24_5 = 1
invariant :P_wait_5_0 + P_done_5_0 = 0
invariant :P_wait_3_4 + -1'P_await_13_3 + P_done_3_4 = 0
invariant :P_start_1_4 + P_setx_3_4 + P_setbi_5_4 + P_ify0_4_4 + P_sety_9_4 + P_ifxi_10_4 + P_setbi_11_4 + P_fordo_12_4 + P_await_13_4 + P_ifyi_15_4 + P_awaity_4 + P_CS_21_4 + P_setbi_24_4 = 1
invariant :P_wait_4_3 + -1'P_await_13_4 + P_done_4_3 = 0
invariant :P_wait_3_3 + -1'P_await_13_3 + P_done_3_3 = 0
invariant :P_wait_5_3 + -1'P_await_13_5 + P_done_5_3 = 0
invariant :x_0 + x_1 + x_2 + x_3 + x_4 + x_5 = 1
invariant :P_wait_0_1 + -1'P_await_13_0 + P_done_0_1 = 0
invariant :P_start_1_2 + P_setx_3_2 + P_setbi_5_2 + P_ify0_4_2 + P_sety_9_2 + P_ifxi_10_2 + P_setbi_11_2 + P_fordo_12_2 + P_await_13_2 + P_ifyi_15_2 + P_awaity_2 + P_CS_21_2 + P_setbi_24_2 = 1
invariant :P_wait_2_5 + -1'P_await_13_2 + P_done_2_5 = 0
invariant :P_wait_3_0 + P_done_3_0 = 0
invariant :P_start_1_3 + P_setx_3_3 + P_setbi_5_3 + P_ify0_4_3 + P_sety_9_3 + P_ifxi_10_3 + P_setbi_11_3 + P_fordo_12_3 + P_await_13_3 + P_ifyi_15_3 + P_awaity_3 + P_CS_21_3 + P_setbi_24_3 = 1
invariant :P_b_2_false + P_b_2_true = 1
invariant :P_wait_0_0 + P_done_0_0 = 0
invariant :P_b_5_false + P_b_5_true = 1
invariant :P_wait_1_2 + -1'P_await_13_1 + P_done_1_2 = 0
invariant :P_wait_1_1 + -1'P_await_13_1 + P_done_1_1 = 0
invariant :P_start_1_0 + P_setx_3_0 + P_setbi_5_0 + P_ify0_4_0 + P_sety_9_0 + P_ifxi_10_0 + P_setbi_11_0 + P_fordo_12_0 + P_await_13_0 + P_ifyi_15_0 + P_awaity_0 + P_CS_21_0 + P_setbi_24_0 = 0
invariant :P_wait_0_3 + -1'P_await_13_0 + P_done_0_3 = 0
invariant :P_wait_4_4 + -1'P_await_13_4 + P_done_4_4 = 0
invariant :P_wait_5_4 + -1'P_await_13_5 + P_done_5_4 = 0
invariant :P_b_4_false + P_b_4_true = 1
invariant :P_wait_3_1 + -1'P_await_13_3 + P_done_3_1 = 0
invariant :P_wait_2_2 + -1'P_await_13_2 + P_done_2_2 = 0
invariant :P_wait_4_0 + P_done_4_0 = 0
invariant :P_wait_0_4 + -1'P_await_13_0 + P_done_0_4 = 0
invariant :P_wait_5_2 + -1'P_await_13_5 + P_done_5_2 = 0
invariant :P_wait_2_0 + P_done_2_0 = 0
invariant :P_b_3_false + P_b_3_true = 1
invariant :P_b_0_false + P_b_0_true = 0
invariant :P_wait_0_2 + -1'P_await_13_0 + P_done_0_2 = 0
invariant :P_wait_2_3 + -1'P_await_13_2 + P_done_2_3 = 0
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-02 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-09 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-11 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-12 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-13 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-14 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-15 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx\_PT\_5\_flat\_flat,5.30682e+08,34.1472,636668,2,90039,5,1.48601e+06,6,0,993,2.14125e+06,0
Total reachable state count : 530682432

Verifying 15 reachability properties.
Invariant property LamportFastMutEx-PT-5-ReachabilityCardinality-00 does not hold.
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-00,160,34.3609,636948,2,951,6,1.48601e+06,7,0,1157,2.14125e+06,0
Reachability property LamportFastMutEx-PT-5-ReachabilityCardinality-02 does not hold.
No reachable states exhibit your property : LamportFastMutEx-PT-5-ReachabilityCardinality-02

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-02,0,34.499,637012,1,0,6,1.48601e+06,8,0,1304,2.14125e+06,0
Invariant property LamportFastMutEx-PT-5-ReachabilityCardinality-03 does not hold.
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-03 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-03,1,34.5032,637012,2,175,7,1.48601e+06,9,0,1343,2.14125e+06,0
Reachability property LamportFastMutEx-PT-5-ReachabilityCardinality-04 is true.
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-04 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-04,99479,35.193,637012,2,18571,8,1.48601e+06,10,0,3580,2.14125e+06,0
Reachability property LamportFastMutEx-PT-5-ReachabilityCardinality-05 is true.
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-05 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-05,1,35.2021,637032,2,175,9,1.48601e+06,11,0,3628,2.14125e+06,0
Reachability property LamportFastMutEx-PT-5-ReachabilityCardinality-06 is true.
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-06 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-06,1,35.2072,637032,2,175,10,1.48601e+06,12,0,3640,2.14125e+06,0
Reachability property LamportFastMutEx-PT-5-ReachabilityCardinality-07 is true.
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-07 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-07,1,35.2085,637032,2,175,11,1.48601e+06,13,0,3649,2.14125e+06,0
Reachability property LamportFastMutEx-PT-5-ReachabilityCardinality-08 is true.
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-08 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-08,16,35.21,637032,2,187,12,1.48601e+06,14,0,3652,2.14125e+06,0
Reachability property LamportFastMutEx-PT-5-ReachabilityCardinality-09 does not hold.
No reachable states exhibit your property : LamportFastMutEx-PT-5-ReachabilityCardinality-09

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-09,0,35.303,637032,1,0,12,1.48601e+06,15,0,3658,2.14125e+06,0
Invariant property LamportFastMutEx-PT-5-ReachabilityCardinality-10 does not hold.
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-10 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-10,250780,35.3117,637032,2,3821,13,1.48601e+06,16,0,3664,2.14125e+06,0
Invariant property LamportFastMutEx-PT-5-ReachabilityCardinality-11 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-11,0,35.3253,637032,1,0,13,1.48601e+06,17,0,3665,2.14125e+06,0
Invariant property LamportFastMutEx-PT-5-ReachabilityCardinality-12 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-12,0,35.4425,637032,1,0,13,1.48601e+06,18,0,3674,2.14125e+06,0
Reachability property LamportFastMutEx-PT-5-ReachabilityCardinality-13 does not hold.
No reachable states exhibit your property : LamportFastMutEx-PT-5-ReachabilityCardinality-13

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-13,0,35.5313,637032,1,0,13,1.48601e+06,19,0,3675,2.14125e+06,0
Reachability property LamportFastMutEx-PT-5-ReachabilityCardinality-14 does not hold.
No reachable states exhibit your property : LamportFastMutEx-PT-5-ReachabilityCardinality-14

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-14,0,35.6005,637032,1,0,13,1.48601e+06,20,0,3684,2.14125e+06,0
Invariant property LamportFastMutEx-PT-5-ReachabilityCardinality-15 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-15,0,35.7373,637032,1,0,13,1.48601e+06,21,0,3690,2.14125e+06,0
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O2, model.c], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1552787161063

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ ReachabilityCardinality = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Mar 17, 2019 1:45:22 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Mar 17, 2019 1:45:22 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Mar 17, 2019 1:45:22 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 141 ms
Mar 17, 2019 1:45:22 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 174 places.
Mar 17, 2019 1:45:22 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 318 transitions.
Mar 17, 2019 1:45:22 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 37 ms
Mar 17, 2019 1:45:23 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 198 ms
Mar 17, 2019 1:45:23 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 81 ms
Mar 17, 2019 1:45:23 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 172 ms
Mar 17, 2019 1:45:23 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 11 ms
Mar 17, 2019 1:45:23 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 2 ms
Mar 17, 2019 1:45:23 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 318 transitions.
Mar 17, 2019 1:45:23 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 318 transitions.
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 50 place invariants in 128 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 15 in 881 ms.
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-00(UNSAT) depth K=0 took 12 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-02(UNSAT) depth K=0 took 16 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-03(UNSAT) depth K=0 took 11 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-04(UNSAT) depth K=0 took 3 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-05(UNSAT) depth K=0 took 7 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-06(UNSAT) depth K=0 took 9 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-07(UNSAT) depth K=0 took 6 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-08(UNSAT) depth K=0 took 3 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-09(UNSAT) depth K=0 took 2 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-10(UNSAT) depth K=0 took 7 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-11(UNSAT) depth K=0 took 2 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-12(UNSAT) depth K=0 took 2 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-13(UNSAT) depth K=0 took 1 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-14(UNSAT) depth K=0 took 2 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-15(UNSAT) depth K=0 took 2 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 318 transitions.
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-00(UNSAT) depth K=1 took 28 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-02(UNSAT) depth K=1 took 6 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-03(UNSAT) depth K=1 took 5 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-04(UNSAT) depth K=1 took 22 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-05(UNSAT) depth K=1 took 22 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-06(UNSAT) depth K=1 took 16 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-07(UNSAT) depth K=1 took 15 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-08(UNSAT) depth K=1 took 15 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-09(UNSAT) depth K=1 took 17 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-10(UNSAT) depth K=1 took 6 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-11(UNSAT) depth K=1 took 16 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-12(UNSAT) depth K=1 took 9 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-13(UNSAT) depth K=1 took 10 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-14(UNSAT) depth K=1 took 10 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-15(UNSAT) depth K=1 took 10 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 50 place invariants in 65 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-00(UNSAT) depth K=2 took 155 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-02(UNSAT) depth K=2 took 148 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-03(UNSAT) depth K=2 took 133 ms
Mar 17, 2019 1:45:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-04(UNSAT) depth K=2 took 70 ms
Mar 17, 2019 1:45:25 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-05(UNSAT) depth K=2 took 240 ms
Mar 17, 2019 1:45:25 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-06(UNSAT) depth K=2 took 62 ms
Mar 17, 2019 1:45:25 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-07(UNSAT) depth K=2 took 50 ms
Mar 17, 2019 1:45:25 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-08(UNSAT) depth K=2 took 57 ms
Mar 17, 2019 1:45:25 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-09(UNSAT) depth K=2 took 83 ms
Mar 17, 2019 1:45:25 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-10(UNSAT) depth K=2 took 61 ms
Mar 17, 2019 1:45:25 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-11(UNSAT) depth K=2 took 122 ms
Mar 17, 2019 1:45:25 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-12(UNSAT) depth K=2 took 54 ms
Mar 17, 2019 1:45:25 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-13(UNSAT) depth K=2 took 65 ms
Mar 17, 2019 1:45:25 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-14(UNSAT) depth K=2 took 206 ms
Mar 17, 2019 1:45:26 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-15(UNSAT) depth K=2 took 44 ms
Mar 17, 2019 1:45:26 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 174 variables to be positive in 2096 ms
Mar 17, 2019 1:45:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 318 transitions.
Mar 17, 2019 1:45:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/318 took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 17, 2019 1:45:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 90 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 17, 2019 1:45:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 318 transitions.
Mar 17, 2019 1:45:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 33 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 17, 2019 1:45:26 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 174 variables to be positive in 1776 ms
Mar 17, 2019 1:45:27 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-00(UNSAT) depth K=3 took 1270 ms
Mar 17, 2019 1:45:27 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-00
Mar 17, 2019 1:45:27 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-00(SAT) depth K=0 took 1105 ms
Mar 17, 2019 1:45:27 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate LamportFastMutEx-PT-5-ReachabilityCardinality-02
Mar 17, 2019 1:45:27 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-PT-5-ReachabilityCardinality-02
Mar 17, 2019 1:45:27 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-02(FALSE) depth K=0 took 293 ms
Mar 17, 2019 1:45:27 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-03
Mar 17, 2019 1:45:27 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-03(SAT) depth K=0 took 235 ms
Mar 17, 2019 1:45:28 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-04
Mar 17, 2019 1:45:28 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-04(SAT) depth K=0 took 526 ms
Mar 17, 2019 1:45:29 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-02(UNSAT) depth K=3 took 1737 ms
Mar 17, 2019 1:45:29 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-05
Mar 17, 2019 1:45:29 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-05(SAT) depth K=0 took 1134 ms
Mar 17, 2019 1:45:29 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-06
Mar 17, 2019 1:45:29 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-06(SAT) depth K=0 took 296 ms
Mar 17, 2019 1:45:30 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-07
Mar 17, 2019 1:45:30 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-07(SAT) depth K=0 took 252 ms
Mar 17, 2019 1:45:30 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-08
Mar 17, 2019 1:45:30 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-08(SAT) depth K=0 took 314 ms
Mar 17, 2019 1:45:30 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate LamportFastMutEx-PT-5-ReachabilityCardinality-09
Mar 17, 2019 1:45:30 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-PT-5-ReachabilityCardinality-09
Mar 17, 2019 1:45:30 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-09(FALSE) depth K=0 took 139 ms
Mar 17, 2019 1:45:30 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-10
Mar 17, 2019 1:45:30 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-10(SAT) depth K=0 took 312 ms
Mar 17, 2019 1:45:31 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant LamportFastMutEx-PT-5-ReachabilityCardinality-11
Mar 17, 2019 1:45:31 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-PT-5-ReachabilityCardinality-11
Mar 17, 2019 1:45:31 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-11(TRUE) depth K=0 took 143 ms
Mar 17, 2019 1:45:31 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant LamportFastMutEx-PT-5-ReachabilityCardinality-12
Mar 17, 2019 1:45:31 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-PT-5-ReachabilityCardinality-12
Mar 17, 2019 1:45:31 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-12(TRUE) depth K=0 took 139 ms
Mar 17, 2019 1:45:31 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate LamportFastMutEx-PT-5-ReachabilityCardinality-13
Mar 17, 2019 1:45:31 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-PT-5-ReachabilityCardinality-13
Mar 17, 2019 1:45:31 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-13(FALSE) depth K=0 took 128 ms
Mar 17, 2019 1:45:31 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate LamportFastMutEx-PT-5-ReachabilityCardinality-14
Mar 17, 2019 1:45:31 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-PT-5-ReachabilityCardinality-14
Mar 17, 2019 1:45:31 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-14(FALSE) depth K=0 took 252 ms
Mar 17, 2019 1:45:31 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant LamportFastMutEx-PT-5-ReachabilityCardinality-15
Mar 17, 2019 1:45:31 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-PT-5-ReachabilityCardinality-15
Mar 17, 2019 1:45:31 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-15(TRUE) depth K=0 took 141 ms
Mar 17, 2019 1:45:32 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-03(UNSAT) depth K=3 took 3021 ms
Mar 17, 2019 1:45:34 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-04(UNSAT) depth K=3 took 2374 ms
Mar 17, 2019 1:45:35 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-00
Mar 17, 2019 1:45:35 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-00(SAT) depth K=1 took 3935 ms
Mar 17, 2019 1:45:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-03
Mar 17, 2019 1:45:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-03(SAT) depth K=1 took 770 ms
Mar 17, 2019 1:45:40 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-05(UNSAT) depth K=3 took 6002 ms
Mar 17, 2019 1:45:41 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-06(UNSAT) depth K=3 took 1074 ms
Mar 17, 2019 1:45:42 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-07(UNSAT) depth K=3 took 539 ms
Mar 17, 2019 1:45:42 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-04
Mar 17, 2019 1:45:42 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-04(SAT) depth K=1 took 5692 ms
Mar 17, 2019 1:45:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 318 transitions.
Mar 17, 2019 1:45:43 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/318) took 569 ms. Total solver calls (SAT/UNSAT): 57(0/57)
Mar 17, 2019 1:45:45 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-08(UNSAT) depth K=3 took 3378 ms
Mar 17, 2019 1:45:46 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(6/318) took 3820 ms. Total solver calls (SAT/UNSAT): 396(15/381)
Mar 17, 2019 1:45:47 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-09(UNSAT) depth K=3 took 2273 ms
Mar 17, 2019 1:45:49 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-10(UNSAT) depth K=3 took 2119 ms
Mar 17, 2019 1:45:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(12/318) took 7487 ms. Total solver calls (SAT/UNSAT): 788(25/763)
Mar 17, 2019 1:45:51 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-11(UNSAT) depth K=3 took 1326 ms
Mar 17, 2019 1:45:53 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-12(UNSAT) depth K=3 took 2105 ms
Mar 17, 2019 1:45:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(15/318) took 10492 ms. Total solver calls (SAT/UNSAT): 1112(25/1087)
Mar 17, 2019 1:45:54 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-13(UNSAT) depth K=3 took 1180 ms
Mar 17, 2019 1:45:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-14(UNSAT) depth K=3 took 751 ms
Mar 17, 2019 1:45:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-05
Mar 17, 2019 1:45:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-05(SAT) depth K=1 took 13386 ms
Mar 17, 2019 1:45:57 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(19/318) took 14420 ms. Total solver calls (SAT/UNSAT): 1530(43/1487)
Mar 17, 2019 1:45:58 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-06
Mar 17, 2019 1:45:58 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-06(SAT) depth K=1 took 3195 ms
Mar 17, 2019 1:45:58 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-15(UNSAT) depth K=3 took 3470 ms
Mar 17, 2019 1:45:59 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-07
Mar 17, 2019 1:45:59 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-07(SAT) depth K=1 took 684 ms
Mar 17, 2019 1:45:59 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
Mar 17, 2019 1:45:59 AM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Mar 17, 2019 1:45:59 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
WARNING: Unexpected error occurred while running SMT. Was verifying LamportFastMutEx-PT-5-ReachabilityCardinality-04 SMT depth 4
java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:404)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
... 3 more
Mar 17, 2019 1:45:59 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: During BMC, SMT solver timed out at depth 4
Mar 17, 2019 1:45:59 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solving timed out (3600000 secs) at depth 4
Mar 17, 2019 1:45:59 AM org.smtlib.impl.Script execute
WARNING: Script execution failed on command (assert (and (>= (select s0 10) 1) (>= (select s0 35) 1))) with error (error "Failed to assert expression: java.io.IOException: Stream closed (and (>= (select s0 10) 1) (>= (select s0 35) 1))")
[(assert (and (>= (select s0 10) 1) (>= (select s0 35) 1)))]
Skipping mayMatrices nes/nds SMT solver raised an exception.
java.lang.RuntimeException: SMT solver raised an exception.
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.computeCoEnablingMatrix(NecessaryEnablingsolver.java:475)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:530)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
Mar 17, 2019 1:45:59 AM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 7/ 15 properties. Interrupting other analysis methods.
Mar 17, 2019 1:45:59 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 36474ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-PT-5"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3957"
echo " Executing tool itstools"
echo " Input is LamportFastMutEx-PT-5, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r096-smll-155246587300215"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-PT-5.tgz
mv LamportFastMutEx-PT-5 execution
cd execution
if [ "ReachabilityCardinality" = "GlobalProperties" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;