fond
Model Checking Contest 2018
8th edition, Bratislava, Slovakia, June 26, 2018
Execution of r281-csrt-152749171100418
Last Updated
June 26, 2018

About the Execution of LTSMin for RERS17pb113-PT-5

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
2477.360 3571885.00 13982542.00 235.70 ???????????????? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.......................................................................................................................................................................................................................................
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 4.3K May 30 21:53 CTLCardinality.txt
-rw-r--r-- 1 mcc users 27K May 30 21:53 CTLCardinality.xml
-rw-r--r-- 1 mcc users 3.7K May 29 15:56 CTLFireability.txt
-rw-r--r-- 1 mcc users 20K May 29 15:56 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.4K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.2K May 28 09:59 LTLCardinality.txt
-rw-r--r-- 1 mcc users 9.1K May 28 09:59 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K May 28 08:14 LTLFireability.txt
-rw-r--r-- 1 mcc users 11K May 28 08:14 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.0K May 28 06:44 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 15K May 28 06:44 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 107 May 26 06:30 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 345 May 26 06:30 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 4.0K May 27 04:14 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 19K May 27 04:14 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 28 07:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 28 07:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 2 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 15M May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool ltsmin
Input is RERS17pb113-PT-5, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r281-csrt-152749171100418

=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-00
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-01
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-02
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-03
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-04
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-05
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-06
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-07
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-08
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-09
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-10
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-11
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-12
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-13
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-14
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1527863187788

FORMULA RERS17pb113-PT-1-CTLFireability-00 CANNOT_COMPUTE
FORMULA RERS17pb113-PT-1-CTLFireability-01 CANNOT_COMPUTE
FORMULA RERS17pb113-PT-1-CTLFireability-02 CANNOT_COMPUTE
FORMULA RERS17pb113-PT-1-CTLFireability-03 CANNOT_COMPUTE
FORMULA RERS17pb113-PT-1-CTLFireability-04 CANNOT_COMPUTE
FORMULA RERS17pb113-PT-1-CTLFireability-05 CANNOT_COMPUTE
FORMULA RERS17pb113-PT-1-CTLFireability-06 CANNOT_COMPUTE
FORMULA RERS17pb113-PT-1-CTLFireability-07 CANNOT_COMPUTE
FORMULA RERS17pb113-PT-1-CTLFireability-08 CANNOT_COMPUTE
FORMULA RERS17pb113-PT-1-CTLFireability-09 CANNOT_COMPUTE
FORMULA RERS17pb113-PT-1-CTLFireability-10 CANNOT_COMPUTE
FORMULA RERS17pb113-PT-1-CTLFireability-11 CANNOT_COMPUTE
FORMULA RERS17pb113-PT-1-CTLFireability-12 CANNOT_COMPUTE
FORMULA RERS17pb113-PT-1-CTLFireability-13 CANNOT_COMPUTE
FORMULA RERS17pb113-PT-1-CTLFireability-14 CANNOT_COMPUTE
FORMULA RERS17pb113-PT-1-CTLFireability-15 CANNOT_COMPUTE

BK_STOP 1527866759673

--------------------
content from stderr:

mcc2018
ctl formula name RERS17pb113-PT-1-CTLFireability-00
ctl formula formula --ctl=/tmp/ctl_0_
ctl formula name RERS17pb113-PT-1-CTLFireability-01
ctl formula formula --ctl=/tmp/ctl_1_
ctl formula name RERS17pb113-PT-1-CTLFireability-02
ctl formula formula --ctl=/tmp/ctl_2_
ctl formula name RERS17pb113-PT-1-CTLFireability-03
ctl formula formula --ctl=/tmp/ctl_3_
ctl formula name RERS17pb113-PT-1-CTLFireability-04
ctl formula formula --ctl=/tmp/ctl_4_
ctl formula name RERS17pb113-PT-1-CTLFireability-05
ctl formula formula --ctl=/tmp/ctl_5_
ctl formula name RERS17pb113-PT-1-CTLFireability-06
ctl formula formula --ctl=/tmp/ctl_6_
ctl formula name RERS17pb113-PT-1-CTLFireability-07
ctl formula formula --ctl=/tmp/ctl_7_
ctl formula name RERS17pb113-PT-1-CTLFireability-08
ctl formula formula --ctl=/tmp/ctl_8_
ctl formula name RERS17pb113-PT-1-CTLFireability-09
ctl formula formula --ctl=/tmp/ctl_9_
ctl formula name RERS17pb113-PT-1-CTLFireability-10
ctl formula formula --ctl=/tmp/ctl_10_
ctl formula name RERS17pb113-PT-1-CTLFireability-11
ctl formula formula --ctl=/tmp/ctl_11_
ctl formula name RERS17pb113-PT-1-CTLFireability-12
ctl formula formula --ctl=/tmp/ctl_12_
ctl formula name RERS17pb113-PT-1-CTLFireability-13
ctl formula formula --ctl=/tmp/ctl_13_
ctl formula name RERS17pb113-PT-1-CTLFireability-14
ctl formula formula --ctl=/tmp/ctl_14_
ctl formula name RERS17pb113-PT-1-CTLFireability-15
ctl formula formula --ctl=/tmp/ctl_15_
pnml2lts-sym: Exploration order is chain-prev
pnml2lts-sym: Saturation strategy is sat-like
pnml2lts-sym: Guided search strategy is unguided
pnml2lts-sym: Attractor strategy is default
pnml2lts-sym: opening model.pnml
pnml2lts-sym: Edge label is id
pnml2lts-sym: Petri net has 639 places, 31353 transitions and 125418 arcs
pnml2lts-sym: Petri net RERS17pb113-PT-1 analyzed
pnml2lts-sym: There are safe places
pnml2lts-sym: Loading Petri net took 0.340 real 0.340 user 0.000 sys
pnml2lts-sym: Initializing regrouping layer
pnml2lts-sym: Regroup specification: bs,w2W,ru,hf
pnml2lts-sym: Regroup Boost's Sloan
pnml2lts-sym: Regroup over-approximate must-write to may-write
pnml2lts-sym: Regroup Row sUbsume
pnml2lts-sym: Reqroup Horizontal Flip
pnml2lts-sym: Regrouping: 31353->31353 groups
pnml2lts-sym: Regrouping took 52.200 real 51.620 user 0.000 sys
pnml2lts-sym: state vector length is 639; there are 31353 groups
pnml2lts-sym: Creating a multi-core ListDD domain.
pnml2lts-sym: Sylvan allocates 15.000 GB virtual memory for nodes table and operation cache.
pnml2lts-sym: Initial nodes table and operation cache requires 15.000 GB.
pnml2lts-sym: Using GBgetTransitionsShortR2W as next-state function

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb113-PT-5"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="ltsmin"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb113-PT-5.tgz
mv RERS17pb113-PT-5 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool ltsmin"
echo " Input is RERS17pb113-PT-5, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r281-csrt-152749171100418"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;