Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
..................
/home/mcc/execution
total 1.1M
-rw-r--r-- 1 mcc users 4.2K May 29 16:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 25K May 29 16:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K May 28 11:15 CTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 28 11:15 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.6K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.4K May 28 09:25 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 28 09:25 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9K May 28 07:39 LTLFireability.txt
-rw-r--r-- 1 mcc users 10K May 28 07:39 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.6K May 27 05:09 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 19K May 27 05:09 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 104 May 26 06:29 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 342 May 26 06:29 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.4K May 26 06:35 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 14K May 26 06:35 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 28 07:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 28 07:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 4 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 920K May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is ASLink-PT-10a, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r273-smll-152749149600170
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ASLink-PT-10a-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1527892371690

Flatten gal took : 724 ms
Constant places removed 41 places and 1 transitions.
Reduce isomorphic transitions removed 34 transitions.
Implicit places reduction removed 20 places :[p2043, p1976, p1781, p1769, p1586, p1574, p1391, p1379, p1196, p1184, p1001, p989, p806, p794, p611, p599, p416, p404, p221, p209]
Performed 421 Post agglomeration using F-continuation condition.
Iterating post reduction 0 with 516 rules applied. Total rules applied 516 place count 2125 transition count 2736
Constant places removed 524 places and 0 transitions.
Performed 32 Post agglomeration using F-continuation condition.
Iterating post reduction 1 with 556 rules applied. Total rules applied 1072 place count 1601 transition count 2704
Constant places removed 33 places and 0 transitions.
Implicit places reduction removed 11 places :[p1953, p1758, p1563, p1368, p1173, p978, p783, p588, p393, p206, p199]
Performed 11 Post agglomeration using F-continuation condition.
Iterating post reduction 2 with 55 rules applied. Total rules applied 1127 place count 1557 transition count 2693
Constant places removed 11 places and 0 transitions.
Iterating post reduction 3 with 11 rules applied. Total rules applied 1138 place count 1546 transition count 2693
Performed 40 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 4 with 40 Pre rules applied. Total rules applied 1138 place count 1546 transition count 2653
Constant places removed 40 places and 0 transitions.
Iterating post reduction 4 with 40 rules applied. Total rules applied 1178 place count 1506 transition count 2653
Symmetric choice reduction at 5 with 23 rule applications. Total rules 1201 place count 1506 transition count 2653
Constant places removed 23 places and 81 transitions.
Reduce isomorphic transitions removed 2 transitions.
Implicit places reduction removed 13 places :[p2185, p2046, p1944, p1749, p1554, p1359, p1164, p969, p774, p579, p384, p190, p23]
Performed 14 Post agglomeration using F-continuation condition.
Iterating post reduction 5 with 52 rules applied. Total rules applied 1253 place count 1470 transition count 2556
Constant places removed 14 places and 0 transitions.
Iterating post reduction 6 with 14 rules applied. Total rules applied 1267 place count 1456 transition count 2556
Symmetric choice reduction at 7 with 11 rule applications. Total rules 1278 place count 1456 transition count 2556
Constant places removed 11 places and 18 transitions.
Iterating post reduction 7 with 11 rules applied. Total rules applied 1289 place count 1445 transition count 2538
Symmetric choice reduction at 8 with 1 rule applications. Total rules 1290 place count 1445 transition count 2538
Constant places removed 1 places and 8 transitions.
Iterating post reduction 8 with 1 rules applied. Total rules applied 1291 place count 1444 transition count 2530
Symmetric choice reduction at 9 with 1 rule applications. Total rules 1292 place count 1444 transition count 2530
Constant places removed 1 places and 8 transitions.
Iterating post reduction 9 with 1 rules applied. Total rules applied 1293 place count 1443 transition count 2522
Symmetric choice reduction at 10 with 1 rule applications. Total rules 1294 place count 1443 transition count 2522
Constant places removed 1 places and 8 transitions.
Iterating post reduction 10 with 1 rules applied. Total rules applied 1295 place count 1442 transition count 2514
Symmetric choice reduction at 11 with 1 rule applications. Total rules 1296 place count 1442 transition count 2514
Constant places removed 1 places and 8 transitions.
Iterating post reduction 11 with 1 rules applied. Total rules applied 1297 place count 1441 transition count 2506
Symmetric choice reduction at 12 with 1 rule applications. Total rules 1298 place count 1441 transition count 2506
Constant places removed 1 places and 8 transitions.
Iterating post reduction 12 with 1 rules applied. Total rules applied 1299 place count 1440 transition count 2498
Symmetric choice reduction at 13 with 1 rule applications. Total rules 1300 place count 1440 transition count 2498
Constant places removed 1 places and 8 transitions.
Iterating post reduction 13 with 1 rules applied. Total rules applied 1301 place count 1439 transition count 2490
Symmetric choice reduction at 14 with 1 rule applications. Total rules 1302 place count 1439 transition count 2490
Constant places removed 1 places and 8 transitions.
Iterating post reduction 14 with 1 rules applied. Total rules applied 1303 place count 1438 transition count 2482
Symmetric choice reduction at 15 with 1 rule applications. Total rules 1304 place count 1438 transition count 2482
Constant places removed 1 places and 8 transitions.
Iterating post reduction 15 with 1 rules applied. Total rules applied 1305 place count 1437 transition count 2474
Symmetric choice reduction at 16 with 1 rule applications. Total rules 1306 place count 1437 transition count 2474
Constant places removed 1 places and 8 transitions.
Iterating post reduction 16 with 1 rules applied. Total rules applied 1307 place count 1436 transition count 2466
Symmetric choice reduction at 17 with 1 rule applications. Total rules 1308 place count 1436 transition count 2466
Constant places removed 1 places and 8 transitions.
Iterating post reduction 17 with 1 rules applied. Total rules applied 1309 place count 1435 transition count 2458
Symmetric choice reduction at 18 with 1 rule applications. Total rules 1310 place count 1435 transition count 2458
Constant places removed 1 places and 8 transitions.
Iterating post reduction 18 with 1 rules applied. Total rules applied 1311 place count 1434 transition count 2450
Symmetric choice reduction at 19 with 1 rule applications. Total rules 1312 place count 1434 transition count 2450
Constant places removed 1 places and 8 transitions.
Iterating post reduction 19 with 1 rules applied. Total rules applied 1313 place count 1433 transition count 2442
Symmetric choice reduction at 20 with 1 rule applications. Total rules 1314 place count 1433 transition count 2442
Constant places removed 1 places and 8 transitions.
Iterating post reduction 20 with 1 rules applied. Total rules applied 1315 place count 1432 transition count 2434
Symmetric choice reduction at 21 with 1 rule applications. Total rules 1316 place count 1432 transition count 2434
Constant places removed 1 places and 8 transitions.
Iterating post reduction 21 with 1 rules applied. Total rules applied 1317 place count 1431 transition count 2426
Symmetric choice reduction at 22 with 1 rule applications. Total rules 1318 place count 1431 transition count 2426
Constant places removed 1 places and 8 transitions.
Iterating post reduction 22 with 1 rules applied. Total rules applied 1319 place count 1430 transition count 2418
Performed 31 Post agglomeration using F-continuation condition.
Constant places removed 31 places and 0 transitions.
Iterating post reduction 23 with 31 rules applied. Total rules applied 1350 place count 1399 transition count 2387
Applied a total of 1350 rules in 2835 ms. Remains 1399 /2186 variables (removed 787) and now considering 2387/3192 (removed 805) transitions.
// Phase 1: matrix 2387 rows 1399 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
built 118 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 100 ordering constraints for composite.
Compilation finished in 34898 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 71 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -d], workingDir=/home/mcc/execution]
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,1.47285e+37,156.596,2465820,7849,586,4.43928e+06,1801,3957,6.88957e+06,150,11798,0


Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,4.55935e+25,157.635,2465820,1788,234,4.43928e+06,7290,11753,6.88957e+06,813,20472,355940

System contains 4.55935e+25 deadlocks (shown below if less than --print-limit option) !
FORMULA ASLink-PT-10a-ReachabilityDeadlock-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
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[ u171={[ ]
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} u153={[ ]
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} i1={[ u431={[ p885=1 ]
[ p881=1 ]
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} u178={[ p1008=1 ]
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} u109={[ p637=1 ]
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} i1={[ u406={[ ]
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[ u136={[ ]
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} i5={[ u422={[ ]
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} ]
} u118={[ ]
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} i3={[ u424={[ ]
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} i1={[ u406={[ p690=1 ]
[ p686=1 ]
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} u117={[ ]
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} ]
} u143={[ p813=1 ]
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} u74={[ p442=1 ]
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} i1={[ u444={[ ]
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[ u101={[ ]
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WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527892542110

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 01, 2018 10:32:53 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
Jun 01, 2018 10:32:53 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 01, 2018 10:32:54 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 313 ms
Jun 01, 2018 10:32:54 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 2186 places.
Jun 01, 2018 10:32:54 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 3192 transitions.
Jun 01, 2018 10:32:54 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
Jun 01, 2018 10:32:54 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 93 ms
Jun 01, 2018 10:32:55 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 717 ms
Jun 01, 2018 10:32:55 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 26 ms
Jun 01, 2018 10:32:55 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 3192 transitions.
Jun 01, 2018 10:33:01 PM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Jun 01, 2018 10:33:01 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 2387 transitions.
Jun 01, 2018 10:33:01 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Too many transitions (2387) to apply POR reductions. Disabling POR matrices.
Jun 01, 2018 10:33:01 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 334 ms
Jun 01, 2018 10:33:01 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 458ms conformant to PINS in folder :/home/mcc/execution
Jun 01, 2018 10:33:01 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 307 ms
Jun 01, 2018 10:33:02 PM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Jun 01, 2018 10:33:02 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 265 ms
Jun 01, 2018 10:33:02 PM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
Jun 01, 2018 10:33:03 PM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 3328 redundant transitions.
Jun 01, 2018 10:33:03 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 41 ms

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ASLink-PT-10a"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/ASLink-PT-10a.tgz
mv ASLink-PT-10a execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is ASLink-PT-10a, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r273-smll-152749149600170"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;