fond
Model Checking Contest 2018
8th edition, Bratislava, Slovakia, June 26, 2018
Execution of r273-smll-152749149600134
Last Updated
June 26, 2018

About the Execution of ITS-Tools.L for ASLink-PT-08a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15747.800 91185.00 188280.00 494.10 T normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
...................
/home/mcc/execution
total 932K
-rw-r--r-- 1 mcc users 3.1K May 29 16:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 17K May 29 16:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K May 28 11:15 CTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 28 11:15 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.6K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.5K May 28 09:24 LTLCardinality.txt
-rw-r--r-- 1 mcc users 13K May 28 09:24 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.8K May 28 07:38 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.6K May 28 07:38 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.5K May 27 05:08 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K May 27 05:08 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 104 May 26 06:29 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 342 May 26 06:29 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.6K May 26 06:35 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 16K May 26 06:35 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 28 07:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 28 07:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 4 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 757K May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is ASLink-PT-08a, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r273-smll-152749149600134

=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ASLink-PT-08a-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1527845385546

Flatten gal took : 668 ms
Constant places removed 33 places and 1 transitions.
Reduce isomorphic transitions removed 28 transitions.
Implicit places reduction removed 16 places :[p1653, p1586, p1391, p1379, p1196, p1184, p1001, p989, p806, p794, p611, p599, p416, p404, p221, p209]
Performed 341 Post agglomeration using F-continuation condition.
Iterating post reduction 0 with 418 rules applied. Total rules applied 418 place count 1747 transition count 2276
Constant places removed 424 places and 0 transitions.
Performed 26 Post agglomeration using F-continuation condition.
Iterating post reduction 1 with 450 rules applied. Total rules applied 868 place count 1323 transition count 2250
Constant places removed 27 places and 0 transitions.
Implicit places reduction removed 9 places :[p1563, p1368, p1173, p978, p783, p588, p393, p206, p199]
Performed 9 Post agglomeration using F-continuation condition.
Iterating post reduction 2 with 45 rules applied. Total rules applied 913 place count 1287 transition count 2241
Constant places removed 9 places and 0 transitions.
Iterating post reduction 3 with 9 rules applied. Total rules applied 922 place count 1278 transition count 2241
Performed 32 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 4 with 32 Pre rules applied. Total rules applied 922 place count 1278 transition count 2209
Constant places removed 32 places and 0 transitions.
Iterating post reduction 4 with 32 rules applied. Total rules applied 954 place count 1246 transition count 2209
Symmetric choice reduction at 5 with 19 rule applications. Total rules 973 place count 1246 transition count 2209
Constant places removed 19 places and 67 transitions.
Reduce isomorphic transitions removed 2 transitions.
Implicit places reduction removed 11 places :[p1795, p1656, p1554, p1359, p1164, p969, p774, p579, p384, p190, p23]
Performed 12 Post agglomeration using F-continuation condition.
Iterating post reduction 5 with 44 rules applied. Total rules applied 1017 place count 1216 transition count 2128
Constant places removed 12 places and 0 transitions.
Iterating post reduction 6 with 12 rules applied. Total rules applied 1029 place count 1204 transition count 2128
Symmetric choice reduction at 7 with 9 rule applications. Total rules 1038 place count 1204 transition count 2128
Constant places removed 9 places and 16 transitions.
Iterating post reduction 7 with 9 rules applied. Total rules applied 1047 place count 1195 transition count 2112
Symmetric choice reduction at 8 with 1 rule applications. Total rules 1048 place count 1195 transition count 2112
Constant places removed 1 places and 8 transitions.
Iterating post reduction 8 with 1 rules applied. Total rules applied 1049 place count 1194 transition count 2104
Symmetric choice reduction at 9 with 1 rule applications. Total rules 1050 place count 1194 transition count 2104
Constant places removed 1 places and 8 transitions.
Iterating post reduction 9 with 1 rules applied. Total rules applied 1051 place count 1193 transition count 2096
Symmetric choice reduction at 10 with 1 rule applications. Total rules 1052 place count 1193 transition count 2096
Constant places removed 1 places and 8 transitions.
Iterating post reduction 10 with 1 rules applied. Total rules applied 1053 place count 1192 transition count 2088
Symmetric choice reduction at 11 with 1 rule applications. Total rules 1054 place count 1192 transition count 2088
Constant places removed 1 places and 8 transitions.
Iterating post reduction 11 with 1 rules applied. Total rules applied 1055 place count 1191 transition count 2080
Symmetric choice reduction at 12 with 1 rule applications. Total rules 1056 place count 1191 transition count 2080
Constant places removed 1 places and 8 transitions.
Iterating post reduction 12 with 1 rules applied. Total rules applied 1057 place count 1190 transition count 2072
Symmetric choice reduction at 13 with 1 rule applications. Total rules 1058 place count 1190 transition count 2072
Constant places removed 1 places and 8 transitions.
Iterating post reduction 13 with 1 rules applied. Total rules applied 1059 place count 1189 transition count 2064
Symmetric choice reduction at 14 with 1 rule applications. Total rules 1060 place count 1189 transition count 2064
Constant places removed 1 places and 8 transitions.
Iterating post reduction 14 with 1 rules applied. Total rules applied 1061 place count 1188 transition count 2056
Symmetric choice reduction at 15 with 1 rule applications. Total rules 1062 place count 1188 transition count 2056
Constant places removed 1 places and 8 transitions.
Iterating post reduction 15 with 1 rules applied. Total rules applied 1063 place count 1187 transition count 2048
Symmetric choice reduction at 16 with 1 rule applications. Total rules 1064 place count 1187 transition count 2048
Constant places removed 1 places and 8 transitions.
Iterating post reduction 16 with 1 rules applied. Total rules applied 1065 place count 1186 transition count 2040
Symmetric choice reduction at 17 with 1 rule applications. Total rules 1066 place count 1186 transition count 2040
Constant places removed 1 places and 8 transitions.
Iterating post reduction 17 with 1 rules applied. Total rules applied 1067 place count 1185 transition count 2032
Symmetric choice reduction at 18 with 1 rule applications. Total rules 1068 place count 1185 transition count 2032
Constant places removed 1 places and 8 transitions.
Iterating post reduction 18 with 1 rules applied. Total rules applied 1069 place count 1184 transition count 2024
Symmetric choice reduction at 19 with 1 rule applications. Total rules 1070 place count 1184 transition count 2024
Constant places removed 1 places and 8 transitions.
Iterating post reduction 19 with 1 rules applied. Total rules applied 1071 place count 1183 transition count 2016
Symmetric choice reduction at 20 with 1 rule applications. Total rules 1072 place count 1183 transition count 2016
Constant places removed 1 places and 8 transitions.
Iterating post reduction 20 with 1 rules applied. Total rules applied 1073 place count 1182 transition count 2008
Symmetric choice reduction at 21 with 1 rule applications. Total rules 1074 place count 1182 transition count 2008
Constant places removed 1 places and 8 transitions.
Iterating post reduction 21 with 1 rules applied. Total rules applied 1075 place count 1181 transition count 2000
Symmetric choice reduction at 22 with 1 rule applications. Total rules 1076 place count 1181 transition count 2000
Constant places removed 1 places and 8 transitions.
Iterating post reduction 22 with 1 rules applied. Total rules applied 1077 place count 1180 transition count 1992
Performed 25 Post agglomeration using F-continuation condition.
Constant places removed 25 places and 0 transitions.
Iterating post reduction 23 with 25 rules applied. Total rules applied 1102 place count 1155 transition count 1967
Applied a total of 1102 rules in 2093 ms. Remains 1155 /1796 variables (removed 641) and now considering 1967/2646 (removed 679) transitions.
// Phase 1: matrix 1967 rows 1155 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
built 96 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 100 ordering constraints for composite.
Compilation finished in 28290 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 161 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -d], workingDir=/home/mcc/execution]
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,2.754e+30,78.73,1410684,6059,586,2.66148e+06,1854,3310,3.39786e+06,150,12263,0


Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,7.0963e+20,80.402,1410684,1320,231,2.66148e+06,6833,9892,3.39786e+06,801,18510,217819

System contains 7.0963e+20 deadlocks (shown below if less than --print-limit option) !
FORMULA ASLink-PT-08a-ReachabilityDeadlock-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
[ u287={[ ]
} u285={[ p1629=1 ]
} i63={[ u324={[ ]
} u323={[ ]
} u322={[ ]
} u321={[ ]
} u317={[ ]
} u316={[ ]
} u315={[ ]
} u314={[ ]
} u313={[ ]
} u311={[ ]
} u312={[ ]
} u310={[ ]
} u309={[ ]
} u331={[ p1659=1 ]
[ p1661=1 ]
} u308={[ ]
} u307={[ ]
} u306={[ ]
} u305={[ ]
} u304={[ ]
} u302={[ ]
} u303={[ ]
} u301={[ ]
} u300={[ ]
} u299={[ ]
} u290={[ ]
} u289={[ ]
} u298={[ ]
} u297={[ ]
} u296={[ ]
} u292={[ ]
} u295={[ ]
} u291={[ ]
} u294={[ ]
} u293={[ ]
} ]
} u284={[ p1611=1 ]
} u286={[ p1654=1 ]
} u249={[ p1401=1 ]
} u280={[ p1584=1 ]
} u250={[ p1418=1 ]
} i55={[ u276={[ ]
} u274={[ ]
} u268={[ p1540=1 ]
} u358={[ ]
} u263={[ ]
} i7={[ u371={[ p1543=1 ]
} u272={[ ]
} ]
} i5={[ u374={[ ]
} u267={[ ]
} ]
} u258={[ ]
} u253={[ ]
} i3={[ u375={[ ]
} u262={[ ]
} ]
} i1={[ u357={[ ]
} u257={[ ]
} ]
} ]
[ u276={[ ]
} u274={[ ]
} u268={[ ]
} u358={[ ]
} u263={[ p1520=1 ]
} i7={[ u371={[ ]
} u272={[ ]
} ]
} i5={[ u374={[ p1523=1 ]
} u267={[ ]
} ]
} u258={[ ]
} u253={[ ]
} i3={[ u375={[ ]
} u262={[ ]
} ]
} i1={[ u357={[ ]
} u257={[ ]
} ]
} ]
[ u276={[ ]
} u274={[ ]
} u268={[ ]
} u358={[ ]
} u263={[ ]
} i7={[ u371={[ ]
} u272={[ ]
} ]
} i5={[ u374={[ ]
} u267={[ ]
} ]
} u258={[ p1498=1 ]
} u253={[ ]
} i3={[ u375={[ p1501=1 ]
} u262={[ ]
} ]
} i1={[ u357={[ ]
} u257={[ ]
} ]
} ]
[ u276={[ ]
} u274={[ ]
} u268={[ ]
} u358={[ ]
} u263={[ ]
} i7={[ u371={[ ]
} u272={[ ]
} ]
} i5={[ u374={[ ]
} u267={[ ]
} ]
} u258={[ ]
} u253={[ p1464=1 ]
} i3={[ u375={[ ]
} u262={[ ]
} ]
} i1={[ u357={[ p1467=1 ]
} u257={[ ]
} ]
} ]
} u283={[ p1593=1 ]
} u251={[ p1436=1 ]
} u214={[ p1206=1 ]
} i56={[ u367={[ ]
} u279={[ p1572=1 ]
} u278={[ p1569=1 ]
} ]
} u215={[ p1223=1 ]
} u245={[ p1382=1 ]
} i48={[ u241={[ ]
} u239={[ ]
} u233={[ p1346=1 ]
} u355={[ ]
} u228={[ ]
} i7={[ u348={[ p1348=1 ]
} u237={[ ]
} ]
} i5={[ u349={[ ]
} u232={[ ]
} ]
} u223={[ ]
} u218={[ ]
} i3={[ u352={[ ]
} u227={[ ]
} ]
} i1={[ u354={[ ]
} u222={[ ]
} ]
} ]
[ u241={[ ]
} u239={[ ]
} u233={[ ]
} u355={[ ]
} u228={[ p1326=1 ]
} i7={[ u348={[ ]
} u237={[ ]
} ]
} i5={[ u349={[ p1328=1 ]
} u232={[ ]
} ]
} u223={[ ]
} u218={[ ]
} i3={[ u352={[ ]
} u227={[ ]
} ]
} i1={[ u354={[ ]
} u222={[ ]
} ]
} ]
[ u241={[ ]
} u239={[ ]
} u233={[ ]
} u355={[ ]
} u228={[ ]
} i7={[ u348={[ ]
} u237={[ ]
} ]
} i5={[ u349={[ ]
} u232={[ ]
} ]
} u223={[ p1304=1 ]
} u218={[ ]
} i3={[ u352={[ p1306=1 ]
} u227={[ ]
} ]
} i1={[ u354={[ ]
} u222={[ ]
} ]
} ]
[ u241={[ ]
} u239={[ ]
} u233={[ ]
} u355={[ ]
} u228={[ ]
} i7={[ u348={[ ]
} u237={[ ]
} ]
} i5={[ u349={[ ]
} u232={[ ]
} ]
} u223={[ ]
} u218={[ p1270=1 ]
} i3={[ u352={[ ]
} u227={[ ]
} ]
} i1={[ u354={[ p1272=1 ]
} u222={[ ]
} ]
} ]
} u248={[ p1398=1 ]
} u216={[ p1241=1 ]
} i49={[ u362={[ ]
} u244={[ ]
} u243={[ p1374=1 ]
} ]
} u179={[ p1011=1 ]
} u180={[ p1028=1 ]
} u210={[ p1187=1 ]
} i41={[ u206={[ ]
} u204={[ ]
} u198={[ p1151=1 ]
} u341={[ ]
} u193={[ ]
} i7={[ u337={[ p1153=1 ]
} u202={[ ]
} ]
} i5={[ u336={[ ]
} u197={[ ]
} ]
} u188={[ ]
} u183={[ ]
} i3={[ u343={[ ]
} u192={[ ]
} ]
} i1={[ u344={[ ]
} u187={[ ]
} ]
} ]
[ u206={[ ]
} u204={[ ]
} u198={[ ]
} u341={[ ]
} u193={[ p1131=1 ]
} i7={[ u337={[ ]
} u202={[ ]
} ]
} i5={[ u336={[ p1133=1 ]
} u197={[ ]
} ]
} u188={[ ]
} u183={[ ]
} i3={[ u343={[ ]
} u192={[ ]
} ]
} i1={[ u344={[ ]
} u187={[ ]
} ]
} ]
[ u206={[ ]
} u204={[ ]
} u198={[ ]
} u341={[ ]
} u193={[ ]
} i7={[ u337={[ ]
} u202={[ ]
} ]
} i5={[ u336={[ ]
} u197={[ ]
} ]
} u188={[ p1109=1 ]
} u183={[ ]
} i3={[ u343={[ p1111=1 ]
} u192={[ ]
} ]
} i1={[ u344={[ ]
} u187={[ ]
} ]
} ]
[ u206={[ ]
} u204={[ ]
} u198={[ ]
} u341={[ ]
} u193={[ ]
} i7={[ u337={[ ]
} u202={[ ]
} ]
} i5={[ u336={[ ]
} u197={[ ]
} ]
} u188={[ ]
} u183={[ p1075=1 ]
} i3={[ u343={[ ]
} u192={[ ]
} ]
} i1={[ u344={[ p1077=1 ]
} u187={[ ]
} ]
} ]
} u213={[ p1203=1 ]
} u181={[ p1046=1 ]
} i42={[ u345={[ ]
} u209={[ ]
} u208={[ p1179=1 ]
} ]
} u144={[ p816=1 ]
} u145={[ p833=1 ]
} u175={[ p992=1 ]
} i34={[ u171={[ ]
} u169={[ ]
} u163={[ p956=1 ]
} u373={[ ]
} u158={[ ]
} i7={[ u332={[ p958=1 ]
} u167={[ ]
} ]
} i5={[ u334={[ ]
} u162={[ ]
} ]
} u153={[ ]
} u148={[ ]
} i3={[ u368={[ ]
} u157={[ ]
} ]
} i1={[ u369={[ ]
} u152={[ ]
} ]
} ]
[ u171={[ ]
} u169={[ ]
} u163={[ ]
} u373={[ ]
} u158={[ p936=1 ]
} i7={[ u332={[ ]
} u167={[ ]
} ]
} i5={[ u334={[ p938=1 ]
} u162={[ ]
} ]
} u153={[ ]
} u148={[ ]
} i3={[ u368={[ ]
} u157={[ ]
} ]
} i1={[ u369={[ ]
} u152={[ ]
} ]
} ]
[ u171={[ ]
} u169={[ ]
} u163={[ ]
} u373={[ ]
} u158={[ ]
} i7={[ u332={[ ]
} u167={[ ]
} ]
} i5={[ u334={[ ]
} u162={[ ]
} ]
} u153={[ p914=1 ]
} u148={[ ]
} i3={[ u368={[ p916=1 ]
} u157={[ ]
} ]
} i1={[ u369={[ ]
} u152={[ ]
} ]
} ]
[ u171={[ ]
} u169={[ ]
} u163={[ ]
} u373={[ ]
} u158={[ ]
} i7={[ u332={[ ]
} u167={[ ]
} ]
} i5={[ u334={[ ]
} u162={[ ]
} ]
} u153={[ ]
} u148={[ p880=1 ]
} i3={[ u368={[ ]
} u157={[ ]
} ]
} i1={[ u369={[ p882=1 ]
} u152={[ ]
} ]
} ]
} u178={[ p1008=1 ]
} u146={[ p851=1 ]
} i35={[ u328={[ ]
} u174={[ ]
} u173={[ p984=1 ]
} ]
} u109={[ p621=1 ]
} u110={[ p638=1 ]
} u140={[ p797=1 ]
} i27={[ u136={[ ]
} u134={[ ]
} u128={[ p761=1 ]
} u346={[ ]
} u123={[ ]
} i7={[ u360={[ p763=1 ]
} u132={[ ]
} ]
} i5={[ u361={[ ]
} u127={[ ]
} ]
} u118={[ ]
} u113={[ ]
} i3={[ u363={[ ]
} u122={[ ]
} ]
} i1={[ u347={[ ]
} u117={[ ]
} ]
} ]
[ u136={[ ]
} u134={[ ]
} u128={[ ]
} u346={[ ]
} u123={[ p741=1 ]
} i7={[ u360={[ ]
} u132={[ ]
} ]
} i5={[ u361={[ p743=1 ]
} u127={[ ]
} ]
} u118={[ ]
} u113={[ ]
} i3={[ u363={[ ]
} u122={[ ]
} ]
} i1={[ u347={[ ]
} u117={[ ]
} ]
} ]
[ u136={[ ]
} u134={[ ]
} u128={[ ]
} u346={[ ]
} u123={[ ]
} i7={[ u360={[ ]
} u132={[ ]
} ]
} i5={[ u361={[ ]
} u127={[ ]
} ]
} u118={[ p719=1 ]
} u113={[ ]
} i3={[ u363={[ p721=1 ]
} u122={[ ]
} ]
} i1={[ u347={[ ]
} u117={[ ]
} ]
} ]
[ u136={[ ]
} u134={[ ]
} u128={[ ]
} u346={[ ]
} u123={[ ]
} i7={[ u360={[ ]
} u132={[ ]
} ]
} i5={[ u361={[ ]
} u127={[ ]
} ]
} u118={[ ]
} u113={[ p685=1 ]
} i3={[ u363={[ ]
} u122={[ ]
} ]
} i1={[ u347={[ p687=1 ]
} u117={[ ]
} ]
} ]
} u143={[ p813=1 ]
} u111={[ p656=1 ]
} i28={[ u376={[ ]
} u139={[ ]
} u138={[ p789=1 ]
} ]
} u74={[ p426=1 ]
} u75={[ p443=1 ]
} u105={[ p602=1 ]
} i20={[ u101={[ ]
} u99={[ ]
} u93={[ p566=1 ]
} u329={[ ]
} u88={[ ]
} i7={[ u338={[ p568=1 ]
} u97={[ ]
} ]
} i5={[ u335={[ ]
} u92={[ ]
} ]
} u83={[ ]
} u78={[ ]
} i3={[ u333={[ ]
} u87={[ ]
} ]
} i1={[ u330={[ ]
} u82={[ ]
} ]
} ]
[ u101={[ ]
} u99={[ ]
} u93={[ ]
} u329={[ ]
} u88={[ p546=1 ]
} i7={[ u338={[ ]
} u97={[ ]
} ]
} i5={[ u335={[ p548=1 ]
} u92={[ ]
} ]
} u83={[ ]
} u78={[ ]
} i3={[ u333={[ ]
} u87={[ ]
} ]
} i1={[ u330={[ ]
} u82={[ ]
} ]
} ]
[ u101={[ ]
} u99={[ ]
} u93={[ ]
} u329={[ ]
} u88={[ ]
} i7={[ u338={[ ]
} u97={[ ]
} ]
} i5={[ u335={[ ]
} u92={[ ]
} ]
} u83={[ p524=1 ]
} u78={[ ]
} i3={[ u333={[ p526=1 ]
} u87={[ ]
} ]
} i1={[ u330={[ ]
} u82={[ ]
} ]
} ]
[ u101={[ ]
} u99={[ ]
} u93={[ ]
} u329={[ ]
} u88={[ ]
} i7={[ u338={[ ]
} u97={[ ]
} ]
} i5={[ u335={[ ]
} u92={[ ]
} ]
} u83={[ ]
} u78={[ p490=1 ]
} i3={[ u333={[ ]
} u87={[ ]
} ]
} i1={[ u330={[ p492=1 ]
} u82={[ ]
} ]
} ]
} u108={[ p618=1 ]
} u76={[ p461=1 ]
} i21={[ u353={[ ]
} u104={[ ]
} u103={[ p594=1 ]
} ]
} u39={[ p231=1 ]
} u70={[ p407=1 ]
} u40={[ p248=1 ]
} i14={[ u377={[ ]
} u69={[ ]
} u68={[ p399=1 ]
} ]
} i13={[ u66={[ ]
} u64={[ ]
} u58={[ p371=1 ]
} u364={[ ]
} u53={[ ]
} i7={[ u372={[ p373=1 ]
} u62={[ ]
} ]
} i5={[ u370={[ ]
} u57={[ ]
} ]
} u48={[ ]
} u43={[ ]
} i3={[ u366={[ ]
} u52={[ ]
} ]
} i1={[ u365={[ ]
} u47={[ ]
} ]
} ]
[ u66={[ ]
} u64={[ ]
} u58={[ ]
} u364={[ ]
} u53={[ p351=1 ]
} i7={[ u372={[ ]
} u62={[ ]
} ]
} i5={[ u370={[ p353=1 ]
} u57={[ ]
} ]
} u48={[ ]
} u43={[ ]
} i3={[ u366={[ ]
} u52={[ ]
} ]
} i1={[ u365={[ ]
} u47={[ ]
} ]
} ]
[ u66={[ ]
} u64={[ ]
} u58={[ ]
} u364={[ ]
} u53={[ ]
} i7={[ u372={[ ]
} u62={[ ]
} ]
} i5={[ u370={[ ]
} u57={[ ]
} ]
} u48={[ p329=1 ]
} u43={[ ]
} i3={[ u366={[ p331=1 ]
} u52={[ ]
} ]
} i1={[ u365={[ ]
} u47={[ ]
} ]
} ]
[ u66={[ ]
} u64={[ ]
} u58={[ ]
} u364={[ ]
} u53={[ ]
} i7={[ u372={[ ]
} u62={[ ]
} ]
} i5={[ u370={[ ]
} u57={[ ]
} ]
} u48={[ ]
} u43={[ p295=1 ]
} i3={[ u366={[ ]
} u52={[ ]
} ]
} i1={[ u365={[ p297=1 ]
} u47={[ ]
} ]
} ]
} u73={[ p423=1 ]
} u359={[ ]
} u35={[ p212=1 ]
} u41={[ p266=1 ]
} u3={[ ]
} u5={[ p54=1 ]
} u2={[ p21=1 ]
} u4={[ p37=1 ]
} i6={[ u31={[ ]
} u29={[ ]
} u23={[ p177=1 ]
} u340={[ ]
} u18={[ ]
} i7={[ u356={[ p179=1 ]
} u27={[ ]
} ]
} i5={[ u351={[ ]
} u22={[ ]
} ]
} u13={[ ]
} u8={[ ]
} i3={[ u350={[ ]
} u17={[ ]
} ]
} i1={[ u342={[ ]
} u12={[ ]
} ]
} ]
[ u31={[ ]
} u29={[ ]
} u23={[ ]
} u340={[ ]
} u18={[ p157=1 ]
} i7={[ u356={[ ]
} u27={[ ]
} ]
} i5={[ u351={[ p159=1 ]
} u22={[ ]
} ]
} u13={[ ]
} u8={[ ]
} i3={[ u350={[ ]
} u17={[ ]
} ]
} i1={[ u342={[ ]
} u12={[ ]
} ]
} ]
[ u31={[ ]
} u29={[ ]
} u23={[ ]
} u340={[ ]
} u18={[ ]
} i7={[ u356={[ ]
} u27={[ ]
} ]
} i5={[ u351={[ ]
} u22={[ ]
} ]
} u13={[ p135=1 ]
} u8={[ ]
} i3={[ u350={[ p137=1 ]
} u17={[ ]
} ]
} i1={[ u342={[ ]
} u12={[ ]
} ]
} ]
[ u31={[ ]
} u29={[ ]
} u23={[ ]
} u340={[ ]
} u18={[ ]
} i7={[ u356={[ ]
} u27={[ ]
} ]
} i5={[ u351={[ ]
} u22={[ ]
} ]
} u13={[ ]
} u8={[ p101=1 ]
} i3={[ u350={[ ]
} u17={[ ]
} ]
} i1={[ u342={[ p103=1 ]
} u12={[ ]
} ]
} ]
} u38={[ p228=1 ]
} u1={[ p2=1 ]
[ p18=1 ]
} u6={[ p72=1 ]
} ]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527845476731

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 01, 2018 9:29:47 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
Jun 01, 2018 9:29:47 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 01, 2018 9:29:48 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 315 ms
Jun 01, 2018 9:29:48 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 1796 places.
Jun 01, 2018 9:29:48 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 2646 transitions.
Jun 01, 2018 9:29:48 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
Jun 01, 2018 9:29:48 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 67 ms
Jun 01, 2018 9:29:49 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 662 ms
Jun 01, 2018 9:29:49 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 32 ms
Jun 01, 2018 9:29:49 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 2646 transitions.
Jun 01, 2018 9:29:53 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Jun 01, 2018 9:29:53 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1967 transitions.
Jun 01, 2018 9:29:53 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Too many transitions (1967) to apply POR reductions. Disabling POR matrices.
Jun 01, 2018 9:29:53 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 307 ms
Jun 01, 2018 9:29:54 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 432ms conformant to PINS in folder :/home/mcc/execution
Jun 01, 2018 9:29:54 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 250 ms
Jun 01, 2018 9:29:54 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Jun 01, 2018 9:29:54 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 236 ms
Jun 01, 2018 9:29:54 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
Jun 01, 2018 9:29:55 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 2740 redundant transitions.
Jun 01, 2018 9:29:55 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 36 ms

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ASLink-PT-08a"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/ASLink-PT-08a.tgz
mv ASLink-PT-08a execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is ASLink-PT-08a, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r273-smll-152749149600134"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;