fond
Model Checking Contest 2018
8th edition, Bratislava, Slovakia, June 26, 2018
Execution of r273-smll-152749149600116
Last Updated
June 26, 2018

About the Execution of ITS-Tools.L for ASLink-PT-07a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15753.940 99393.00 203954.00 309.40 T normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
...................
/home/mcc/execution
total 848K
-rw-r--r-- 1 mcc users 3.3K May 29 16:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 18K May 29 16:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K May 28 11:15 CTLFireability.txt
-rw-r--r-- 1 mcc users 19K May 28 11:15 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.6K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.6K May 28 09:23 LTLCardinality.txt
-rw-r--r-- 1 mcc users 13K May 28 09:23 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.7K May 28 07:38 LTLFireability.txt
-rw-r--r-- 1 mcc users 6.8K May 28 07:38 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.8K May 27 05:08 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 20K May 27 05:08 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 104 May 26 06:29 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 342 May 26 06:29 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.6K May 26 06:35 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 15K May 26 06:35 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 28 07:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 28 07:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 4 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 677K May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is ASLink-PT-07a, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r273-smll-152749149600116

=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ASLink-PT-07a-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1527829021483

Flatten gal took : 625 ms
Constant places removed 29 places and 1 transitions.
Reduce isomorphic transitions removed 25 transitions.
Implicit places reduction removed 14 places :[p1458, p1391, p1196, p1184, p1001, p989, p806, p794, p611, p599, p416, p404, p221, p209]
Performed 301 Post agglomeration using F-continuation condition.
Iterating post reduction 0 with 369 rules applied. Total rules applied 369 place count 1558 transition count 2046
Constant places removed 374 places and 0 transitions.
Performed 23 Post agglomeration using F-continuation condition.
Iterating post reduction 1 with 397 rules applied. Total rules applied 766 place count 1184 transition count 2023
Constant places removed 24 places and 0 transitions.
Implicit places reduction removed 8 places :[p1368, p1173, p978, p783, p588, p393, p206, p199]
Performed 8 Post agglomeration using F-continuation condition.
Iterating post reduction 2 with 40 rules applied. Total rules applied 806 place count 1152 transition count 2015
Constant places removed 8 places and 0 transitions.
Iterating post reduction 3 with 8 rules applied. Total rules applied 814 place count 1144 transition count 2015
Performed 28 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 4 with 28 Pre rules applied. Total rules applied 814 place count 1144 transition count 1987
Constant places removed 28 places and 0 transitions.
Iterating post reduction 4 with 28 rules applied. Total rules applied 842 place count 1116 transition count 1987
Symmetric choice reduction at 5 with 17 rule applications. Total rules 859 place count 1116 transition count 1987
Constant places removed 17 places and 60 transitions.
Reduce isomorphic transitions removed 2 transitions.
Implicit places reduction removed 10 places :[p1600, p1461, p1359, p1164, p969, p774, p579, p384, p190, p23]
Performed 11 Post agglomeration using F-continuation condition.
Iterating post reduction 5 with 40 rules applied. Total rules applied 899 place count 1089 transition count 1914
Constant places removed 11 places and 0 transitions.
Iterating post reduction 6 with 11 rules applied. Total rules applied 910 place count 1078 transition count 1914
Symmetric choice reduction at 7 with 8 rule applications. Total rules 918 place count 1078 transition count 1914
Constant places removed 8 places and 15 transitions.
Iterating post reduction 7 with 8 rules applied. Total rules applied 926 place count 1070 transition count 1899
Symmetric choice reduction at 8 with 1 rule applications. Total rules 927 place count 1070 transition count 1899
Constant places removed 1 places and 8 transitions.
Iterating post reduction 8 with 1 rules applied. Total rules applied 928 place count 1069 transition count 1891
Symmetric choice reduction at 9 with 1 rule applications. Total rules 929 place count 1069 transition count 1891
Constant places removed 1 places and 8 transitions.
Iterating post reduction 9 with 1 rules applied. Total rules applied 930 place count 1068 transition count 1883
Symmetric choice reduction at 10 with 1 rule applications. Total rules 931 place count 1068 transition count 1883
Constant places removed 1 places and 8 transitions.
Iterating post reduction 10 with 1 rules applied. Total rules applied 932 place count 1067 transition count 1875
Symmetric choice reduction at 11 with 1 rule applications. Total rules 933 place count 1067 transition count 1875
Constant places removed 1 places and 8 transitions.
Iterating post reduction 11 with 1 rules applied. Total rules applied 934 place count 1066 transition count 1867
Symmetric choice reduction at 12 with 1 rule applications. Total rules 935 place count 1066 transition count 1867
Constant places removed 1 places and 8 transitions.
Iterating post reduction 12 with 1 rules applied. Total rules applied 936 place count 1065 transition count 1859
Symmetric choice reduction at 13 with 1 rule applications. Total rules 937 place count 1065 transition count 1859
Constant places removed 1 places and 8 transitions.
Iterating post reduction 13 with 1 rules applied. Total rules applied 938 place count 1064 transition count 1851
Symmetric choice reduction at 14 with 1 rule applications. Total rules 939 place count 1064 transition count 1851
Constant places removed 1 places and 8 transitions.
Iterating post reduction 14 with 1 rules applied. Total rules applied 940 place count 1063 transition count 1843
Symmetric choice reduction at 15 with 1 rule applications. Total rules 941 place count 1063 transition count 1843
Constant places removed 1 places and 8 transitions.
Iterating post reduction 15 with 1 rules applied. Total rules applied 942 place count 1062 transition count 1835
Symmetric choice reduction at 16 with 1 rule applications. Total rules 943 place count 1062 transition count 1835
Constant places removed 1 places and 8 transitions.
Iterating post reduction 16 with 1 rules applied. Total rules applied 944 place count 1061 transition count 1827
Symmetric choice reduction at 17 with 1 rule applications. Total rules 945 place count 1061 transition count 1827
Constant places removed 1 places and 8 transitions.
Iterating post reduction 17 with 1 rules applied. Total rules applied 946 place count 1060 transition count 1819
Symmetric choice reduction at 18 with 1 rule applications. Total rules 947 place count 1060 transition count 1819
Constant places removed 1 places and 8 transitions.
Iterating post reduction 18 with 1 rules applied. Total rules applied 948 place count 1059 transition count 1811
Symmetric choice reduction at 19 with 1 rule applications. Total rules 949 place count 1059 transition count 1811
Constant places removed 1 places and 8 transitions.
Iterating post reduction 19 with 1 rules applied. Total rules applied 950 place count 1058 transition count 1803
Symmetric choice reduction at 20 with 1 rule applications. Total rules 951 place count 1058 transition count 1803
Constant places removed 1 places and 8 transitions.
Iterating post reduction 20 with 1 rules applied. Total rules applied 952 place count 1057 transition count 1795
Symmetric choice reduction at 21 with 1 rule applications. Total rules 953 place count 1057 transition count 1795
Constant places removed 1 places and 8 transitions.
Iterating post reduction 21 with 1 rules applied. Total rules applied 954 place count 1056 transition count 1787
Symmetric choice reduction at 22 with 1 rule applications. Total rules 955 place count 1056 transition count 1787
Constant places removed 1 places and 8 transitions.
Iterating post reduction 22 with 1 rules applied. Total rules applied 956 place count 1055 transition count 1779
Performed 22 Post agglomeration using F-continuation condition.
Constant places removed 22 places and 0 transitions.
Iterating post reduction 23 with 22 rules applied. Total rules applied 978 place count 1033 transition count 1757
Applied a total of 978 rules in 1810 ms. Remains 1033 /1601 variables (removed 568) and now considering 1757/2373 (removed 616) transitions.
// Phase 1: matrix 1757 rows 1033 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
built 85 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 100 ordering constraints for composite.
Compilation finished in 26043 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 62 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -d], workingDir=/home/mcc/execution]
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,1.19088e+27,87.4844,1714648,6146,588,3.3027e+06,1908,2989,4.39508e+06,150,14532,0


Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,2.7996e+18,89.3941,1714648,1192,231,3.3027e+06,6497,8941,4.39508e+06,775,17719,203129

System contains 2.7996e+18 deadlocks (shown below if less than --print-limit option) !
FORMULA ASLink-PT-07a-ReachabilityDeadlock-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
[ 2799602283312780576 states ] showing 10 first states
[ u250={[ p1434=1 ]
} u249={[ p1416=1 ]
} u245={[ p1389=1 ]
} u215={[ p1223=1 ]
} u214={[ p1206=1 ]
} i56={[ u289={[ ]
} u288={[ ]
} u287={[ ]
} u286={[ ]
} u282={[ ]
} u281={[ ]
} u280={[ ]
} u279={[ ]
} u278={[ ]
} u276={[ ]
} u277={[ ]
} u275={[ ]
} u274={[ ]
} u321={[ p1464=1 ]
[ p1466=1 ]
[ p1468=1 ]
[ p1470=1 ]
} u273={[ ]
} u272={[ ]
} u271={[ ]
} u270={[ ]
} u269={[ ]
} u267={[ ]
} u268={[ ]
} u266={[ ]
} u265={[ ]
} u264={[ ]
} u255={[ ]
} u254={[ ]
} u263={[ ]
} u262={[ ]
} u261={[ ]
} u257={[ ]
} u260={[ ]
} u256={[ ]
} u259={[ ]
} u258={[ ]
} ]
} u252={[ ]
} u251={[ p1459=1 ]
} i48={[ u241={[ ]
} u239={[ ]
} u233={[ p1345=1 ]
} u319={[ ]
} u228={[ ]
} i7={[ u312={[ p1348=1 ]
} u237={[ ]
} ]
} i5={[ u313={[ ]
} u232={[ ]
} ]
} u223={[ ]
} u218={[ ]
} i3={[ u316={[ ]
} u227={[ ]
} ]
} i1={[ u318={[ ]
} u222={[ ]
} ]
} ]
[ u241={[ ]
} u239={[ ]
} u233={[ ]
} u319={[ ]
} u228={[ p1325=1 ]
} i7={[ u312={[ ]
} u237={[ ]
} ]
} i5={[ u313={[ p1328=1 ]
} u232={[ ]
} ]
} u223={[ ]
} u218={[ ]
} i3={[ u316={[ ]
} u227={[ ]
} ]
} i1={[ u318={[ ]
} u222={[ ]
} ]
} ]
[ u241={[ ]
} u239={[ ]
} u233={[ ]
} u319={[ ]
} u228={[ ]
} i7={[ u312={[ ]
} u237={[ ]
} ]
} i5={[ u313={[ ]
} u232={[ ]
} ]
} u223={[ p1303=1 ]
} u218={[ ]
} i3={[ u316={[ p1306=1 ]
} u227={[ ]
} ]
} i1={[ u318={[ ]
} u222={[ ]
} ]
} ]
[ u241={[ ]
} u239={[ ]
} u233={[ ]
} u319={[ ]
} u228={[ ]
} i7={[ u312={[ ]
} u237={[ ]
} ]
} i5={[ u313={[ ]
} u232={[ ]
} ]
} u223={[ ]
} u218={[ p1269=1 ]
} i3={[ u316={[ ]
} u227={[ ]
} ]
} i1={[ u318={[ p1272=1 ]
} u222={[ ]
} ]
} ]
} u248={[ p1398=1 ]
} u216={[ p1241=1 ]
} i49={[ u325={[ ]
} u244={[ p1377=1 ]
} u243={[ p1374=1 ]
} ]
} u179={[ p1011=1 ]
} u180={[ p1028=1 ]
} u210={[ p1193=1 ]
} i41={[ u206={[ ]
} u204={[ ]
} u198={[ p1150=1 ]
} u305={[ ]
} u193={[ ]
} i7={[ u301={[ p1153=1 ]
} u202={[ ]
} ]
} i5={[ u300={[ ]
} u197={[ ]
} ]
} u188={[ ]
} u183={[ ]
} i3={[ u307={[ ]
} u192={[ ]
} ]
} i1={[ u308={[ ]
} u187={[ ]
} ]
} ]
[ u206={[ ]
} u204={[ ]
} u198={[ ]
} u305={[ ]
} u193={[ p1130=1 ]
} i7={[ u301={[ ]
} u202={[ ]
} ]
} i5={[ u300={[ p1133=1 ]
} u197={[ ]
} ]
} u188={[ ]
} u183={[ ]
} i3={[ u307={[ ]
} u192={[ ]
} ]
} i1={[ u308={[ ]
} u187={[ ]
} ]
} ]
[ u206={[ ]
} u204={[ ]
} u198={[ ]
} u305={[ ]
} u193={[ ]
} i7={[ u301={[ ]
} u202={[ ]
} ]
} i5={[ u300={[ ]
} u197={[ ]
} ]
} u188={[ p1108=1 ]
} u183={[ ]
} i3={[ u307={[ p1111=1 ]
} u192={[ ]
} ]
} i1={[ u308={[ ]
} u187={[ ]
} ]
} ]
[ u206={[ ]
} u204={[ ]
} u198={[ ]
} u305={[ ]
} u193={[ ]
} i7={[ u301={[ ]
} u202={[ ]
} ]
} i5={[ u300={[ ]
} u197={[ ]
} ]
} u188={[ ]
} u183={[ p1074=1 ]
} i3={[ u307={[ ]
} u192={[ ]
} ]
} i1={[ u308={[ p1077=1 ]
} u187={[ ]
} ]
} ]
} u213={[ p1203=1 ]
} u181={[ p1046=1 ]
} i42={[ u309={[ ]
} u209={[ p1182=1 ]
} u208={[ p1179=1 ]
} ]
} u144={[ p816=1 ]
} u145={[ p833=1 ]
} u175={[ p998=1 ]
} i34={[ u171={[ ]
} u169={[ ]
} u163={[ p955=1 ]
} u334={[ ]
} u158={[ ]
} i7={[ u296={[ p958=1 ]
} u167={[ ]
} ]
} i5={[ u298={[ ]
} u162={[ ]
} ]
} u153={[ ]
} u148={[ ]
} i3={[ u330={[ ]
} u157={[ ]
} ]
} i1={[ u331={[ ]
} u152={[ ]
} ]
} ]
[ u171={[ ]
} u169={[ ]
} u163={[ ]
} u334={[ ]
} u158={[ p935=1 ]
} i7={[ u296={[ ]
} u167={[ ]
} ]
} i5={[ u298={[ p938=1 ]
} u162={[ ]
} ]
} u153={[ ]
} u148={[ ]
} i3={[ u330={[ ]
} u157={[ ]
} ]
} i1={[ u331={[ ]
} u152={[ ]
} ]
} ]
[ u171={[ ]
} u169={[ ]
} u163={[ ]
} u334={[ ]
} u158={[ ]
} i7={[ u296={[ ]
} u167={[ ]
} ]
} i5={[ u298={[ ]
} u162={[ ]
} ]
} u153={[ p913=1 ]
} u148={[ ]
} i3={[ u330={[ p916=1 ]
} u157={[ ]
} ]
} i1={[ u331={[ ]
} u152={[ ]
} ]
} ]
[ u171={[ ]
} u169={[ ]
} u163={[ ]
} u334={[ ]
} u158={[ ]
} i7={[ u296={[ ]
} u167={[ ]
} ]
} i5={[ u298={[ ]
} u162={[ ]
} ]
} u153={[ ]
} u148={[ p879=1 ]
} i3={[ u330={[ ]
} u157={[ ]
} ]
} i1={[ u331={[ p882=1 ]
} u152={[ ]
} ]
} ]
} u178={[ p1008=1 ]
} u146={[ p851=1 ]
} i35={[ u293={[ ]
} u174={[ p987=1 ]
} u173={[ p984=1 ]
} ]
} u109={[ p621=1 ]
} u110={[ p638=1 ]
} u140={[ p803=1 ]
} i27={[ u136={[ ]
} u134={[ ]
} u128={[ p760=1 ]
} u310={[ ]
} u123={[ ]
} i7={[ u323={[ p763=1 ]
} u132={[ ]
} ]
} i5={[ u324={[ ]
} u127={[ ]
} ]
} u118={[ ]
} u113={[ ]
} i3={[ u326={[ ]
} u122={[ ]
} ]
} i1={[ u311={[ ]
} u117={[ ]
} ]
} ]
[ u136={[ ]
} u134={[ ]
} u128={[ ]
} u310={[ ]
} u123={[ p740=1 ]
} i7={[ u323={[ ]
} u132={[ ]
} ]
} i5={[ u324={[ p743=1 ]
} u127={[ ]
} ]
} u118={[ ]
} u113={[ ]
} i3={[ u326={[ ]
} u122={[ ]
} ]
} i1={[ u311={[ ]
} u117={[ ]
} ]
} ]
[ u136={[ ]
} u134={[ ]
} u128={[ ]
} u310={[ ]
} u123={[ ]
} i7={[ u323={[ ]
} u132={[ ]
} ]
} i5={[ u324={[ ]
} u127={[ ]
} ]
} u118={[ p718=1 ]
} u113={[ ]
} i3={[ u326={[ p721=1 ]
} u122={[ ]
} ]
} i1={[ u311={[ ]
} u117={[ ]
} ]
} ]
[ u136={[ ]
} u134={[ ]
} u128={[ ]
} u310={[ ]
} u123={[ ]
} i7={[ u323={[ ]
} u132={[ ]
} ]
} i5={[ u324={[ ]
} u127={[ ]
} ]
} u118={[ ]
} u113={[ p684=1 ]
} i3={[ u326={[ ]
} u122={[ ]
} ]
} i1={[ u311={[ p687=1 ]
} u117={[ ]
} ]
} ]
} u143={[ p813=1 ]
} u111={[ p656=1 ]
} i28={[ u335={[ ]
} u139={[ p792=1 ]
} u138={[ p789=1 ]
} ]
} u74={[ p426=1 ]
} u75={[ p443=1 ]
} u105={[ p608=1 ]
} i20={[ u101={[ ]
} u99={[ ]
} u93={[ p565=1 ]
} u294={[ ]
} u88={[ ]
} i7={[ u302={[ p568=1 ]
} u97={[ ]
} ]
} i5={[ u299={[ ]
} u92={[ ]
} ]
} u83={[ ]
} u78={[ ]
} i3={[ u297={[ ]
} u87={[ ]
} ]
} i1={[ u295={[ ]
} u82={[ ]
} ]
} ]
[ u101={[ ]
} u99={[ ]
} u93={[ ]
} u294={[ ]
} u88={[ p545=1 ]
} i7={[ u302={[ ]
} u97={[ ]
} ]
} i5={[ u299={[ p548=1 ]
} u92={[ ]
} ]
} u83={[ ]
} u78={[ ]
} i3={[ u297={[ ]
} u87={[ ]
} ]
} i1={[ u295={[ ]
} u82={[ ]
} ]
} ]
[ u101={[ ]
} u99={[ ]
} u93={[ ]
} u294={[ ]
} u88={[ ]
} i7={[ u302={[ ]
} u97={[ ]
} ]
} i5={[ u299={[ ]
} u92={[ ]
} ]
} u83={[ p523=1 ]
} u78={[ ]
} i3={[ u297={[ p526=1 ]
} u87={[ ]
} ]
} i1={[ u295={[ ]
} u82={[ ]
} ]
} ]
[ u101={[ ]
} u99={[ ]
} u93={[ ]
} u294={[ ]
} u88={[ ]
} i7={[ u302={[ ]
} u97={[ ]
} ]
} i5={[ u299={[ ]
} u92={[ ]
} ]
} u83={[ ]
} u78={[ p489=1 ]
} i3={[ u297={[ ]
} u87={[ ]
} ]
} i1={[ u295={[ p492=1 ]
} u82={[ ]
} ]
} ]
} u108={[ p618=1 ]
} u76={[ p461=1 ]
} i21={[ u317={[ ]
} u104={[ p597=1 ]
} u103={[ p594=1 ]
} ]
} u39={[ p231=1 ]
} u70={[ p413=1 ]
} u40={[ p248=1 ]
} i14={[ u336={[ ]
} u69={[ p402=1 ]
} u68={[ p399=1 ]
} ]
} i13={[ u66={[ ]
} u64={[ ]
} u58={[ p370=1 ]
} u327={[ ]
} u53={[ ]
} i7={[ u333={[ p373=1 ]
} u62={[ ]
} ]
} i5={[ u332={[ ]
} u57={[ ]
} ]
} u48={[ ]
} u43={[ ]
} i3={[ u329={[ ]
} u52={[ ]
} ]
} i1={[ u328={[ ]
} u47={[ ]
} ]
} ]
[ u66={[ ]
} u64={[ ]
} u58={[ ]
} u327={[ ]
} u53={[ p350=1 ]
} i7={[ u333={[ ]
} u62={[ ]
} ]
} i5={[ u332={[ p353=1 ]
} u57={[ ]
} ]
} u48={[ ]
} u43={[ ]
} i3={[ u329={[ ]
} u52={[ ]
} ]
} i1={[ u328={[ ]
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} ]
} ]
[ u66={[ ]
} u64={[ ]
} u58={[ ]
} u327={[ ]
} u53={[ ]
} i7={[ u333={[ ]
} u62={[ ]
} ]
} i5={[ u332={[ ]
} u57={[ ]
} ]
} u48={[ p328=1 ]
} u43={[ ]
} i3={[ u329={[ p331=1 ]
} u52={[ ]
} ]
} i1={[ u328={[ ]
} u47={[ ]
} ]
} ]
[ u66={[ ]
} u64={[ ]
} u58={[ ]
} u327={[ ]
} u53={[ ]
} i7={[ u333={[ ]
} u62={[ ]
} ]
} i5={[ u332={[ ]
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} ]
} u48={[ ]
} u43={[ p294=1 ]
} i3={[ u329={[ ]
} u52={[ ]
} ]
} i1={[ u328={[ p297=1 ]
} u47={[ ]
} ]
} ]
} u73={[ p423=1 ]
} u322={[ p204=1 ]
} u35={[ p218=1 ]
} u41={[ p266=1 ]
} u3={[ p25=1 ]
} u5={[ p54=1 ]
} u2={[ p21=1 ]
} u4={[ p37=1 ]
} i6={[ u31={[ ]
} u29={[ ]
} u23={[ p176=1 ]
} u304={[ ]
} u18={[ ]
} i7={[ u320={[ p179=1 ]
} u27={[ ]
} ]
} i5={[ u315={[ ]
} u22={[ ]
} ]
} u13={[ ]
} u8={[ ]
} i3={[ u314={[ ]
} u17={[ ]
} ]
} i1={[ u306={[ ]
} u12={[ ]
} ]
} ]
[ u31={[ ]
} u29={[ ]
} u23={[ ]
} u304={[ ]
} u18={[ p156=1 ]
} i7={[ u320={[ ]
} u27={[ ]
} ]
} i5={[ u315={[ p159=1 ]
} u22={[ ]
} ]
} u13={[ ]
} u8={[ ]
} i3={[ u314={[ ]
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} ]
} i1={[ u306={[ ]
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} ]
} ]
[ u31={[ ]
} u29={[ ]
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} u18={[ ]
} i7={[ u320={[ ]
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} i5={[ u315={[ ]
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} ]
} u13={[ p134=1 ]
} u8={[ ]
} i3={[ u314={[ p137=1 ]
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} ]
} i1={[ u306={[ ]
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} ]
[ u31={[ ]
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} u18={[ ]
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} i5={[ u315={[ ]
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} ]
} u13={[ ]
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} i1={[ u306={[ p103=1 ]
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} ]
} ]
} u38={[ p228=1 ]
} u1={[ p2=1 ]
[ p18=1 ]
} u6={[ p72=1 ]
} ]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527829120876

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 01, 2018 4:57:03 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
Jun 01, 2018 4:57:03 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 01, 2018 4:57:03 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 287 ms
Jun 01, 2018 4:57:03 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 1601 places.
Jun 01, 2018 4:57:04 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 2373 transitions.
Jun 01, 2018 4:57:04 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
Jun 01, 2018 4:57:04 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 73 ms
Jun 01, 2018 4:57:04 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 618 ms
Jun 01, 2018 4:57:04 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 27 ms
Jun 01, 2018 4:57:05 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 2373 transitions.
Jun 01, 2018 4:57:08 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Jun 01, 2018 4:57:09 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1757 transitions.
Jun 01, 2018 4:57:09 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Too many transitions (1757) to apply POR reductions. Disabling POR matrices.
Jun 01, 2018 4:57:09 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 277 ms
Jun 01, 2018 4:57:09 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 410ms conformant to PINS in folder :/home/mcc/execution
Jun 01, 2018 4:57:09 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 277 ms
Jun 01, 2018 4:57:09 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Jun 01, 2018 4:57:09 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 198 ms
Jun 01, 2018 4:57:09 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
Jun 01, 2018 4:57:10 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 2446 redundant transitions.
Jun 01, 2018 4:57:10 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 22 ms

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ASLink-PT-07a"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/ASLink-PT-07a.tgz
mv ASLink-PT-07a execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is ASLink-PT-07a, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r273-smll-152749149600116"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;