Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.......................
/home/mcc/execution
total 764K
-rw-r--r-- 1 mcc users 3.5K May 29 16:53 CTLCardinality.txt
-rw-r--r-- 1 mcc users 20K May 29 16:53 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K May 28 11:14 CTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 28 11:14 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.6K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.3K May 28 09:23 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 28 09:23 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.8K May 28 07:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.3K May 28 07:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.7K May 27 05:08 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 19K May 27 05:08 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 104 May 26 06:29 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 342 May 26 06:29 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.2K May 26 06:34 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 12K May 26 06:34 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 28 07:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 28 07:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 4 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 597K May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is ASLink-PT-06a, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r273-smll-152749149500098
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ASLink-PT-06a-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1527807900555

Flatten gal took : 767 ms
Constant places removed 25 places and 1 transitions.
Reduce isomorphic transitions removed 22 transitions.
Implicit places reduction removed 12 places :[p1263, p1196, p1001, p989, p806, p794, p611, p599, p416, p404, p221, p209]
Performed 261 Post agglomeration using F-continuation condition.
Iterating post reduction 0 with 320 rules applied. Total rules applied 320 place count 1369 transition count 1816
Constant places removed 324 places and 0 transitions.
Performed 20 Post agglomeration using F-continuation condition.
Iterating post reduction 1 with 344 rules applied. Total rules applied 664 place count 1045 transition count 1796
Constant places removed 21 places and 0 transitions.
Implicit places reduction removed 7 places :[p1173, p978, p783, p588, p393, p206, p199]
Performed 7 Post agglomeration using F-continuation condition.
Iterating post reduction 2 with 35 rules applied. Total rules applied 699 place count 1017 transition count 1789
Constant places removed 7 places and 0 transitions.
Iterating post reduction 3 with 7 rules applied. Total rules applied 706 place count 1010 transition count 1789
Performed 24 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 4 with 24 Pre rules applied. Total rules applied 706 place count 1010 transition count 1765
Constant places removed 24 places and 0 transitions.
Iterating post reduction 4 with 24 rules applied. Total rules applied 730 place count 986 transition count 1765
Symmetric choice reduction at 5 with 15 rule applications. Total rules 745 place count 986 transition count 1765
Constant places removed 15 places and 53 transitions.
Reduce isomorphic transitions removed 2 transitions.
Implicit places reduction removed 9 places :[p1405, p1266, p1164, p969, p774, p579, p384, p190, p23]
Performed 10 Post agglomeration using F-continuation condition.
Iterating post reduction 5 with 36 rules applied. Total rules applied 781 place count 962 transition count 1700
Constant places removed 10 places and 0 transitions.
Iterating post reduction 6 with 10 rules applied. Total rules applied 791 place count 952 transition count 1700
Symmetric choice reduction at 7 with 7 rule applications. Total rules 798 place count 952 transition count 1700
Constant places removed 7 places and 14 transitions.
Iterating post reduction 7 with 7 rules applied. Total rules applied 805 place count 945 transition count 1686
Symmetric choice reduction at 8 with 1 rule applications. Total rules 806 place count 945 transition count 1686
Constant places removed 1 places and 8 transitions.
Iterating post reduction 8 with 1 rules applied. Total rules applied 807 place count 944 transition count 1678
Symmetric choice reduction at 9 with 1 rule applications. Total rules 808 place count 944 transition count 1678
Constant places removed 1 places and 8 transitions.
Iterating post reduction 9 with 1 rules applied. Total rules applied 809 place count 943 transition count 1670
Symmetric choice reduction at 10 with 1 rule applications. Total rules 810 place count 943 transition count 1670
Constant places removed 1 places and 8 transitions.
Iterating post reduction 10 with 1 rules applied. Total rules applied 811 place count 942 transition count 1662
Symmetric choice reduction at 11 with 1 rule applications. Total rules 812 place count 942 transition count 1662
Constant places removed 1 places and 8 transitions.
Iterating post reduction 11 with 1 rules applied. Total rules applied 813 place count 941 transition count 1654
Symmetric choice reduction at 12 with 1 rule applications. Total rules 814 place count 941 transition count 1654
Constant places removed 1 places and 8 transitions.
Iterating post reduction 12 with 1 rules applied. Total rules applied 815 place count 940 transition count 1646
Symmetric choice reduction at 13 with 1 rule applications. Total rules 816 place count 940 transition count 1646
Constant places removed 1 places and 8 transitions.
Iterating post reduction 13 with 1 rules applied. Total rules applied 817 place count 939 transition count 1638
Symmetric choice reduction at 14 with 1 rule applications. Total rules 818 place count 939 transition count 1638
Constant places removed 1 places and 8 transitions.
Iterating post reduction 14 with 1 rules applied. Total rules applied 819 place count 938 transition count 1630
Symmetric choice reduction at 15 with 1 rule applications. Total rules 820 place count 938 transition count 1630
Constant places removed 1 places and 8 transitions.
Iterating post reduction 15 with 1 rules applied. Total rules applied 821 place count 937 transition count 1622
Symmetric choice reduction at 16 with 1 rule applications. Total rules 822 place count 937 transition count 1622
Constant places removed 1 places and 8 transitions.
Iterating post reduction 16 with 1 rules applied. Total rules applied 823 place count 936 transition count 1614
Symmetric choice reduction at 17 with 1 rule applications. Total rules 824 place count 936 transition count 1614
Constant places removed 1 places and 8 transitions.
Iterating post reduction 17 with 1 rules applied. Total rules applied 825 place count 935 transition count 1606
Symmetric choice reduction at 18 with 1 rule applications. Total rules 826 place count 935 transition count 1606
Constant places removed 1 places and 8 transitions.
Iterating post reduction 18 with 1 rules applied. Total rules applied 827 place count 934 transition count 1598
Symmetric choice reduction at 19 with 1 rule applications. Total rules 828 place count 934 transition count 1598
Constant places removed 1 places and 8 transitions.
Iterating post reduction 19 with 1 rules applied. Total rules applied 829 place count 933 transition count 1590
Symmetric choice reduction at 20 with 1 rule applications. Total rules 830 place count 933 transition count 1590
Constant places removed 1 places and 8 transitions.
Iterating post reduction 20 with 1 rules applied. Total rules applied 831 place count 932 transition count 1582
Symmetric choice reduction at 21 with 1 rule applications. Total rules 832 place count 932 transition count 1582
Constant places removed 1 places and 8 transitions.
Iterating post reduction 21 with 1 rules applied. Total rules applied 833 place count 931 transition count 1574
Symmetric choice reduction at 22 with 1 rule applications. Total rules 834 place count 931 transition count 1574
Constant places removed 1 places and 8 transitions.
Iterating post reduction 22 with 1 rules applied. Total rules applied 835 place count 930 transition count 1566
Performed 19 Post agglomeration using F-continuation condition.
Constant places removed 19 places and 0 transitions.
Iterating post reduction 23 with 19 rules applied. Total rules applied 854 place count 911 transition count 1547
Applied a total of 854 rules in 1370 ms. Remains 911 /1406 variables (removed 495) and now considering 1547/2100 (removed 553) transitions.
// Phase 1: matrix 1547 rows 911 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
built 74 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 8 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 100 ordering constraints for composite.
Compilation finished in 21700 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 58 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -d], workingDir=/home/mcc/execution]
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,5.14955e+23,26.511,602084,4879,586,1.16125e+06,1682,2668,1.52068e+06,150,11253,0


Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,1.10449e+16,27.1335,602084,1103,243,1.16125e+06,6326,8028,1.52068e+06,767,17313,141438

System contains 1.10449e+16 deadlocks (shown below if less than --print-limit option) !
FORMULA ASLink-PT-06a-ReachabilityDeadlock-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
[ 11044872394605661 states ] showing 10 first states
[ u217={[ p1267=1 ]
} u215={[ p1239=1 ]
} i49={[ u254={[ p1398=1 ]
} u253={[ p1394=1 ]
} u252={[ ]
} u251={[ ]
} u247={[ ]
} u246={[ ]
} u245={[ ]
} u244={[ ]
} u243={[ ]
} u241={[ ]
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} u239={[ ]
} u280={[ ]
} u238={[ ]
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} u232={[ ]
} u233={[ ]
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} u220={[ ]
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} u227={[ ]
} u226={[ ]
} u222={[ ]
} u225={[ ]
} u221={[ ]
} u224={[ ]
} u223={[ ]
} ]
[ u254={[ ]
} u253={[ ]
} u252={[ p1392=1 ]
} u251={[ p1387=1 ]
} u247={[ ]
} u246={[ ]
} u245={[ ]
} u244={[ ]
} u243={[ ]
} u241={[ ]
} u242={[ ]
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} u280={[ ]
} u238={[ ]
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} u236={[ ]
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} u226={[ ]
} u222={[ ]
} u225={[ ]
} u221={[ ]
} u224={[ ]
} u223={[ ]
} ]
[ u254={[ ]
} u253={[ ]
} u252={[ ]
} u251={[ ]
} u247={[ p1379=1 ]
} u246={[ p1375=1 ]
} u245={[ ]
} u244={[ ]
} u243={[ ]
} u241={[ ]
} u242={[ ]
} u240={[ ]
} u239={[ ]
} u280={[ ]
} u238={[ ]
} u237={[ ]
} u236={[ ]
} u235={[ ]
} u234={[ ]
} u232={[ ]
} u233={[ ]
} u231={[ ]
} u230={[ ]
} u229={[ ]
} u220={[ ]
} u219={[ ]
} u228={[ ]
} u227={[ ]
} u226={[ ]
} u222={[ ]
} u225={[ ]
} u221={[ ]
} u224={[ ]
} u223={[ ]
} ]
[ u254={[ ]
} u253={[ ]
} u252={[ ]
} u251={[ ]
} u247={[ ]
} u246={[ ]
} u245={[ p1373=1 ]
} u244={[ p1369=1 ]
} u243={[ ]
} u241={[ ]
} u242={[ ]
} u240={[ ]
} u239={[ ]
} u280={[ ]
} u238={[ ]
} u237={[ ]
} u236={[ ]
} u235={[ ]
} u234={[ ]
} u232={[ ]
} u233={[ ]
} u231={[ ]
} u230={[ ]
} u229={[ ]
} u220={[ ]
} u219={[ ]
} u228={[ ]
} u227={[ ]
} u226={[ ]
} u222={[ ]
} u225={[ ]
} u221={[ ]
} u224={[ ]
} u223={[ ]
} ]
[ u254={[ ]
} u253={[ ]
} u252={[ ]
} u251={[ ]
} u247={[ ]
} u246={[ ]
} u245={[ ]
} u244={[ ]
} u243={[ p1367=1 ]
} u241={[ p1360=1 ]
} u242={[ p1363=1 ]
} u240={[ ]
} u239={[ ]
} u280={[ ]
} u238={[ ]
} u237={[ ]
} u236={[ ]
} u235={[ ]
} u234={[ ]
} u232={[ ]
} u233={[ ]
} u231={[ ]
} u230={[ ]
} u229={[ ]
} u220={[ ]
} u219={[ ]
} u228={[ ]
} u227={[ ]
} u226={[ ]
} u222={[ ]
} u225={[ ]
} u221={[ ]
} u224={[ ]
} u223={[ ]
} ]
} u214={[ p1221=1 ]
} u216={[ p1264=1 ]
} u179={[ p1011=1 ]
} u210={[ p1191=1 ]
} u180={[ p1030=1 ]
[ p1032=1 ]
[ p1034=1 ]
[ p1036=1 ]
[ p1038=1 ]
[ p1040=1 ]
[ p1042=1 ]
[ p1044=1 ]
} i41={[ u206={[ ]
} u204={[ ]
} u198={[ ]
} u270={[ ]
} u193={[ ]
} i7={[ u266={[ ]
} u202={[ ]
} ]
} i5={[ u265={[ ]
} u197={[ ]
} ]
} u188={[ p1099=1 ]
[ p1101=1 ]
[ p1103=1 ]
[ p1105=1 ]
} u183={[ ]
} i3={[ u272={[ p1111=1 ]
} u192={[ ]
} ]
} i1={[ u273={[ ]
} u187={[ ]
} ]
} ]
[ u206={[ ]
} u204={[ ]
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} u270={[ ]
} u193={[ p1125=1 ]
[ p1127=1 ]
} i7={[ u266={[ ]
} u202={[ ]
} ]
} i5={[ u265={[ p1133=1 ]
} u197={[ ]
} ]
} u188={[ ]
} u183={[ ]
} i3={[ u272={[ ]
} u192={[ ]
} ]
} i1={[ u273={[ ]
} u187={[ ]
} ]
} ]
[ u206={[ ]
} u204={[ ]
} u198={[ p1147=1 ]
} u270={[ ]
} u193={[ ]
} i7={[ u266={[ p1153=1 ]
} u202={[ ]
} ]
} i5={[ u265={[ ]
} u197={[ ]
} ]
} u188={[ ]
} u183={[ ]
} i3={[ u272={[ ]
} u192={[ ]
} ]
} i1={[ u273={[ ]
} u187={[ ]
} ]
} ]
} u213={[ p1203=1 ]
} u181={[ p1046=1 ]
} u144={[ p816=1 ]
} i42={[ u274={[ ]
} u209={[ p1182=1 ]
} u208={[ p1179=1 ]
} ]
} u145={[ p833=1 ]
} u175={[ p992=1 ]
} i34={[ u171={[ ]
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} u163={[ p956=1 ]
} u293={[ ]
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} i7={[ u261={[ p958=1 ]
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} ]
} i5={[ u263={[ ]
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} ]
} u153={[ ]
} u148={[ ]
} i3={[ u289={[ ]
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} ]
} i1={[ u290={[ ]
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} ]
} ]
[ u171={[ ]
} u169={[ ]
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} u293={[ ]
} u158={[ p936=1 ]
} i7={[ u261={[ ]
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} ]
} i5={[ u263={[ p938=1 ]
} u162={[ ]
} ]
} u153={[ ]
} u148={[ ]
} i3={[ u289={[ ]
} u157={[ ]
} ]
} i1={[ u290={[ ]
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} ]
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[ u171={[ ]
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} u158={[ ]
} i7={[ u261={[ ]
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} ]
} i5={[ u263={[ ]
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} ]
} u153={[ p914=1 ]
} u148={[ ]
} i3={[ u289={[ p916=1 ]
} u157={[ ]
} ]
} i1={[ u290={[ ]
} u152={[ ]
} ]
} ]
[ u171={[ ]
} u169={[ ]
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} u293={[ ]
} u158={[ ]
} i7={[ u261={[ ]
} u167={[ ]
} ]
} i5={[ u263={[ ]
} u162={[ ]
} ]
} u153={[ ]
} u148={[ p880=1 ]
} i3={[ u289={[ ]
} u157={[ ]
} ]
} i1={[ u290={[ p882=1 ]
} u152={[ ]
} ]
} ]
} u178={[ p1008=1 ]
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} i35={[ u258={[ ]
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} u173={[ p984=1 ]
} ]
} u109={[ p621=1 ]
} u110={[ p638=1 ]
} u140={[ p797=1 ]
} i27={[ u136={[ ]
} u134={[ ]
} u128={[ p761=1 ]
} u275={[ ]
} u123={[ ]
} i7={[ u283={[ p763=1 ]
} u132={[ ]
} ]
} i5={[ u284={[ ]
} u127={[ ]
} ]
} u118={[ ]
} u113={[ ]
} i3={[ u285={[ ]
} u122={[ ]
} ]
} i1={[ u276={[ ]
} u117={[ ]
} ]
} ]
[ u136={[ ]
} u134={[ ]
} u128={[ ]
} u275={[ ]
} u123={[ p741=1 ]
} i7={[ u283={[ ]
} u132={[ ]
} ]
} i5={[ u284={[ p743=1 ]
} u127={[ ]
} ]
} u118={[ ]
} u113={[ ]
} i3={[ u285={[ ]
} u122={[ ]
} ]
} i1={[ u276={[ ]
} u117={[ ]
} ]
} ]
[ u136={[ ]
} u134={[ ]
} u128={[ ]
} u275={[ ]
} u123={[ ]
} i7={[ u283={[ ]
} u132={[ ]
} ]
} i5={[ u284={[ ]
} u127={[ ]
} ]
} u118={[ p719=1 ]
} u113={[ ]
} i3={[ u285={[ p721=1 ]
} u122={[ ]
} ]
} i1={[ u276={[ ]
} u117={[ ]
} ]
} ]
[ u136={[ ]
} u134={[ ]
} u128={[ ]
} u275={[ ]
} u123={[ ]
} i7={[ u283={[ ]
} u132={[ ]
} ]
} i5={[ u284={[ ]
} u127={[ ]
} ]
} u118={[ ]
} u113={[ p685=1 ]
} i3={[ u285={[ ]
} u122={[ ]
} ]
} i1={[ u276={[ p687=1 ]
} u117={[ ]
} ]
} ]
} u143={[ p813=1 ]
} u111={[ p656=1 ]
} i28={[ u294={[ ]
} u139={[ ]
} u138={[ p789=1 ]
} ]
} u74={[ p426=1 ]
} u75={[ p443=1 ]
} u105={[ p602=1 ]
} i20={[ u101={[ ]
} u99={[ ]
} u93={[ p566=1 ]
} u259={[ ]
} u88={[ ]
} i7={[ u267={[ p568=1 ]
} u97={[ ]
} ]
} i5={[ u264={[ ]
} u92={[ ]
} ]
} u83={[ ]
} u78={[ ]
} i3={[ u262={[ ]
} u87={[ ]
} ]
} i1={[ u260={[ ]
} u82={[ ]
} ]
} ]
[ u101={[ ]
} u99={[ ]
} u93={[ ]
} u259={[ ]
} u88={[ p546=1 ]
} i7={[ u267={[ ]
} u97={[ ]
} ]
} i5={[ u264={[ p548=1 ]
} u92={[ ]
} ]
} u83={[ ]
} u78={[ ]
} i3={[ u262={[ ]
} u87={[ ]
} ]
} i1={[ u260={[ ]
} u82={[ ]
} ]
} ]
[ u101={[ ]
} u99={[ ]
} u93={[ ]
} u259={[ ]
} u88={[ ]
} i7={[ u267={[ ]
} u97={[ ]
} ]
} i5={[ u264={[ ]
} u92={[ ]
} ]
} u83={[ p524=1 ]
} u78={[ ]
} i3={[ u262={[ p526=1 ]
} u87={[ ]
} ]
} i1={[ u260={[ ]
} u82={[ ]
} ]
} ]
[ u101={[ ]
} u99={[ ]
} u93={[ ]
} u259={[ ]
} u88={[ ]
} i7={[ u267={[ ]
} u97={[ ]
} ]
} i5={[ u264={[ ]
} u92={[ ]
} ]
} u83={[ ]
} u78={[ p490=1 ]
} i3={[ u262={[ ]
} u87={[ ]
} ]
} i1={[ u260={[ p492=1 ]
} u82={[ ]
} ]
} ]
} u108={[ p618=1 ]
} u76={[ p461=1 ]
} i21={[ u279={[ ]
} u104={[ ]
} u103={[ p594=1 ]
} ]
} u39={[ p231=1 ]
} u70={[ p407=1 ]
} u40={[ p248=1 ]
} i14={[ u295={[ ]
} u69={[ ]
} u68={[ p399=1 ]
} ]
} i13={[ u66={[ ]
} u64={[ ]
} u58={[ p371=1 ]
} u286={[ ]
} u53={[ ]
} i7={[ u292={[ p373=1 ]
} u62={[ ]
} ]
} i5={[ u291={[ ]
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} ]
} u48={[ ]
} u43={[ ]
} i3={[ u288={[ ]
} u52={[ ]
} ]
} i1={[ u287={[ ]
} u47={[ ]
} ]
} ]
[ u66={[ ]
} u64={[ ]
} u58={[ ]
} u286={[ ]
} u53={[ p351=1 ]
} i7={[ u292={[ ]
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} ]
} i5={[ u291={[ p353=1 ]
} u57={[ ]
} ]
} u48={[ ]
} u43={[ ]
} i3={[ u288={[ ]
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} ]
} i1={[ u287={[ ]
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} ]
[ u66={[ ]
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} u53={[ ]
} i7={[ u292={[ ]
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} ]
} i5={[ u291={[ ]
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} ]
} u48={[ p329=1 ]
} u43={[ ]
} i3={[ u288={[ p331=1 ]
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} i1={[ u287={[ ]
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} ]
[ u66={[ ]
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} i5={[ u291={[ ]
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} u48={[ ]
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} i3={[ u288={[ ]
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} i1={[ u287={[ p297=1 ]
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} ]
} u73={[ p423=1 ]
} u282={[ p204=1 ]
} u35={[ p218=1 ]
} u41={[ p266=1 ]
} u3={[ p22=1 ]
[ p31=1 ]
} u5={[ p54=1 ]
} u2={[ p21=1 ]
} u4={[ p37=1 ]
} i6={[ u31={[ ]
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} u18={[ p156=1 ]
} i7={[ u281={[ ]
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} i5={[ u278={[ p159=1 ]
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} u13={[ ]
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} i3={[ u277={[ ]
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} i1={[ u271={[ ]
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} ]
} ]
[ u31={[ ]
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} u18={[ ]
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} ]
} i5={[ u278={[ ]
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} u13={[ ]
} u8={[ p100=1 ]
} i3={[ u277={[ ]
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} i1={[ u271={[ p103=1 ]
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} ]
[ u31={[ ]
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} i5={[ u278={[ ]
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} i1={[ u271={[ ]
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} ]
[ u31={[ ]
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} i5={[ u278={[ ]
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} ]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527807937668

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 31, 2018 11:05:03 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 31, 2018 11:05:03 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 31, 2018 11:05:03 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 370 ms
May 31, 2018 11:05:03 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 1406 places.
May 31, 2018 11:05:03 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 2100 transitions.
May 31, 2018 11:05:03 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 31, 2018 11:05:04 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 72 ms
May 31, 2018 11:05:04 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 760 ms
May 31, 2018 11:05:04 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 25 ms
May 31, 2018 11:05:05 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 2100 transitions.
May 31, 2018 11:05:07 PM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 31, 2018 11:05:08 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1547 transitions.
May 31, 2018 11:05:08 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Too many transitions (1547) to apply POR reductions. Disabling POR matrices.
May 31, 2018 11:05:08 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 287 ms
May 31, 2018 11:05:08 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 310ms conformant to PINS in folder :/home/mcc/execution
May 31, 2018 11:05:08 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 304 ms
May 31, 2018 11:05:08 PM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 31, 2018 11:05:08 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 187 ms
May 31, 2018 11:05:08 PM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 31, 2018 11:05:09 PM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 2152 redundant transitions.
May 31, 2018 11:05:09 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 19 ms

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ASLink-PT-06a"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/ASLink-PT-06a.tgz
mv ASLink-PT-06a execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is ASLink-PT-06a, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r273-smll-152749149500098"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;