Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
....................
/home/mcc/execution
total 364K
-rw-r--r-- 1 mcc users 3.3K May 29 16:52 CTLCardinality.txt
-rw-r--r-- 1 mcc users 19K May 29 16:52 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K May 28 11:13 CTLFireability.txt
-rw-r--r-- 1 mcc users 16K May 28 11:13 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.6K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.5K May 28 09:20 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 28 09:20 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.7K May 28 07:35 LTLFireability.txt
-rw-r--r-- 1 mcc users 7.7K May 28 07:35 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.5K May 27 05:07 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 19K May 27 05:07 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 104 May 26 06:29 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 342 May 26 06:29 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.5K May 26 06:33 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 15K May 26 06:33 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 28 07:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 28 07:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 4 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 201K May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is ASLink-PT-01a, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r273-smll-152749149400008
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ASLink-PT-01a-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1527751972940

Flatten gal took : 243 ms
Constant places removed 5 places and 1 transitions.
Reduce isomorphic transitions removed 7 transitions.
Implicit places reduction removed 2 places :[p288, p221]
Performed 61 Post agglomeration using F-continuation condition.
Iterating post reduction 0 with 75 rules applied. Total rules applied 75 place count 424 transition count 666
Constant places removed 74 places and 0 transitions.
Performed 5 Post agglomeration using F-continuation condition.
Iterating post reduction 1 with 79 rules applied. Total rules applied 154 place count 350 transition count 661
Constant places removed 6 places and 0 transitions.
Implicit places reduction removed 2 places :[p206, p199]
Performed 2 Post agglomeration using F-continuation condition.
Iterating post reduction 2 with 10 rules applied. Total rules applied 164 place count 342 transition count 659
Constant places removed 2 places and 0 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 166 place count 340 transition count 659
Performed 4 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 4 with 4 Pre rules applied. Total rules applied 166 place count 340 transition count 655
Constant places removed 4 places and 0 transitions.
Iterating post reduction 4 with 4 rules applied. Total rules applied 170 place count 336 transition count 655
Symmetric choice reduction at 5 with 5 rule applications. Total rules 175 place count 336 transition count 655
Constant places removed 5 places and 18 transitions.
Reduce isomorphic transitions removed 2 transitions.
Implicit places reduction removed 4 places :[p430, p291, p190, p23]
Performed 5 Post agglomeration using F-continuation condition.
Iterating post reduction 5 with 16 rules applied. Total rules applied 191 place count 327 transition count 630
Constant places removed 5 places and 0 transitions.
Iterating post reduction 6 with 5 rules applied. Total rules applied 196 place count 322 transition count 630
Symmetric choice reduction at 7 with 2 rule applications. Total rules 198 place count 322 transition count 630
Constant places removed 2 places and 9 transitions.
Iterating post reduction 7 with 2 rules applied. Total rules applied 200 place count 320 transition count 621
Symmetric choice reduction at 8 with 1 rule applications. Total rules 201 place count 320 transition count 621
Constant places removed 1 places and 8 transitions.
Iterating post reduction 8 with 1 rules applied. Total rules applied 202 place count 319 transition count 613
Symmetric choice reduction at 9 with 1 rule applications. Total rules 203 place count 319 transition count 613
Constant places removed 1 places and 8 transitions.
Iterating post reduction 9 with 1 rules applied. Total rules applied 204 place count 318 transition count 605
Symmetric choice reduction at 10 with 1 rule applications. Total rules 205 place count 318 transition count 605
Constant places removed 1 places and 8 transitions.
Iterating post reduction 10 with 1 rules applied. Total rules applied 206 place count 317 transition count 597
Symmetric choice reduction at 11 with 1 rule applications. Total rules 207 place count 317 transition count 597
Constant places removed 1 places and 8 transitions.
Iterating post reduction 11 with 1 rules applied. Total rules applied 208 place count 316 transition count 589
Symmetric choice reduction at 12 with 1 rule applications. Total rules 209 place count 316 transition count 589
Constant places removed 1 places and 8 transitions.
Iterating post reduction 12 with 1 rules applied. Total rules applied 210 place count 315 transition count 581
Symmetric choice reduction at 13 with 1 rule applications. Total rules 211 place count 315 transition count 581
Constant places removed 1 places and 8 transitions.
Iterating post reduction 13 with 1 rules applied. Total rules applied 212 place count 314 transition count 573
Symmetric choice reduction at 14 with 1 rule applications. Total rules 213 place count 314 transition count 573
Constant places removed 1 places and 8 transitions.
Iterating post reduction 14 with 1 rules applied. Total rules applied 214 place count 313 transition count 565
Symmetric choice reduction at 15 with 1 rule applications. Total rules 215 place count 313 transition count 565
Constant places removed 1 places and 8 transitions.
Iterating post reduction 15 with 1 rules applied. Total rules applied 216 place count 312 transition count 557
Symmetric choice reduction at 16 with 1 rule applications. Total rules 217 place count 312 transition count 557
Constant places removed 1 places and 8 transitions.
Iterating post reduction 16 with 1 rules applied. Total rules applied 218 place count 311 transition count 549
Symmetric choice reduction at 17 with 1 rule applications. Total rules 219 place count 311 transition count 549
Constant places removed 1 places and 8 transitions.
Iterating post reduction 17 with 1 rules applied. Total rules applied 220 place count 310 transition count 541
Symmetric choice reduction at 18 with 1 rule applications. Total rules 221 place count 310 transition count 541
Constant places removed 1 places and 8 transitions.
Iterating post reduction 18 with 1 rules applied. Total rules applied 222 place count 309 transition count 533
Symmetric choice reduction at 19 with 1 rule applications. Total rules 223 place count 309 transition count 533
Constant places removed 1 places and 8 transitions.
Iterating post reduction 19 with 1 rules applied. Total rules applied 224 place count 308 transition count 525
Symmetric choice reduction at 20 with 1 rule applications. Total rules 225 place count 308 transition count 525
Constant places removed 1 places and 8 transitions.
Iterating post reduction 20 with 1 rules applied. Total rules applied 226 place count 307 transition count 517
Symmetric choice reduction at 21 with 1 rule applications. Total rules 227 place count 307 transition count 517
Constant places removed 1 places and 8 transitions.
Iterating post reduction 21 with 1 rules applied. Total rules applied 228 place count 306 transition count 509
Symmetric choice reduction at 22 with 1 rule applications. Total rules 229 place count 306 transition count 509
Constant places removed 1 places and 8 transitions.
Iterating post reduction 22 with 1 rules applied. Total rules applied 230 place count 305 transition count 501
Performed 4 Post agglomeration using F-continuation condition.
Constant places removed 4 places and 0 transitions.
Iterating post reduction 23 with 4 rules applied. Total rules applied 234 place count 301 transition count 497
Applied a total of 234 rules in 461 ms. Remains 301 /431 variables (removed 130) and now considering 497/735 (removed 238) transitions.
// Phase 1: matrix 497 rows 301 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
built 19 ordering constraints for composite.
built 2 ordering constraints for composite.
built 58 ordering constraints for composite.
built 12 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 4 ordering constraints for composite.
built 100 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 497 rows 301 cols
invariant :p38 + p40 + p42 + p44 + p46 + p48 + p50 + p52 + p230 + p232 + p234 + p236 + p238 + p240 + p242 + p244 + p246 + -1'p294 + -1'p296 + -1'p298 + -1'p300 + -1'p392 + -1'p398 + -1'p404 + -1'p417 + -1'p423 = 0
invariant :p98 + p100 + p101 + -1'p102 + -1'p103 + -1'p104 + -1'p105 + -1'p106 + -1'p107 + -1'p108 + -1'p109 + -1'p110 + -1'p111 + p145 + p167 + p187 + p228 = 1
invariant :p20 + p22 + p25 + p29 + p30 + p31 + p32 + p34 + p209 = 1
invariant :p119 + p145 + p167 + p187 + p228 = 1
invariant :-1'p209 + p211 + p212 + p213 = 0
invariant :p149 + p151 + p152 + p153 + p154 + p156 + p157 + -1'p158 + -1'p159 + -1'p167 = 0
invariant :p332 + p333 + p334 + -1'p335 + -1'p336 + -1'p337 = 0
invariant :p56 + p58 + p60 + p62 + p64 + p66 + p68 + p70 + p100 + p134 + p156 + p176 + p209 + p210 = 1
invariant :p265 + p268 + -1'p311 + p316 + -1'p319 + p324 + -1'p327 + p330 + -1'p333 + p336 + -1'p339 + p342 + p344 + p346 + -1'p347 + -1'p349 + -1'p351 + p356 + -1'p359 + p362 + p364 + p366 + -1'p367 + -1'p369 + -1'p371 + p376 + p378 + p380 + -1'p381 + -1'p383 = 0
invariant :-1'p38 + -1'p40 + -1'p42 + -1'p44 + -1'p46 + -1'p48 + -1'p50 + -1'p52 + p231 + p233 + p235 + p237 + p239 + p241 + p243 + p245 = 0
invariant :p326 + p327 + p328 + -1'p329 + -1'p330 + -1'p331 = 0
invariant :p364 + p365 + p366 + -1'p367 + -1'p368 + -1'p369 = 0
invariant :p384 + p385 + -1'p390 + -1'p391 + -1'p392 = 0
invariant :p1 + -1'p27 + -1'p30 + -1'p32 + -1'p34 = 0
invariant :p2 + p4 + p6 + p8 + p10 + p12 + p14 + p16 + p18 + p27 + p30 + p32 + p34 + p74 + p76 + p78 + p80 + p82 + p84 + p86 + p88 = 1
invariant :p22 + p25 + p26 + p27 + p28 + p29 + p30 + p31 + p32 + p34 + p209 = 1
invariant :p209 + p210 + -1'p212 + p214 + p216 + p217 + p219 + -1'p268 + -1'p270 + -1'p272 + -1'p274 + -1'p276 + -1'p278 + -1'p280 + -1'p282 + -1'p284 + -1'p286 + p317 + -1'p320 + p325 + -1'p328 + p331 + -1'p334 + p337 + -1'p340 + p343 + p349 + -1'p352 + p357 + -1'p360 + p363 + p369 + -1'p372 + p377 + p383 = 1
invariant :p264 + p317 + p325 + p331 + p337 + p343 + p349 + p357 + p363 + p369 + p377 + p383 = 1
invariant :p370 + p371 + p372 + -1'p375 + -1'p376 + -1'p377 = 0
invariant :p269 + -1'p320 + -1'p328 + -1'p334 + -1'p340 + -1'p352 + -1'p360 + -1'p372 = 0
invariant :p289 + p389 + p395 + p401 + p420 = 1
invariant :p3 + p5 + p7 + p9 + p11 + p13 + p15 + p17 + -1'p74 + -1'p76 + -1'p78 + -1'p80 + -1'p82 + -1'p84 + -1'p86 + -1'p88 = 0
invariant :p56 + p58 + p60 + p62 + p64 + p66 + p68 + p70 + p209 + p210 + p217 + p218 + p219 = 1
invariant :p91 + p92 + p93 + p96 + p102 + p103 + p104 + p105 + p106 + p107 + p108 + p109 + p110 + p111 + p136 + p137 + p158 + p159 + p178 + p179 + p193 + p197 + p203 + -1'p228 = 0
invariant :p227 + p228 = 1
invariant :p338 + p339 + p340 + -1'p341 + -1'p342 + -1'p343 = 0
invariant :p21 + -1'p22 + -1'p25 + -1'p29 + -1'p30 + -1'p31 + -1'p32 + -1'p34 + -1'p209 = 0
invariant :p387 + p388 + p389 + -1'p390 + -1'p391 + -1'p392 = 0
invariant :p72 + p92 = 1
invariant :p35 + p96 + p102 + p103 + p104 + p106 + p108 + p110 + p136 + p137 + p158 + p159 + p178 + p179 + p193 + -1'p228 = 0
invariant :p310 + p311 + p312 + -1'p315 + -1'p316 + -1'p317 = 0
invariant :p229 + p294 + p296 + p298 + p300 + p392 + p398 + p404 + p417 + p423 = 1
invariant :p266 + -1'p312 + -1'p346 + -1'p366 + -1'p380 = 0
invariant :p393 + p394 + p395 + -1'p396 + -1'p397 + -1'p398 = 0
invariant :p73 + p74 + p75 + p76 + p77 + p78 + p79 + p80 + p81 + p82 + p83 + p84 + p85 + p86 + p87 + p88 + p89 + -1'p92 = 0
invariant :p350 + p351 + p352 + -1'p355 + -1'p356 + -1'p357 = 0
invariant :p54 + p125 + p127 + p129 + p131 + p151 + p153 + p173 = 1
invariant :p292 + p294 + p295 + p296 + p297 + p298 + p299 + p300 + p301 = 1
invariant :p204 + p209 = 1
invariant :p344 + p345 + p346 + -1'p347 + -1'p348 + -1'p349 = 0
invariant :p55 + p56 + p57 + p58 + p59 + p60 + p61 + p62 + p63 + p64 + p65 + p66 + p67 + p68 + p69 + p70 + p71 + -1'p125 + -1'p127 + -1'p129 + -1'p131 + -1'p151 + -1'p153 + -1'p173 = 0
invariant :-1'p56 + -1'p58 + -1'p60 + -1'p62 + -1'p64 + -1'p66 + -1'p68 + -1'p70 + -1'p209 + -1'p210 + p212 + p215 + -1'p217 + -1'p219 + p268 + p270 + p272 + p274 + p276 + p278 + p280 + p282 + p284 + p286 + -1'p317 + p320 + -1'p325 + p328 + -1'p331 + p334 + -1'p337 + p340 + -1'p343 + -1'p349 + p352 + -1'p357 + p360 + -1'p363 + -1'p369 + p372 + -1'p377 + -1'p383 = -1
invariant :p399 + p400 + p401 + -1'p402 + -1'p403 + -1'p404 = 0
invariant :-1'p56 + -1'p58 + -1'p60 + -1'p62 + -1'p64 + -1'p66 + -1'p68 + -1'p70 + -1'p100 + p123 + p125 + p126 + p127 + p128 + p129 + p130 + p131 + p132 + p135 + -1'p136 + -1'p137 + -1'p145 + -1'p156 + -1'p176 + -1'p209 + -1'p210 = -1
invariant :p378 + p379 + p380 + -1'p381 + -1'p382 + -1'p383 = 0
invariant :p358 + p359 + p360 + -1'p361 + -1'p362 + -1'p363 = 0
invariant :p318 + p319 + p320 + -1'p323 + -1'p324 + -1'p325 = 0
invariant :p171 + p173 + p174 + p176 + p177 + -1'p178 + -1'p179 + -1'p187 = 0
invariant :p37 + p38 + p39 + p40 + p41 + p42 + p43 + p44 + p45 + p46 + p47 + p48 + p49 + p50 + p51 + p52 + p53 + -1'p96 + -1'p102 + -1'p103 + -1'p104 + -1'p106 + -1'p108 + -1'p110 + -1'p136 + -1'p137 + -1'p158 + -1'p159 + -1'p178 + -1'p179 + -1'p193 + p228 = 1
invariant :p287 + -1'p389 + -1'p395 + -1'p401 + -1'p420 = 0
invariant :p418 + p419 + p420 + -1'p421 + -1'p422 + -1'p423 = 0
invariant :p294 + p295 + p296 + p297 + p298 + p299 + p300 + p301 + p309 + p315 + p316 + p317 + p323 + p324 + p325 + p329 + p330 + p331 + p335 + p336 + p337 + p341 + p342 + p343 + p347 + p348 + p349 + p355 + p356 + p357 + p361 + p362 + p363 + p367 + p368 + p369 + p375 + p376 + p377 + p381 + p382 + p383 + p390 + p391 + p392 + p396 + p397 + p398 + p402 + p403 + p404 + p415 + p416 + p417 + p421 + p422 + p423 = 1
invariant :p411 + p412 + -1'p415 + -1'p416 + -1'p417 = 0
invariant :p267 + p270 + p271 + p272 + p273 + p274 + p275 + p276 + p277 + p278 + p279 + p280 + p281 + p282 + p283 + p284 + p285 + p286 + p311 + p312 + -1'p316 + -1'p317 + p319 + p320 + -1'p324 + -1'p325 + p327 + p328 + -1'p330 + -1'p331 + p333 + p334 + -1'p336 + -1'p337 + p339 + p340 + -1'p342 + -1'p343 + -1'p344 + p347 + p351 + p352 + -1'p356 + -1'p357 + p359 + p360 + -1'p362 + -1'p363 + -1'p364 + p367 + p371 + p372 + -1'p376 + -1'p377 + -1'p378 + p381 = 0
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,7.63654e+06,1.57394,56036,2563,553,92829,1951,1045,169294,144,15063,0


Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,10842,1.74099,56036,510,243,92829,4549,3232,169294,632,15063,43609

System contains 10842 deadlocks (shown below if less than --print-limit option) !
FORMULA ASLink-PT-01a-ReachabilityDeadlock-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
[ 10842 states ] showing 10 first states
[ u42={[ p292=1 ]
} u41={[ p289=1 ]
} i14={[ u79={[ ]
} u78={[ ]
} u77={[ ]
} u76={[ ]
} u72={[ ]
} u71={[ ]
} u70={[ ]
} u69={[ ]
} u68={[ ]
} u66={[ ]
} u67={[ ]
} u65={[ ]
} u64={[ ]
} u84={[ ]
} u63={[ ]
} u62={[ ]
} u61={[ ]
} u60={[ ]
} u59={[ ]
} u57={[ ]
} u58={[ ]
} u56={[ ]
} u55={[ ]
} u54={[ ]
} u45={[ ]
} u44={[ ]
} u53={[ p343=1 ]
} u52={[ p338=1 ]
} u51={[ ]
} u47={[ ]
} u50={[ ]
} u46={[ ]
} u49={[ ]
} u48={[ ]
} ]
[ u79={[ ]
} u78={[ ]
} u77={[ ]
} u76={[ ]
} u72={[ ]
} u71={[ ]
} u70={[ ]
} u69={[ ]
} u68={[ ]
} u66={[ ]
} u67={[ ]
} u65={[ ]
} u64={[ ]
} u84={[ ]
} u63={[ ]
} u62={[ ]
} u61={[ ]
} u60={[ ]
} u59={[ p363=1 ]
} u57={[ ]
} u58={[ p358=1 ]
} u56={[ ]
} u55={[ ]
} u54={[ ]
} u45={[ ]
} u44={[ ]
} u53={[ ]
} u52={[ ]
} u51={[ ]
} u47={[ ]
} u50={[ ]
} u46={[ ]
} u49={[ ]
} u48={[ ]
} ]
[ u79={[ ]
} u78={[ ]
} u77={[ ]
} u76={[ ]
} u72={[ ]
} u71={[ ]
} u70={[ ]
} u69={[ ]
} u68={[ ]
} u66={[ ]
} u67={[ ]
} u65={[ ]
} u64={[ ]
} u84={[ ]
} u63={[ p377=1 ]
} u62={[ p370=1 ]
} u61={[ ]
} u60={[ ]
} u59={[ ]
} u57={[ ]
} u58={[ ]
} u56={[ ]
} u55={[ ]
} u54={[ ]
} u45={[ ]
} u44={[ ]
} u53={[ ]
} u52={[ ]
} u51={[ ]
} u47={[ ]
} u50={[ ]
} u46={[ ]
} u49={[ ]
} u48={[ ]
} ]
} u40={[ p267=1 ]
} u39={[ p229=1 ]
} u38={[ p228=1 ]
} u35={[ p218=1 ]
} u5={[ p54=1 ]
} u4={[ p53=1 ]
} i6={[ u31={[ ]
} u29={[ ]
} u23={[ ]
} u88={[ ]
} u18={[ ]
} i7={[ u90={[ ]
} u27={[ ]
} ]
} i5={[ u87={[ ]
} u22={[ ]
} ]
} u13={[ ]
} u8={[ p100=1 ]
} i3={[ u85={[ ]
} u17={[ ]
} ]
} i1={[ u89={[ p102=1 ]
[ p110=1 ]
} u12={[ ]
} ]
} ]
[ u31={[ ]
} u29={[ ]
} u23={[ ]
} u88={[ ]
} u18={[ ]
} i7={[ u90={[ ]
} u27={[ ]
} ]
} i5={[ u87={[ ]
} u22={[ ]
} ]
} u13={[ p134=1 ]
} u8={[ ]
} i3={[ u85={[ p137=1 ]
} u17={[ ]
} ]
} i1={[ u89={[ ]
} u12={[ ]
} ]
} ]
[ u31={[ ]
} u29={[ ]
} u23={[ ]
} u88={[ ]
} u18={[ p156=1 ]
} i7={[ u90={[ ]
} u27={[ ]
} ]
} i5={[ u87={[ p159=1 ]
} u22={[ ]
} ]
} u13={[ ]
} u8={[ ]
} i3={[ u85={[ ]
} u17={[ ]
} ]
} i1={[ u89={[ ]
} u12={[ ]
} ]
} ]
[ u31={[ ]
} u29={[ ]
} u23={[ p176=1 ]
} u88={[ ]
} u18={[ ]
} i7={[ u90={[ p179=1 ]
} u27={[ ]
} ]
} i5={[ u87={[ ]
} u22={[ ]
} ]
} u13={[ ]
} u8={[ ]
} i3={[ u85={[ ]
} u17={[ ]
} ]
} i1={[ u89={[ ]
} u12={[ ]
} ]
} ]
} i7={[ u83={[ p204=1 ]
} u34={[ ]
} ]
} u6={[ p72=1 ]
} u3={[ p25=1 ]
} u1={[ p2=1 ]
[ p18=1 ]
} u2={[ p21=1 ]
} ]
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527751980681

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 31, 2018 7:32:55 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 31, 2018 7:32:55 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 31, 2018 7:32:55 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 139 ms
May 31, 2018 7:32:55 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 431 places.
May 31, 2018 7:32:55 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 735 transitions.
May 31, 2018 7:32:55 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 31, 2018 7:32:55 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 44 ms
May 31, 2018 7:32:55 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 239 ms
May 31, 2018 7:32:55 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 10 ms
May 31, 2018 7:32:56 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 735 transitions.
May 31, 2018 7:32:57 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 31, 2018 7:32:57 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 111 ms
May 31, 2018 7:32:57 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 497 transitions.
May 31, 2018 7:32:57 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 92 ms
May 31, 2018 7:32:57 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 31, 2018 7:32:57 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 97 ms
May 31, 2018 7:32:57 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 31, 2018 7:32:57 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 682 redundant transitions.
May 31, 2018 7:32:57 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 10 ms
May 31, 2018 7:32:58 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 54 place invariants in 150 ms
May 31, 2018 7:32:59 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 301 variables to be positive in 1298 ms
May 31, 2018 7:32:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 497 transitions.
May 31, 2018 7:32:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/497 took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 31, 2018 7:32:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 75 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 31, 2018 7:32:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 497 transitions.
May 31, 2018 7:32:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 73 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 31, 2018 7:32:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 497 transitions.
SMT solver raised 'unknown', retrying with same input.
Skipping mayMatrices nes/nds SMT solver raised an error :unknown
java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.computeCoEnablingMatrix(NecessaryEnablingsolver.java:490)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:530)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
May 31, 2018 7:32:59 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 2576ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ASLink-PT-01a"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/ASLink-PT-01a.tgz
mv ASLink-PT-01a execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is ASLink-PT-01a, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r273-smll-152749149400008"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;