fond
Model Checking Contest 2018
8th edition, Bratislava, Slovakia, June 26, 2018
Execution of r272-smll-152749149200413
Last Updated
June 26, 2018

About the Execution of ITS-Tools for DLCflexbar-PT-4b

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15751.430 3600000.00 4547451.00 15683.00 [undef] Time out reached

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
...................
/home/mcc/execution
total 4.3M
-rw-r--r-- 1 mcc users 3.3K May 29 18:50 CTLCardinality.txt
-rw-r--r-- 1 mcc users 18K May 29 18:50 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K May 28 13:05 CTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 28 13:05 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.6K May 28 09:33 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 28 09:33 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.8K May 28 07:45 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.4K May 28 07:45 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.3K May 27 06:08 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 16K May 27 06:08 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 107 May 26 06:29 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 345 May 26 06:29 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.4K May 26 07:56 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 12K May 26 07:56 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 28 07:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 28 07:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 3 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 4.1M May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is DLCflexbar-PT-4b, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r272-smll-152749149200413

=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-4b-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1527961970541

Flatten gal took : 2090 ms
Constant places removed 1 places and 1 transitions.
Performed 7166 Post agglomeration using F-continuation condition.
Iterating post reduction 0 with 7167 rules applied. Total rules applied 7167 place count 11439 transition count 9961
Constant places removed 7167 places and 1 transitions.
Reduce isomorphic transitions removed 150 transitions.
Performed 144 Post agglomeration using F-continuation condition.
Iterating post reduction 1 with 7461 rules applied. Total rules applied 14628 place count 4272 transition count 9666
Constant places removed 144 places and 0 transitions.
Reduce isomorphic transitions removed 44 transitions.
Performed 44 Post agglomeration using F-continuation condition.
Iterating post reduction 2 with 232 rules applied. Total rules applied 14860 place count 4128 transition count 9578
Constant places removed 44 places and 0 transitions.
Iterating post reduction 3 with 44 rules applied. Total rules applied 14904 place count 4084 transition count 9578
Performed 44 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 4 with 44 Pre rules applied. Total rules applied 14904 place count 4084 transition count 9534
Constant places removed 44 places and 0 transitions.
Iterating post reduction 4 with 44 rules applied. Total rules applied 14948 place count 4040 transition count 9534
Symmetric choice reduction at 5 with 776 rule applications. Total rules 15724 place count 4040 transition count 9534
Constant places removed 776 places and 776 transitions.
Iterating post reduction 5 with 776 rules applied. Total rules applied 16500 place count 3264 transition count 8758
Performed 18 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 6 with 18 Pre rules applied. Total rules applied 16500 place count 3264 transition count 8740
Constant places removed 18 places and 0 transitions.
Iterating post reduction 6 with 18 rules applied. Total rules applied 16518 place count 3246 transition count 8740
Symmetric choice reduction at 7 with 50 rule applications. Total rules 16568 place count 3246 transition count 8740
Constant places removed 50 places and 558 transitions.
Reduce isomorphic transitions removed 44 transitions.
Iterating post reduction 7 with 94 rules applied. Total rules applied 16662 place count 3196 transition count 8138
Performed 924 Post agglomeration using F-continuation condition.
Constant places removed 924 places and 0 transitions.
Iterating post reduction 8 with 924 rules applied. Total rules applied 17586 place count 2272 transition count 7208
Symmetric choice reduction at 9 with 24 rule applications. Total rules 17610 place count 2272 transition count 7208
Constant places removed 24 places and 1176 transitions.
Iterating post reduction 9 with 24 rules applied. Total rules applied 17634 place count 2248 transition count 6032
Performed 101 Post agglomeration using F-continuation condition.
Constant places removed 101 places and 0 transitions.
Reduce isomorphic transitions removed 25 transitions.
Iterating post reduction 10 with 126 rules applied. Total rules applied 17760 place count 2147 transition count 6587
Performed 87 Post agglomeration using F-continuation condition.
Constant places removed 87 places and 0 transitions.
Reduce isomorphic transitions removed 25 transitions.
Iterating post reduction 11 with 112 rules applied. Total rules applied 17872 place count 2060 transition count 7288
Applied a total of 17872 rules in 26012 ms. Remains 2060 /11440 variables (removed 9380) and now considering 7288/17128 (removed 9840) transitions.
Normalized transition count is 6687
// Phase 1: matrix 6687 rows 2060 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
No direction supplied, using forward translation only.
Compilation finished in 149114 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 126 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -d], workingDir=/home/mcc/execution]
sparsehash FATAL ERROR: failed to allocate 35 groups

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 02, 2018 5:52:53 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Jun 02, 2018 5:52:53 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 02, 2018 5:52:54 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 858 ms
Jun 02, 2018 5:52:54 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 11440 places.
Jun 02, 2018 5:52:54 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 17128 transitions.
Jun 02, 2018 5:52:54 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
Jun 02, 2018 5:52:57 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 2080 ms
Jun 02, 2018 5:52:57 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 182 ms
Jun 02, 2018 5:52:58 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 17128 transitions.
Jun 02, 2018 5:53:29 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 39 ms
Jun 02, 2018 5:53:29 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 7288 transitions.
Jun 02, 2018 5:53:29 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Too many transitions (7288) to apply POR reductions. Disabling POR matrices.
Jun 02, 2018 5:53:30 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 1086ms conformant to PINS in folder :/home/mcc/execution
ITS-tools command line returned an error code 1

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-4b"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-4b.tgz
mv DLCflexbar-PT-4b execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is DLCflexbar-PT-4b, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r272-smll-152749149200413"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;