Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
........................
/home/mcc/execution
total 1.3M
-rw-r--r-- 1 mcc users 5.0K May 29 16:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 31K May 29 16:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K May 28 11:15 CTLFireability.txt
-rw-r--r-- 1 mcc users 15K May 28 11:15 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 24 11:17 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.6K May 24 11:17 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.4K May 28 09:23 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 28 09:23 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.8K May 28 07:38 LTLFireability.txt
-rw-r--r-- 1 mcc users 7.9K May 28 07:38 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 24 11:17 NewModel
-rw-r--r-- 1 mcc users 3.6K May 27 05:08 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 19K May 27 05:08 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 104 May 26 06:29 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 342 May 26 06:29 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 3.1K May 26 06:35 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 21K May 26 06:35 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 28 07:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 28 07:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 24 11:17 equiv_col
-rw-r--r-- 1 mcc users 4 May 24 11:17 instance
-rw-r--r-- 1 mcc users 6 May 24 11:17 iscolored
-rw-r--r-- 1 mcc users 1.1M May 24 11:17 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is ASLink-PT-07b, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r272-smll-152749148800125
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ASLink-PT-07b-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1527832291327

Flatten gal took : 863 ms
Constant places removed 1 places and 1 transitions.
Performed 1504 Post agglomeration using F-continuation condition.
Iterating post reduction 0 with 1505 rules applied. Total rules applied 1505 place count 3221 transition count 2481
Constant places removed 1601 places and 2 transitions.
Reduce isomorphic transitions removed 25 transitions.
Implicit places reduction removed 14 places :[p2951, p2823, p2428, p2402, p2033, p2007, p1638, p1612, p1243, p1217, p848, p822, p453, p427]
Performed 95 Post agglomeration using F-continuation condition.
Iterating post reduction 1 with 1735 rules applied. Total rules applied 3240 place count 1606 transition count 2359
Constant places removed 109 places and 0 transitions.
Performed 35 Post agglomeration using F-continuation condition.
Iterating post reduction 2 with 144 rules applied. Total rules applied 3384 place count 1497 transition count 2324
Constant places removed 35 places and 0 transitions.
Implicit places reduction removed 13 places :[p2792, p2778, p2397, p2383, p2002, p1988, p1607, p1593, p1212, p1198, p817, p803, p408]
Performed 13 Post agglomeration using F-continuation condition.
Iterating post reduction 3 with 61 rules applied. Total rules applied 3445 place count 1449 transition count 2311
Constant places removed 13 places and 0 transitions.
Iterating post reduction 4 with 13 rules applied. Total rules applied 3458 place count 1436 transition count 2311
Performed 221 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 5 with 221 Pre rules applied. Total rules applied 3458 place count 1436 transition count 2090
Constant places removed 222 places and 0 transitions.
Implicit places reduction removed 1 places :[p422]
Performed 1 Post agglomeration using F-continuation condition.
Iterating post reduction 5 with 224 rules applied. Total rules applied 3682 place count 1213 transition count 2089
Constant places removed 1 places and 0 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 3683 place count 1212 transition count 2089
Performed 1 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 7 with 1 Pre rules applied. Total rules applied 3683 place count 1212 transition count 2088
Constant places removed 1 places and 0 transitions.
Iterating post reduction 7 with 1 rules applied. Total rules applied 3684 place count 1211 transition count 2088
Symmetric choice reduction at 8 with 26 rule applications. Total rules 3710 place count 1211 transition count 2088
Constant places removed 26 places and 26 transitions.
Reduce isomorphic transitions removed 1 transitions.
Implicit places reduction removed 1 places :[p3221]
Performed 10 Post agglomeration using F-continuation condition.
Iterating post reduction 8 with 38 rules applied. Total rules applied 3748 place count 1184 transition count 2051
Constant places removed 11 places and 0 transitions.
Iterating post reduction 9 with 11 rules applied. Total rules applied 3759 place count 1173 transition count 2051
Symmetric choice reduction at 10 with 16 rule applications. Total rules 3775 place count 1173 transition count 2051
Constant places removed 16 places and 59 transitions.
Reduce isomorphic transitions removed 1 transitions.
Implicit places reduction removed 8 places :[p2960, p2764, p2369, p1974, p1579, p1184, p789, p394]
Performed 17 Post agglomeration using F-continuation condition.
Iterating post reduction 10 with 42 rules applied. Total rules applied 3817 place count 1149 transition count 1974
Constant places removed 17 places and 0 transitions.
Iterating post reduction 11 with 17 rules applied. Total rules applied 3834 place count 1132 transition count 1974
Symmetric choice reduction at 12 with 8 rule applications. Total rules 3842 place count 1132 transition count 1974
Constant places removed 8 places and 15 transitions.
Iterating post reduction 12 with 8 rules applied. Total rules applied 3850 place count 1124 transition count 1959
Symmetric choice reduction at 13 with 1 rule applications. Total rules 3851 place count 1124 transition count 1959
Constant places removed 1 places and 8 transitions.
Iterating post reduction 13 with 1 rules applied. Total rules applied 3852 place count 1123 transition count 1951
Symmetric choice reduction at 14 with 1 rule applications. Total rules 3853 place count 1123 transition count 1951
Constant places removed 1 places and 8 transitions.
Iterating post reduction 14 with 1 rules applied. Total rules applied 3854 place count 1122 transition count 1943
Symmetric choice reduction at 15 with 1 rule applications. Total rules 3855 place count 1122 transition count 1943
Constant places removed 1 places and 8 transitions.
Iterating post reduction 15 with 1 rules applied. Total rules applied 3856 place count 1121 transition count 1935
Symmetric choice reduction at 16 with 1 rule applications. Total rules 3857 place count 1121 transition count 1935
Constant places removed 1 places and 8 transitions.
Iterating post reduction 16 with 1 rules applied. Total rules applied 3858 place count 1120 transition count 1927
Symmetric choice reduction at 17 with 1 rule applications. Total rules 3859 place count 1120 transition count 1927
Constant places removed 1 places and 8 transitions.
Iterating post reduction 17 with 1 rules applied. Total rules applied 3860 place count 1119 transition count 1919
Symmetric choice reduction at 18 with 1 rule applications. Total rules 3861 place count 1119 transition count 1919
Constant places removed 1 places and 8 transitions.
Iterating post reduction 18 with 1 rules applied. Total rules applied 3862 place count 1118 transition count 1911
Symmetric choice reduction at 19 with 1 rule applications. Total rules 3863 place count 1118 transition count 1911
Constant places removed 1 places and 8 transitions.
Iterating post reduction 19 with 1 rules applied. Total rules applied 3864 place count 1117 transition count 1903
Symmetric choice reduction at 20 with 1 rule applications. Total rules 3865 place count 1117 transition count 1903
Constant places removed 1 places and 8 transitions.
Iterating post reduction 20 with 1 rules applied. Total rules applied 3866 place count 1116 transition count 1895
Symmetric choice reduction at 21 with 1 rule applications. Total rules 3867 place count 1116 transition count 1895
Constant places removed 1 places and 8 transitions.
Iterating post reduction 21 with 1 rules applied. Total rules applied 3868 place count 1115 transition count 1887
Symmetric choice reduction at 22 with 1 rule applications. Total rules 3869 place count 1115 transition count 1887
Constant places removed 1 places and 8 transitions.
Iterating post reduction 22 with 1 rules applied. Total rules applied 3870 place count 1114 transition count 1879
Symmetric choice reduction at 23 with 1 rule applications. Total rules 3871 place count 1114 transition count 1879
Constant places removed 1 places and 8 transitions.
Iterating post reduction 23 with 1 rules applied. Total rules applied 3872 place count 1113 transition count 1871
Symmetric choice reduction at 24 with 1 rule applications. Total rules 3873 place count 1113 transition count 1871
Constant places removed 1 places and 8 transitions.
Iterating post reduction 24 with 1 rules applied. Total rules applied 3874 place count 1112 transition count 1863
Symmetric choice reduction at 25 with 1 rule applications. Total rules 3875 place count 1112 transition count 1863
Constant places removed 1 places and 8 transitions.
Iterating post reduction 25 with 1 rules applied. Total rules applied 3876 place count 1111 transition count 1855
Symmetric choice reduction at 26 with 1 rule applications. Total rules 3877 place count 1111 transition count 1855
Constant places removed 1 places and 8 transitions.
Iterating post reduction 26 with 1 rules applied. Total rules applied 3878 place count 1110 transition count 1847
Symmetric choice reduction at 27 with 1 rule applications. Total rules 3879 place count 1110 transition count 1847
Constant places removed 1 places and 8 transitions.
Iterating post reduction 27 with 1 rules applied. Total rules applied 3880 place count 1109 transition count 1839
Performed 79 Post agglomeration using F-continuation condition.
Constant places removed 79 places and 0 transitions.
Iterating post reduction 28 with 79 rules applied. Total rules applied 3959 place count 1030 transition count 1753
Performed 1 Post agglomeration using F-continuation condition.
Constant places removed 1 places and 0 transitions.
Iterating post reduction 29 with 1 rules applied. Total rules applied 3960 place count 1029 transition count 1762
Applied a total of 3960 rules in 3142 ms. Remains 1029 /3222 variables (removed 2193) and now considering 1762/3986 (removed 2224) transitions.
// Phase 1: matrix 1762 rows 1029 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 24185 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 67 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -d], workingDir=/home/mcc/execution]
terminate called after throwing an instance of 'std::bad_alloc'
what(): std::bad_alloc

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 01, 2018 5:51:34 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Jun 01, 2018 5:51:34 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 01, 2018 5:51:34 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 450 ms
Jun 01, 2018 5:51:34 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 3222 places.
Jun 01, 2018 5:51:35 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 3986 transitions.
Jun 01, 2018 5:51:35 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
Jun 01, 2018 5:51:35 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 857 ms
Jun 01, 2018 5:51:36 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 74 ms
Jun 01, 2018 5:51:36 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 3986 transitions.
Jun 01, 2018 5:51:41 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 11 ms
Jun 01, 2018 5:51:41 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1762 transitions.
Jun 01, 2018 5:51:41 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Too many transitions (1762) to apply POR reductions. Disabling POR matrices.
Jun 01, 2018 5:51:41 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 327ms conformant to PINS in folder :/home/mcc/execution
ITS-tools command line returned an error code 134

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ASLink-PT-07b"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/ASLink-PT-07b.tgz
mv ASLink-PT-07b execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is ASLink-PT-07b, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r272-smll-152749148800125"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;