Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.........................................................................................
/home/mcc/execution
total 1.3M
-rw-r--r-- 1 mcc users 40K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 114K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 24K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 82K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 20K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 53K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 15K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 52K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 37K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 106K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 104 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 342 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 29K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 100K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 12K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 25K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 2 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 511K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is Peterson-PT-4, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r261-csrt-152732586000164
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Peterson-PT-4-LTLFireability-00
FORMULA_NAME Peterson-PT-4-LTLFireability-01
FORMULA_NAME Peterson-PT-4-LTLFireability-02
FORMULA_NAME Peterson-PT-4-LTLFireability-03
FORMULA_NAME Peterson-PT-4-LTLFireability-04
FORMULA_NAME Peterson-PT-4-LTLFireability-05
FORMULA_NAME Peterson-PT-4-LTLFireability-06
FORMULA_NAME Peterson-PT-4-LTLFireability-07
FORMULA_NAME Peterson-PT-4-LTLFireability-08
FORMULA_NAME Peterson-PT-4-LTLFireability-09
FORMULA_NAME Peterson-PT-4-LTLFireability-10
FORMULA_NAME Peterson-PT-4-LTLFireability-11
FORMULA_NAME Peterson-PT-4-LTLFireability-12
FORMULA_NAME Peterson-PT-4-LTLFireability-13
FORMULA_NAME Peterson-PT-4-LTLFireability-14
FORMULA_NAME Peterson-PT-4-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527504714915

Converted graph to binary with : CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.louvain.binaries_1.0.0.201805241334/bin/convert-linux64, -i, /tmp/graph6272661719332239766.txt, -o, /tmp/graph6272661719332239766.bin, -w, /tmp/graph6272661719332239766.weights], workingDir=null]
Built communities with : CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.louvain.binaries_1.0.0.201805241334/bin/louvain-linux64, /tmp/graph6272661719332239766.bin, -l, -1, -v, -w, /tmp/graph6272661719332239766.weights, -q, 0, -e, 0.001], workingDir=null]
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((G("((((((((((((((((((((i6.u23.IsEndLoop_2_3_4>=1)||(i6.u22.IsEndLoop_3_3_4>=1))||(i8.u7.IsEndLoop_4_3_4>=1))||(i7.u17.IsEndLoop_3_2_4>=1))||(i10.u9.IsEndLoop_4_2_4>=1))||(i6.u88.IsEndLoop_0_3_4>=1))||(i6.u15.IsEndLoop_1_3_4>=1))||(i7.u18.IsEndLoop_0_2_4>=1))||(i18.u122.IsEndLoop_4_1_4>=1))||(i7.u84.IsEndLoop_2_2_4>=1))||(i7.u83.IsEndLoop_1_2_4>=1))||(i3.u13.IsEndLoop_1_1_4>=1))||(i3.u12.IsEndLoop_0_1_4>=1))||(i3.u11.IsEndLoop_3_1_4>=1))||(i3.u10.IsEndLoop_2_1_4>=1))||(i5.u14.IsEndLoop_2_0_4>=1))||(i5.u62.IsEndLoop_1_0_4>=1))||(i19.u120.IsEndLoop_4_0_4>=1))||(i5.u64.IsEndLoop_3_0_4>=1))||(i5.u8.IsEndLoop_0_0_4>=1))")))
Formula 0 simplified : !G"((((((((((((((((((((i6.u23.IsEndLoop_2_3_4>=1)||(i6.u22.IsEndLoop_3_3_4>=1))||(i8.u7.IsEndLoop_4_3_4>=1))||(i7.u17.IsEndLoop_3_2_4>=1))||(i10.u9.IsEndLoop_4_2_4>=1))||(i6.u88.IsEndLoop_0_3_4>=1))||(i6.u15.IsEndLoop_1_3_4>=1))||(i7.u18.IsEndLoop_0_2_4>=1))||(i18.u122.IsEndLoop_4_1_4>=1))||(i7.u84.IsEndLoop_2_2_4>=1))||(i7.u83.IsEndLoop_1_2_4>=1))||(i3.u13.IsEndLoop_1_1_4>=1))||(i3.u12.IsEndLoop_0_1_4>=1))||(i3.u11.IsEndLoop_3_1_4>=1))||(i3.u10.IsEndLoop_2_1_4>=1))||(i5.u14.IsEndLoop_2_0_4>=1))||(i5.u62.IsEndLoop_1_0_4>=1))||(i19.u120.IsEndLoop_4_0_4>=1))||(i5.u64.IsEndLoop_3_0_4>=1))||(i5.u8.IsEndLoop_0_0_4>=1))"
built 122 ordering constraints for composite.
built 11 ordering constraints for composite.
built 25 ordering constraints for composite.
built 8 ordering constraints for composite.
built 80 ordering constraints for composite.
built 47 ordering constraints for composite.
built 119 ordering constraints for composite.
built 118 ordering constraints for composite.
built 84 ordering constraints for composite.
built 6 ordering constraints for composite.
built 11 ordering constraints for composite.
built 8 ordering constraints for composite.
built 10 ordering constraints for composite.
built 5 ordering constraints for composite.
built 8 ordering constraints for composite.
built 8 ordering constraints for composite.
built 8 ordering constraints for composite.
built 8 ordering constraints for composite.
built 28 ordering constraints for composite.
built 8 ordering constraints for composite.
built 8 ordering constraints for composite.
built 8 ordering constraints for composite.
built 6 ordering constraints for composite.
built 8 ordering constraints for composite.
built 8 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 630
// Phase 1: matrix 630 rows 480 cols
invariant :i5:u126:WantSection_0_T + i5:u126:Idle_0 = 1
invariant :i1:u1:IsEndLoop_1_1_0 + i1:u1:IsEndLoop_1_1_1 + i1:u1:BeginLoop_1_1_1 + i1:u1:TestIdentity_1_1_1 + i1:u34:BeginLoop_1_1_2 + i1:u34:TestAlone_1_1_2 + i1:u34:TestIdentity_1_1_2 + i3:u13:IsEndLoop_1_1_4 + i3:u13:EndTurn_1_1 + i3:u13:TestTurn_1_1 + i3:u13:AskForSection_1_1 + i3:u75:BeginLoop_1_1_0 + i3:u75:TestAlone_1_1_0 + i3:u75:TestIdentity_1_1_0 + i4:u56:IsEndLoop_1_1_2 + i4:u56:BeginLoop_1_1_3 + i4:u56:TestAlone_1_1_3 + i4:u56:TestIdentity_1_1_3 + i4:u121:IsEndLoop_1_1_3 + i4:u121:BeginLoop_1_1_4 + i4:u121:TestAlone_1_1_4 + i4:u121:TestIdentity_1_1_4 + i4:u105:IsEndLoop_1_0_3 + i4:u105:BeginLoop_1_0_4 + i4:u105:TestAlone_1_0_4 + i4:u105:TestIdentity_1_0_4 + i5:u20:BeginLoop_1_0_0 + i5:u20:TestAlone_1_0_0 + i5:u20:TestIdentity_1_0_0 + i5:u62:IsEndLoop_1_0_4 + i5:u62:EndTurn_1_0 + i5:u62:TestTurn_1_0 + i5:u62:AskForSection_1_0 + i6:u15:IsEndLoop_1_3_4 + i6:u15:EndTurn_1_3 + i6:u15:TestTurn_1_3 + i6:u15:CS_1 + i6:u15:AskForSection_1_3 + i6:u78:BeginLoop_1_3_0 + i6:u78:TestAlone_1_3_0 + i6:u78:TestIdentity_1_3_0 + i7:u82:BeginLoop_1_2_0 + i7:u82:TestAlone_1_2_0 + i7:u82:TestIdentity_1_2_0 + i7:u83:IsEndLoop_1_2_4 + i7:u83:EndTurn_1_2 + i7:u83:TestTurn_1_2 + i7:u83:AskForSection_1_2 + i12:u37:IsEndLoop_1_0_0 + i12:u37:IsEndLoop_1_0_1 + i12:u37:BeginLoop_1_0_1 + i12:u37:BeginLoop_1_0_2 + i12:u37:TestAlone_1_0_2 + i12:u37:TestIdentity_1_0_2 + i12:u37:TestIdentity_1_0_1 + i12:u110:IsEndLoop_1_0_2 + i12:u110:BeginLoop_1_0_3 + i12:u110:TestAlone_1_0_3 + i12:u110:TestIdentity_1_0_3 + i17:u89:WantSection_1_F + i20:u38:IsEndLoop_1_3_0 + i20:u38:IsEndLoop_1_3_1 + i20:u38:BeginLoop_1_3_1 + i20:u38:TestIdentity_1_3_1 + i20:u114:BeginLoop_1_3_2 + i20:u114:TestAlone_1_3_2 + i20:u114:TestIdentity_1_3_2 + i20:u104:IsEndLoop_1_3_2 + i20:u104:BeginLoop_1_3_3 + i20:u104:TestAlone_1_3_3 + i20:u104:TestIdentity_1_3_3 + i20:u117:IsEndLoop_1_3_3 + i20:u117:BeginLoop_1_3_4 + i20:u117:TestAlone_1_3_4 + i20:u117:TestIdentity_1_3_4 + i22:u35:IsEndLoop_1_2_0 + i22:u35:IsEndLoop_1_2_1 + i22:u35:BeginLoop_1_2_1 + i22:u35:TestIdentity_1_2_1 + i22:u113:BeginLoop_1_2_2 + i22:u113:TestAlone_1_2_2 + i22:u113:TestIdentity_1_2_2 + i22:u108:IsEndLoop_1_2_2 + i22:u108:BeginLoop_1_2_3 + i22:u108:TestAlone_1_2_3 + i22:u108:TestIdentity_1_2_3 + i22:u116:IsEndLoop_1_2_3 + i22:u116:BeginLoop_1_2_4 + i22:u116:TestAlone_1_2_4 + i22:u116:TestIdentity_1_2_4 = 1
invariant :i6:u123:WantSection_4_T + i6:u123:Idle_4 = 1
invariant :i5:u63:Turn_0_2 + i5:u63:Turn_0_3 + i5:u63:Turn_0_0 + i5:u63:Turn_0_1 + i5:u63:Turn_0_4 = 1
invariant :i4:u55:WantSection_2_F + -1'i6:u48:Idle_2 = 0
invariant :i4:u67:WantSection_3_F + -1'i5:u124:Idle_3 = 0
invariant :i6:u48:WantSection_2_T + i6:u48:Idle_2 = 1
invariant :i5:u124:WantSection_3_T + i5:u124:Idle_3 = 1
invariant :i1:u96:WantSection_0_F + -1'i5:u126:Idle_0 = 0
invariant :i6:u15:Turn_3_1 + i6:u15:Turn_3_2 + i6:u15:Turn_3_0 + i6:u15:Turn_3_4 + i6:u15:Turn_3_3 = 1
invariant :i1:u36:IsEndLoop_4_3_0 + i1:u36:BeginLoop_4_3_1 + i1:u36:TestAlone_4_3_1 + i1:u36:TestIdentity_4_3_1 + i3:u28:BeginLoop_4_1_0 + i3:u28:TestAlone_4_1_0 + i3:u28:TestIdentity_4_1_0 + i3:u85:EndTurn_4_1 + i3:u85:TestTurn_4_1 + i3:u85:AskForSection_4_1 + i5:u19:BeginLoop_4_0_0 + i5:u19:TestAlone_4_0_0 + i5:u19:TestIdentity_4_0_0 + i5:u63:EndTurn_4_0 + i5:u63:TestTurn_4_0 + i5:u63:AskForSection_4_0 + i6:u21:EndTurn_4_3 + i6:u21:TestTurn_4_3 + i6:u21:AskForSection_4_3 + i6:u21:CS_4 + i6:u95:BeginLoop_4_3_0 + i6:u95:TestAlone_4_3_0 + i6:u95:TestIdentity_4_3_0 + i6:u123:Idle_4 + i7:u16:EndTurn_4_2 + i7:u16:TestTurn_4_2 + i7:u16:AskForSection_4_2 + i7:u80:BeginLoop_4_2_0 + i7:u80:TestAlone_4_2_0 + i7:u80:TestIdentity_4_2_0 + i8:u7:IsEndLoop_4_3_3 + i8:u7:IsEndLoop_4_3_4 + i8:u7:BeginLoop_4_3_4 + i8:u7:TestIdentity_4_3_4 + i8:u39:IsEndLoop_4_3_1 + i8:u39:BeginLoop_4_3_2 + i8:u39:TestAlone_4_3_2 + i8:u39:TestIdentity_4_3_2 + i8:u66:IsEndLoop_4_3_2 + i8:u66:BeginLoop_4_3_3 + i8:u66:TestAlone_4_3_3 + i8:u66:TestIdentity_4_3_3 + i10:u9:IsEndLoop_4_2_3 + i10:u9:IsEndLoop_4_2_4 + i10:u9:BeginLoop_4_2_4 + i10:u9:TestIdentity_4_2_4 + i10:u30:IsEndLoop_4_2_0 + i10:u30:BeginLoop_4_2_1 + i10:u30:TestAlone_4_2_1 + i10:u30:TestIdentity_4_2_1 + i10:u43:IsEndLoop_4_2_2 + i10:u43:BeginLoop_4_2_3 + i10:u43:TestAlone_4_2_3 + i10:u43:TestIdentity_4_2_3 + i10:u54:IsEndLoop_4_2_1 + i10:u54:BeginLoop_4_2_2 + i10:u54:TestAlone_4_2_2 + i10:u54:TestIdentity_4_2_2 + i18:u44:IsEndLoop_4_1_2 + i18:u44:BeginLoop_4_1_3 + i18:u44:TestAlone_4_1_3 + i18:u44:TestIdentity_4_1_3 + i18:u52:IsEndLoop_4_1_1 + i18:u52:BeginLoop_4_1_2 + i18:u52:TestAlone_4_1_2 + i18:u52:TestIdentity_4_1_2 + i18:u100:IsEndLoop_4_1_0 + i18:u100:BeginLoop_4_1_1 + i18:u100:TestAlone_4_1_1 + i18:u100:TestIdentity_4_1_1 + i18:u122:IsEndLoop_4_1_3 + i18:u122:IsEndLoop_4_1_4 + i18:u122:BeginLoop_4_1_4 + i18:u122:TestIdentity_4_1_4 + i19:u111:IsEndLoop_4_0_2 + i19:u111:BeginLoop_4_0_3 + i19:u111:TestAlone_4_0_3 + i19:u111:TestIdentity_4_0_3 + i19:u120:IsEndLoop_4_0_3 + i19:u120:IsEndLoop_4_0_4 + i19:u120:BeginLoop_4_0_4 + i19:u120:TestIdentity_4_0_4 + i19:u92:IsEndLoop_4_0_1 + i19:u92:BeginLoop_4_0_2 + i19:u92:TestAlone_4_0_2 + i19:u92:TestIdentity_4_0_2 + i19:u94:IsEndLoop_4_0_0 + i19:u94:BeginLoop_4_0_1 + i19:u94:TestAlone_4_0_1 + i19:u94:TestIdentity_4_0_1 = 1
invariant :i3:u12:Turn_1_2 + i3:u12:Turn_1_3 + i3:u12:Turn_1_0 + i3:u12:Turn_1_1 + i3:u12:Turn_1_4 = 1
invariant :i0:u0:IsEndLoop_0_3_0 + i0:u0:BeginLoop_0_3_1 + i0:u31:TestAlone_0_3_1 + i0:u31:TestIdentity_0_3_1 + i0:u53:IsEndLoop_0_3_1 + i0:u53:BeginLoop_0_3_2 + i0:u53:TestAlone_0_3_2 + i0:u53:TestIdentity_0_3_2 + i0:u79:BeginLoop_0_3_0 + i0:u79:TestIdentity_0_3_0 + i0:u61:IsEndLoop_0_3_3 + i0:u61:BeginLoop_0_3_4 + i0:u61:TestAlone_0_3_4 + i0:u61:TestIdentity_0_3_4 + i0:u103:IsEndLoop_0_3_2 + i0:u103:BeginLoop_0_3_3 + i0:u103:TestAlone_0_3_3 + i0:u103:TestIdentity_0_3_3 + i3:u12:IsEndLoop_0_1_4 + i3:u12:EndTurn_0_1 + i3:u12:TestTurn_0_1 + i3:u12:AskForSection_0_1 + i4:u55:IsEndLoop_0_0_2 + i4:u55:BeginLoop_0_0_3 + i4:u55:TestAlone_0_0_3 + i4:u55:TestIdentity_0_0_3 + i4:u67:IsEndLoop_0_0_3 + i4:u67:BeginLoop_0_0_4 + i4:u67:TestAlone_0_0_4 + i4:u67:TestIdentity_0_0_4 + i5:u8:IsEndLoop_0_0_4 + i5:u8:EndTurn_0_0 + i5:u8:TestTurn_0_0 + i5:u8:AskForSection_0_0 + i5:u126:Idle_0 + i6:u88:IsEndLoop_0_3_4 + i6:u88:EndTurn_0_3 + i6:u88:TestTurn_0_3 + i6:u88:CS_0 + i6:u88:AskForSection_0_3 + i7:u18:IsEndLoop_0_2_4 + i7:u18:EndTurn_0_2 + i7:u18:TestTurn_0_2 + i7:u18:AskForSection_0_2 + i9:u29:IsEndLoop_0_2_0 + i9:u29:BeginLoop_0_2_1 + i9:u51:IsEndLoop_0_2_1 + i9:u51:BeginLoop_0_2_2 + i9:u51:TestAlone_0_2_2 + i9:u51:TestIdentity_0_2_2 + i9:u72:BeginLoop_0_2_0 + i9:u72:TestIdentity_0_2_0 + i9:u101:TestAlone_0_2_1 + i9:u101:TestIdentity_0_2_1 + i9:u60:IsEndLoop_0_2_3 + i9:u60:BeginLoop_0_2_4 + i9:u60:TestAlone_0_2_4 + i9:u60:TestIdentity_0_2_4 + i9:u106:IsEndLoop_0_2_2 + i9:u106:BeginLoop_0_2_3 + i9:u106:TestAlone_0_2_3 + i9:u106:TestIdentity_0_2_3 + i11:u32:BeginLoop_0_1_1 + i11:u32:TestAlone_0_1_1 + i11:u32:TestIdentity_0_1_1 + i11:u59:IsEndLoop_0_1_1 + i11:u59:BeginLoop_0_1_2 + i11:u59:TestAlone_0_1_2 + i11:u59:TestIdentity_0_1_2 + i11:u76:IsEndLoop_0_1_0 + i11:u76:BeginLoop_0_1_0 + i11:u76:TestIdentity_0_1_0 + i11:u57:IsEndLoop_0_1_2 + i11:u57:BeginLoop_0_1_3 + i11:u57:TestAlone_0_1_3 + i11:u57:TestIdentity_0_1_3 + i11:u70:IsEndLoop_0_1_3 + i11:u70:BeginLoop_0_1_4 + i11:u70:TestAlone_0_1_4 + i11:u70:TestIdentity_0_1_4 + i17:u27:IsEndLoop_0_0_0 + i17:u27:BeginLoop_0_0_1 + i17:u50:TestAlone_0_0_1 + i17:u50:TestIdentity_0_0_1 + i17:u87:BeginLoop_0_0_0 + i17:u87:TestIdentity_0_0_0 + i17:u89:IsEndLoop_0_0_1 + i17:u89:BeginLoop_0_0_2 + i17:u89:TestAlone_0_0_2 + i17:u89:TestIdentity_0_0_2 = 1
invariant :i3:u11:IsEndLoop_3_1_4 + i3:u11:EndTurn_3_1 + i3:u11:TestTurn_3_1 + i3:u11:AskForSection_3_1 + i3:u73:BeginLoop_3_1_0 + i3:u73:TestAlone_3_1_0 + i3:u73:TestIdentity_3_1_0 + i4:u4:IsEndLoop_3_1_2 + i4:u4:IsEndLoop_3_1_3 + i4:u4:BeginLoop_3_1_3 + i4:u4:TestIdentity_3_1_3 + i4:u47:BeginLoop_3_1_4 + i4:u47:TestAlone_3_1_4 + i4:u47:TestIdentity_3_1_4 + i5:u64:IsEndLoop_3_0_4 + i5:u64:EndTurn_3_0 + i5:u64:TestTurn_3_0 + i5:u64:AskForSection_3_0 + i5:u77:BeginLoop_3_0_0 + i5:u77:TestAlone_3_0_0 + i5:u77:TestIdentity_3_0_0 + i5:u124:Idle_3 + i6:u22:IsEndLoop_3_3_4 + i6:u22:EndTurn_3_3 + i6:u22:TestTurn_3_3 + i6:u22:AskForSection_3_3 + i6:u22:CS_3 + i6:u25:BeginLoop_3_3_0 + i6:u25:TestAlone_3_3_0 + i6:u25:TestIdentity_3_3_0 + i7:u17:IsEndLoop_3_2_4 + i7:u17:EndTurn_3_2 + i7:u17:TestTurn_3_2 + i7:u17:AskForSection_3_2 + i7:u24:BeginLoop_3_2_0 + i7:u24:TestAlone_3_2_0 + i7:u24:TestIdentity_3_2_0 + i15:u97:IsEndLoop_3_2_0 + i15:u97:BeginLoop_3_2_1 + i15:u97:TestAlone_3_2_1 + i15:u97:TestIdentity_3_2_1 + i15:u112:IsEndLoop_3_2_1 + i15:u112:BeginLoop_3_2_2 + i15:u112:TestAlone_3_2_2 + i15:u112:TestIdentity_3_2_2 + i15:u5:IsEndLoop_3_2_2 + i15:u5:IsEndLoop_3_2_3 + i15:u5:BeginLoop_3_2_3 + i15:u5:TestIdentity_3_2_3 + i15:u46:BeginLoop_3_2_4 + i15:u46:TestAlone_3_2_4 + i15:u46:TestIdentity_3_2_4 + i16:u41:IsEndLoop_3_0_2 + i16:u41:IsEndLoop_3_0_3 + i16:u41:BeginLoop_3_0_3 + i16:u41:TestIdentity_3_0_3 + i16:u69:BeginLoop_3_0_4 + i16:u69:TestAlone_3_0_4 + i16:u69:TestIdentity_3_0_4 + i16:u49:IsEndLoop_3_0_0 + i16:u49:BeginLoop_3_0_1 + i16:u49:TestAlone_3_0_1 + i16:u49:TestIdentity_3_0_1 + i16:u93:IsEndLoop_3_0_1 + i16:u93:BeginLoop_3_0_2 + i16:u93:TestAlone_3_0_2 + i16:u93:TestIdentity_3_0_2 + i17:u33:IsEndLoop_3_1_1 + i17:u33:BeginLoop_3_1_2 + i17:u33:TestAlone_3_1_2 + i17:u33:TestIdentity_3_1_2 + i17:u99:IsEndLoop_3_1_0 + i17:u99:BeginLoop_3_1_1 + i17:u99:TestAlone_3_1_1 + i17:u99:TestIdentity_3_1_1 + i23:u40:IsEndLoop_3_3_1 + i23:u40:BeginLoop_3_3_2 + i23:u40:TestAlone_3_3_2 + i23:u40:TestIdentity_3_3_2 + i23:u90:IsEndLoop_3_3_0 + i23:u90:BeginLoop_3_3_1 + i23:u90:TestAlone_3_3_1 + i23:u90:TestIdentity_3_3_1 + i23:u6:IsEndLoop_3_3_2 + i23:u6:IsEndLoop_3_3_3 + i23:u6:BeginLoop_3_3_3 + i23:u6:TestIdentity_3_3_3 + i23:u118:BeginLoop_3_3_4 + i23:u118:TestAlone_3_3_4 + i23:u118:TestIdentity_3_3_4 = 1
invariant :i1:u96:IsEndLoop_2_0_0 + i1:u96:BeginLoop_2_0_1 + i1:u96:TestAlone_2_0_1 + i1:u96:TestIdentity_2_0_1 + i2:u3:IsEndLoop_2_1_1 + i2:u3:IsEndLoop_2_1_2 + i2:u3:BeginLoop_2_1_2 + i2:u3:TestIdentity_2_1_2 + i2:u71:IsEndLoop_2_1_3 + i2:u71:BeginLoop_2_1_4 + i2:u71:TestAlone_2_1_4 + i2:u71:TestIdentity_2_1_4 + i2:u98:IsEndLoop_2_1_0 + i2:u98:BeginLoop_2_1_1 + i2:u98:TestAlone_2_1_1 + i2:u98:TestIdentity_2_1_1 + i2:u107:BeginLoop_2_1_3 + i2:u107:TestAlone_2_1_3 + i2:u107:TestIdentity_2_1_3 + i3:u10:IsEndLoop_2_1_4 + i3:u10:EndTurn_2_1 + i3:u10:TestTurn_2_1 + i3:u10:AskForSection_2_1 + i3:u74:BeginLoop_2_1_0 + i3:u74:TestAlone_2_1_0 + i3:u74:TestIdentity_2_1_0 + i5:u14:IsEndLoop_2_0_4 + i5:u14:EndTurn_2_0 + i5:u14:TestTurn_2_0 + i5:u14:AskForSection_2_0 + i5:u86:BeginLoop_2_0_0 + i5:u86:TestAlone_2_0_0 + i5:u86:TestIdentity_2_0_0 + i6:u23:IsEndLoop_2_3_4 + i6:u23:EndTurn_2_3 + i6:u23:TestTurn_2_3 + i6:u23:AskForSection_2_3 + i6:u23:CS_2 + i6:u26:BeginLoop_2_3_0 + i6:u26:TestAlone_2_3_0 + i6:u26:TestIdentity_2_3_0 + i6:u48:Idle_2 + i7:u81:BeginLoop_2_2_0 + i7:u81:TestAlone_2_2_0 + i7:u81:TestIdentity_2_2_0 + i7:u84:IsEndLoop_2_2_4 + i7:u84:EndTurn_2_2 + i7:u84:TestTurn_2_2 + i7:u84:AskForSection_2_2 + i13:u42:IsEndLoop_2_3_1 + i13:u42:IsEndLoop_2_3_2 + i13:u42:BeginLoop_2_3_2 + i13:u42:TestIdentity_2_3_2 + i13:u91:IsEndLoop_2_3_0 + i13:u91:BeginLoop_2_3_1 + i13:u91:TestAlone_2_3_1 + i13:u91:TestIdentity_2_3_1 + i13:u102:BeginLoop_2_3_3 + i13:u102:TestAlone_2_3_3 + i13:u102:TestIdentity_2_3_3 + i13:u119:IsEndLoop_2_3_3 + i13:u119:BeginLoop_2_3_4 + i13:u119:TestAlone_2_3_4 + i13:u119:TestIdentity_2_3_4 + i14:u45:IsEndLoop_2_2_1 + i14:u45:IsEndLoop_2_2_2 + i14:u45:BeginLoop_2_2_2 + i14:u45:TestIdentity_2_2_2 + i14:u58:IsEndLoop_2_2_0 + i14:u58:BeginLoop_2_2_1 + i14:u58:TestAlone_2_2_1 + i14:u58:TestIdentity_2_2_1 + i14:u65:BeginLoop_2_2_3 + i14:u65:TestAlone_2_2_3 + i14:u65:TestIdentity_2_2_3 + i14:u115:IsEndLoop_2_2_3 + i14:u115:BeginLoop_2_2_4 + i14:u115:TestAlone_2_2_4 + i14:u115:TestIdentity_2_2_4 + i21:u2:IsEndLoop_2_0_1 + i21:u2:IsEndLoop_2_0_2 + i21:u2:BeginLoop_2_0_2 + i21:u2:TestIdentity_2_0_2 + i21:u68:IsEndLoop_2_0_3 + i21:u68:BeginLoop_2_0_4 + i21:u68:TestAlone_2_0_4 + i21:u68:TestIdentity_2_0_4 + i21:u109:BeginLoop_2_0_3 + i21:u109:TestAlone_2_0_3 + i21:u109:TestIdentity_2_0_3 = 1
invariant :i7:u16:Turn_2_4 + i7:u17:Turn_2_3 + i7:u18:Turn_2_0 + i7:u83:Turn_2_1 + i7:u84:Turn_2_2 = 1
invariant :i5:u125:Idle_1 + -1'i17:u89:WantSection_1_F = 0
invariant :i6:u123:WantSection_4_F + -1'i6:u123:Idle_4 = 0
invariant :i5:u125:WantSection_1_T + i17:u89:WantSection_1_F = 1
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 9536 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 220 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP0==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1308 ms.
FORMULA Peterson-PT-4-LTLFireability-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>((<>((LTLAP1==true)))U(X((LTLAP2==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 77 ms.
FORMULA Peterson-PT-4-LTLFireability-01 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((LTLAP1==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1208 ms.
FORMULA Peterson-PT-4-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(((LTLAP3==true))U(X(X((LTLAP4==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 137 ms.
FORMULA Peterson-PT-4-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ([](X([]((LTLAP5==true)))))U([]([]([]((LTLAP6==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 74 ms.
FORMULA Peterson-PT-4-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ([]([](X((LTLAP7==true)))))U([]([]([]((LTLAP8==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 72 ms.
FORMULA Peterson-PT-4-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, []([](X(((LTLAP9==true))U((LTLAP1==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 112 ms.
FORMULA Peterson-PT-4-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>((<>((LTLAP6==true)))U((LTLAP5==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 39 ms.
FORMULA Peterson-PT-4-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>([](<>(X(<>((LTLAP10==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 75 ms.
FORMULA Peterson-PT-4-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X(X(X((LTLAP11==true)))))U((LTLAP12==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 85 ms.
FORMULA Peterson-PT-4-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (([]((LTLAP13==true)))U((LTLAP14==true)))U((LTLAP15==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1167 ms.
FORMULA Peterson-PT-4-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>([](X(((LTLAP16==true))U((LTLAP17==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 68 ms.
FORMULA Peterson-PT-4-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP18==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1176 ms.
FORMULA Peterson-PT-4-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (<>([](X((LTLAP19==true)))))U((LTLAP20==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 56 ms.
FORMULA Peterson-PT-4-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((<>((LTLAP21==true)))U(((LTLAP22==true))U((LTLAP23==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 60 ms.
FORMULA Peterson-PT-4-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, []([]([](X(<>((LTLAP24==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 44 ms.
FORMULA Peterson-PT-4-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1527504790718

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 28, 2018 10:51:56 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 28, 2018 10:51:56 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 28, 2018 10:51:57 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 107 ms
May 28, 2018 10:51:57 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 480 places.
May 28, 2018 10:51:57 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 690 transitions.
May 28, 2018 10:51:57 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 42 ms
May 28, 2018 10:51:57 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 28, 2018 10:51:57 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 121 ms
May 28, 2018 10:51:57 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 82 ms
Begin: Mon May 28 10:51:57 2018

Computation of communities with the Newman-Girvan Modularity quality function

level 0:
start computation: Mon May 28 10:51:57 2018
network size: 480 nodes, 1980 links, 1380 weight
quality increased from -0.00319261 to 0.557626
end computation: Mon May 28 10:51:57 2018
level 1:
start computation: Mon May 28 10:51:57 2018
network size: 127 nodes, 889 links, 1380 weight
quality increased from 0.557626 to 0.709183
end computation: Mon May 28 10:51:57 2018
level 2:
start computation: Mon May 28 10:51:57 2018
network size: 37 nodes, 271 links, 1380 weight
quality increased from 0.709183 to 0.714265
end computation: Mon May 28 10:51:57 2018
level 3:
start computation: Mon May 28 10:51:57 2018
network size: 24 nodes, 184 links, 1380 weight
quality increased from 0.714265 to 0.714265
end computation: Mon May 28 10:51:57 2018
End: Mon May 28 10:51:57 2018
Total duration: 0 sec
0.714265
May 28, 2018 10:51:57 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 28, 2018 10:51:57 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 58 ms
May 28, 2018 10:51:57 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 28, 2018 10:51:58 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 487 redundant transitions.
May 28, 2018 10:51:58 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 28 ms
May 28, 2018 10:51:58 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 8 ms
May 28, 2018 10:51:58 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 690 transitions.
May 28, 2018 10:51:58 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 19 place invariants in 165 ms
May 28, 2018 10:51:59 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 480 variables to be positive in 986 ms
May 28, 2018 10:51:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 690 transitions.
May 28, 2018 10:51:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/690 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 10:51:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 71 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 10:51:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 690 transitions.
May 28, 2018 10:51:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 33 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 10:52:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 690 transitions.
May 28, 2018 10:52:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/690) took 71 ms. Total solver calls (SAT/UNSAT): 137(0/137)
May 28, 2018 10:52:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(9/690) took 3537 ms. Total solver calls (SAT/UNSAT): 1492(23/1469)
May 28, 2018 10:52:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(13/690) took 7436 ms. Total solver calls (SAT/UNSAT): 2176(50/2126)
May 28, 2018 10:52:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(17/690) took 11039 ms. Total solver calls (SAT/UNSAT): 2844(76/2768)
May 28, 2018 10:52:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(20/690) took 14676 ms. Total solver calls (SAT/UNSAT): 3336(94/3242)
May 28, 2018 10:52:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(24/690) took 18420 ms. Total solver calls (SAT/UNSAT): 3977(120/3857)
May 28, 2018 10:52:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(38/690) took 22329 ms. Total solver calls (SAT/UNSAT): 5919(157/5762)
May 28, 2018 10:52:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(40/690) took 27805 ms. Total solver calls (SAT/UNSAT): 6209(189/6020)
May 28, 2018 10:52:47 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(47/690) took 30832 ms. Total solver calls (SAT/UNSAT): 7137(205/6932)
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown' twice, overapproximating result to 1.
May 28, 2018 10:52:49 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 32424 ms. Total solver calls (SAT/UNSAT): 8318(206/8112)
May 28, 2018 10:52:49 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 690 transitions.
May 28, 2018 10:52:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 4574 ms. Total solver calls (SAT/UNSAT): 2336(0/2336)
May 28, 2018 10:52:54 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 55981ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Peterson-PT-4"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/Peterson-PT-4.tgz
mv Peterson-PT-4 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is Peterson-PT-4, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r261-csrt-152732586000164"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;