Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
....................
/home/mcc/execution
total 688K
-rw-r--r-- 1 mcc users 15K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 49K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 17K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 59K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 11K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 32K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 7.0K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 27K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 41K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 104 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 342 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 21K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 8.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 2 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 248K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is Peterson-PT-3, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r260-csrt-152732585400162
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Peterson-PT-3-LTLFireability-00
FORMULA_NAME Peterson-PT-3-LTLFireability-01
FORMULA_NAME Peterson-PT-3-LTLFireability-02
FORMULA_NAME Peterson-PT-3-LTLFireability-03
FORMULA_NAME Peterson-PT-3-LTLFireability-04
FORMULA_NAME Peterson-PT-3-LTLFireability-05
FORMULA_NAME Peterson-PT-3-LTLFireability-06
FORMULA_NAME Peterson-PT-3-LTLFireability-07
FORMULA_NAME Peterson-PT-3-LTLFireability-08
FORMULA_NAME Peterson-PT-3-LTLFireability-09
FORMULA_NAME Peterson-PT-3-LTLFireability-10
FORMULA_NAME Peterson-PT-3-LTLFireability-11
FORMULA_NAME Peterson-PT-3-LTLFireability-12
FORMULA_NAME Peterson-PT-3-LTLFireability-13
FORMULA_NAME Peterson-PT-3-LTLFireability-14
FORMULA_NAME Peterson-PT-3-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527489553543

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !(("(((((WantSection_3_F>=1)&&(Idle_3>=1))||((WantSection_1_F>=1)&&(Idle_1>=1)))||((WantSection_2_F>=1)&&(Idle_2>=1)))||((WantSection_0_F>=1)&&(Idle_0>=1)))"))
Formula 0 simplified : !"(((((WantSection_3_F>=1)&&(Idle_3>=1))||((WantSection_1_F>=1)&&(Idle_1>=1)))||((WantSection_2_F>=1)&&(Idle_2>=1)))||((WantSection_0_F>=1)&&(Idle_0>=1)))"
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 308
// Phase 1: matrix 308 rows 244 cols
invariant :Turn_2_1 + Turn_2_2 + Turn_2_0 + Turn_2_3 = 1
invariant :WantSection_3_F + -1'Idle_3 = 0
invariant :WantSection_2_F + -1'Idle_2 = 0
invariant :WantSection_1_T + Idle_1 = 1
invariant :IsEndLoop_0_0_0 + IsEndLoop_0_1_0 + IsEndLoop_0_2_0 + IsEndLoop_0_0_1 + IsEndLoop_0_1_1 + IsEndLoop_0_2_1 + IsEndLoop_0_0_2 + IsEndLoop_0_1_2 + IsEndLoop_0_2_2 + IsEndLoop_0_0_3 + IsEndLoop_0_1_3 + IsEndLoop_0_2_3 + EndTurn_0_0 + EndTurn_0_1 + EndTurn_0_2 + BeginLoop_0_0_0 + BeginLoop_0_2_0 + BeginLoop_0_1_0 + BeginLoop_0_1_1 + BeginLoop_0_0_1 + BeginLoop_0_0_2 + BeginLoop_0_2_1 + BeginLoop_0_2_2 + BeginLoop_0_1_2 + BeginLoop_0_1_3 + BeginLoop_0_0_3 + BeginLoop_0_2_3 + TestAlone_0_0_2 + TestAlone_0_1_2 + TestAlone_0_2_2 + TestAlone_0_0_1 + TestAlone_0_1_1 + TestAlone_0_2_1 + TestAlone_0_2_3 + TestTurn_0_0 + TestTurn_0_1 + TestAlone_0_0_3 + TestAlone_0_1_3 + TestIdentity_0_1_0 + TestIdentity_0_2_0 + TestTurn_0_2 + TestIdentity_0_0_0 + TestIdentity_0_2_1 + TestIdentity_0_0_2 + TestIdentity_0_0_1 + TestIdentity_0_1_1 + TestIdentity_0_1_3 + TestIdentity_0_0_3 + TestIdentity_0_2_2 + TestIdentity_0_1_2 + TestIdentity_0_2_3 + AskForSection_0_2 + AskForSection_0_1 + AskForSection_0_0 + Idle_0 + CS_0 = 1
invariant :Turn_1_2 + Turn_1_0 + Turn_1_1 + Turn_1_3 = 1
invariant :WantSection_3_T + Idle_3 = 1
invariant :IsEndLoop_2_0_0 + IsEndLoop_2_1_0 + IsEndLoop_2_2_0 + IsEndLoop_2_0_1 + IsEndLoop_2_1_1 + IsEndLoop_2_2_1 + IsEndLoop_2_0_2 + IsEndLoop_2_1_2 + IsEndLoop_2_2_2 + IsEndLoop_2_0_3 + IsEndLoop_2_1_3 + IsEndLoop_2_2_3 + EndTurn_2_0 + EndTurn_2_1 + EndTurn_2_2 + BeginLoop_2_1_0 + BeginLoop_2_0_0 + BeginLoop_2_0_1 + BeginLoop_2_2_0 + BeginLoop_2_2_1 + BeginLoop_2_1_1 + BeginLoop_2_1_2 + BeginLoop_2_0_2 + BeginLoop_2_0_3 + BeginLoop_2_2_2 + BeginLoop_2_2_3 + BeginLoop_2_1_3 + TestAlone_2_2_0 + TestAlone_2_1_0 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_1_1 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestTurn_2_0 + TestAlone_2_0_3 + TestAlone_2_1_3 + TestIdentity_2_0_0 + TestIdentity_2_1_0 + TestTurn_2_1 + TestTurn_2_2 + TestIdentity_2_1_1 + TestIdentity_2_2_1 + TestIdentity_2_2_0 + TestIdentity_2_0_1 + TestIdentity_2_0_3 + TestIdentity_2_2_2 + TestIdentity_2_1_2 + TestIdentity_2_0_2 + TestIdentity_2_2_3 + TestIdentity_2_1_3 + AskForSection_2_1 + AskForSection_2_0 + Idle_2 + CS_2 + AskForSection_2_2 = 1
invariant :Turn_0_2 + Turn_0_1 + Turn_0_0 + Turn_0_3 = 1
invariant :IsEndLoop_3_0_0 + IsEndLoop_3_1_0 + IsEndLoop_3_2_0 + IsEndLoop_3_0_1 + IsEndLoop_3_1_1 + IsEndLoop_3_2_1 + IsEndLoop_3_0_2 + IsEndLoop_3_1_2 + IsEndLoop_3_2_2 + IsEndLoop_3_0_3 + IsEndLoop_3_1_3 + IsEndLoop_3_2_3 + EndTurn_3_0 + EndTurn_3_1 + EndTurn_3_2 + BeginLoop_3_1_0 + BeginLoop_3_0_0 + BeginLoop_3_0_1 + BeginLoop_3_2_0 + BeginLoop_3_2_1 + BeginLoop_3_1_1 + BeginLoop_3_1_2 + BeginLoop_3_0_2 + BeginLoop_3_0_3 + BeginLoop_3_2_2 + BeginLoop_3_2_3 + BeginLoop_3_1_3 + TestAlone_3_2_0 + TestAlone_3_1_0 + TestAlone_3_0_0 + TestAlone_3_2_1 + TestAlone_3_0_2 + TestAlone_3_1_2 + TestAlone_3_0_1 + TestAlone_3_1_1 + TestTurn_3_0 + TestAlone_3_2_2 + TestIdentity_3_0_0 + TestIdentity_3_1_0 + TestTurn_3_1 + TestTurn_3_2 + TestIdentity_3_1_1 + TestIdentity_3_2_1 + TestIdentity_3_2_0 + TestIdentity_3_0_1 + TestIdentity_3_0_3 + TestIdentity_3_2_2 + TestIdentity_3_1_2 + TestIdentity_3_0_2 + TestIdentity_3_2_3 + TestIdentity_3_1_3 + AskForSection_3_1 + AskForSection_3_0 + Idle_3 + CS_3 + AskForSection_3_2 = 1
invariant :IsEndLoop_1_0_0 + IsEndLoop_1_1_0 + IsEndLoop_1_2_0 + IsEndLoop_1_0_1 + IsEndLoop_1_1_1 + IsEndLoop_1_2_1 + IsEndLoop_1_0_2 + IsEndLoop_1_1_2 + IsEndLoop_1_2_2 + IsEndLoop_1_0_3 + IsEndLoop_1_1_3 + IsEndLoop_1_2_3 + EndTurn_1_0 + EndTurn_1_1 + EndTurn_1_2 + BeginLoop_1_1_0 + BeginLoop_1_0_0 + BeginLoop_1_0_1 + BeginLoop_1_2_0 + BeginLoop_1_2_1 + BeginLoop_1_1_1 + BeginLoop_1_1_2 + BeginLoop_1_0_2 + BeginLoop_1_0_3 + BeginLoop_1_2_2 + BeginLoop_1_2_3 + BeginLoop_1_1_3 + TestAlone_1_0_0 + TestAlone_1_2_0 + TestAlone_1_1_0 + TestAlone_1_0_2 + TestAlone_1_1_2 + TestAlone_1_2_3 + TestTurn_1_0 + TestAlone_1_2_2 + TestAlone_1_0_3 + TestAlone_1_1_3 + TestIdentity_1_0_0 + TestIdentity_1_1_0 + TestTurn_1_1 + TestTurn_1_2 + TestIdentity_1_1_1 + TestIdentity_1_2_1 + TestIdentity_1_2_0 + TestIdentity_1_0_1 + TestIdentity_1_0_3 + TestIdentity_1_2_2 + TestIdentity_1_1_2 + TestIdentity_1_0_2 + TestIdentity_1_2_3 + TestIdentity_1_1_3 + AskForSection_1_1 + AskForSection_1_0 + Idle_1 + CS_1 + AskForSection_1_2 = 1
invariant :WantSection_0_F + -1'Idle_0 = 0
invariant :WantSection_2_T + Idle_2 = 1
invariant :WantSection_0_T + Idle_0 = 1
invariant :WantSection_1_F + -1'Idle_1 = 0
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Reverse transition relation is NOT exact ! Due to transitions BecomeIdle_0, UpdateTurn_1_3_2, UpdateTurn_2_3_2, UpdateTurn_3_3_2, BecomeIdle_1, BecomeIdle_2, BecomeIdle_3, EndLoop_3_1, EndLoop_1_1, EndLoop_2_1, EndLoop_3_0, EndLoop_0_1, EndLoop_1_0, EndLoop_2_0, EndLoop_0_0, NotAlone_2_3_0, NotAlone_1_3_0, NotAlone_0_3_0, NotAlone_3_2_0, NotAlone_1_2_0, NotAlone_0_2_0, NotAlone_3_1_0, NotAlone_3_2_1, NotAlone_1_2_1, NotAlone_0_2_1, NotAlone_3_1_1, NotAlone_2_1_1, NotAlone_2_1_0, NotAlone_2_1_2, NotAlone_0_3_1, NotAlone_1_3_1, NotAlone_2_3_1, NotAlone_0_3_2, NotAlone_1_3_2, NotAlone_2_3_2, NotAlone_3_1_2, NotAlone_0_2_2, NotAlone_1_2_2, NotAlone_3_2_2, UpdateTurn_3_2_0, UpdateTurn_0_3_0, UpdateTurn_1_2_0, UpdateTurn_2_2_0, UpdateTurn_3_1_0, UpdateTurn_0_2_0, UpdateTurn_1_1_0, UpdateTurn_2_1_0, UpdateTurn_3_0_0, UpdateTurn_0_1_0, UpdateTurn_1_0_0, UpdateTurn_2_0_0, UpdateTurn_0_0_0, UpdateTurn_1_2_2, UpdateTurn_2_2_2, UpdateTurn_3_2_2, UpdateTurn_0_3_2, UpdateTurn_1_1_2, UpdateTurn_2_1_2, UpdateTurn_3_1_2, UpdateTurn_0_2_2, UpdateTurn_1_0_2, UpdateTurn_2_0_2, UpdateTurn_3_0_2, UpdateTurn_0_1_2, UpdateTurn_1_3_1, UpdateTurn_2_3_1, UpdateTurn_3_3_1, UpdateTurn_0_0_2, UpdateTurn_2_2_1, UpdateTurn_1_2_1, UpdateTurn_0_3_1, UpdateTurn_3_2_1, UpdateTurn_2_1_1, UpdateTurn_1_1_1, UpdateTurn_0_2_1, UpdateTurn_3_1_1, UpdateTurn_2_0_1, UpdateTurn_1_0_1, UpdateTurn_0_1_1, UpdateTurn_3_0_1, UpdateTurn_2_3_0, UpdateTurn_1_3_0, UpdateTurn_0_0_1, UpdateTurn_3_3_0, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :0/248/84/332
Compilation finished in 4849 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 82 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP0==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
1 unique states visited
0 strongly connected components in search stack
0 transitions explored
1 items max in DFS search stack
7571 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,75.7738,1339124,1,0,660,5.67165e+06,684,335,7546,5.05016e+06,672
no accepting run found
Formula 0 is TRUE no accepting run found.
FORMULA Peterson-PT-3-LTLFireability-00 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 1 : !((("((((((((((((TestIdentity_0_0_0>=1)||(TestIdentity_3_1_3>=1))||(TestIdentity_0_2_0>=1))||(TestIdentity_1_1_1>=1))||(TestIdentity_2_1_2>=1))||(TestIdentity_3_0_3>=1))||(TestIdentity_0_1_0>=1))||(TestIdentity_1_0_1>=1))||(TestIdentity_2_0_2>=1))||(TestIdentity_3_2_3>=1))||(TestIdentity_2_2_2>=1))||(TestIdentity_1_2_1>=1))")U(X(("((((((((((((TestIdentity_0_0_0>=1)||(TestIdentity_3_1_3>=1))||(TestIdentity_0_2_0>=1))||(TestIdentity_1_1_1>=1))||(TestIdentity_2_1_2>=1))||(TestIdentity_3_0_3>=1))||(TestIdentity_0_1_0>=1))||(TestIdentity_1_0_1>=1))||(TestIdentity_2_0_2>=1))||(TestIdentity_3_2_3>=1))||(TestIdentity_2_2_2>=1))||(TestIdentity_1_2_1>=1))")U("((((((((((((((((((((((((((((((((((((IsEndLoop_0_1_1>=1)||(IsEndLoop_3_1_0>=1))||(IsEndLoop_2_1_0>=1))||(IsEndLoop_1_1_0>=1))||(IsEndLoop_0_1_2>=1))||(IsEndLoop_3_1_1>=1))||(IsEndLoop_2_1_1>=1))||(IsEndLoop_1_1_1>=1))||(IsEndLoop_0_2_0>=1))||(IsEndLoop_3_1_2>=1))||(IsEndLoop_2_1_2>=1))||(IsEndLoop_1_1_2>=1))||(IsEndLoop_0_2_1>=1))||(IsEndLoop_3_2_0>=1))||(IsEndLoop_2_2_0>=1))||(IsEndLoop_1_2_0>=1))||(IsEndLoop_0_0_0>=1))||(IsEndLoop_3_0_0>=1))||(IsEndLoop_0_0_1>=1))||(IsEndLoop_1_0_0>=1))||(IsEndLoop_2_0_0>=1))||(IsEndLoop_3_0_1>=1))||(IsEndLoop_0_0_2>=1))||(IsEndLoop_1_0_1>=1))||(IsEndLoop_2_0_1>=1))||(IsEndLoop_3_0_2>=1))||(IsEndLoop_0_1_0>=1))||(IsEndLoop_1_0_2>=1))||(IsEndLoop_2_0_2>=1))||(IsEndLoop_1_2_1>=1))||(IsEndLoop_2_2_1>=1))||(IsEndLoop_3_2_1>=1))||(IsEndLoop_0_2_2>=1))||(IsEndLoop_1_2_2>=1))||(IsEndLoop_2_2_2>=1))||(IsEndLoop_3_2_2>=1))")))))
Formula 1 simplified : !("((((((((((((TestIdentity_0_0_0>=1)||(TestIdentity_3_1_3>=1))||(TestIdentity_0_2_0>=1))||(TestIdentity_1_1_1>=1))||(TestIdentity_2_1_2>=1))||(TestIdentity_3_0_3>=1))||(TestIdentity_0_1_0>=1))||(TestIdentity_1_0_1>=1))||(TestIdentity_2_0_2>=1))||(TestIdentity_3_2_3>=1))||(TestIdentity_2_2_2>=1))||(TestIdentity_1_2_1>=1))" U X("((((((((((((TestIdentity_0_0_0>=1)||(TestIdentity_3_1_3>=1))||(TestIdentity_0_2_0>=1))||(TestIdentity_1_1_1>=1))||(TestIdentity_2_1_2>=1))||(TestIdentity_3_0_3>=1))||(TestIdentity_0_1_0>=1))||(TestIdentity_1_0_1>=1))||(TestIdentity_2_0_2>=1))||(TestIdentity_3_2_3>=1))||(TestIdentity_2_2_2>=1))||(TestIdentity_1_2_1>=1))" U "((((((((((((((((((((((((((((((((((((IsEndLoop_0_1_1>=1)||(IsEndLoop_3_1_0>=1))||(IsEndLoop_2_1_0>=1))||(IsEndLoop_1_1_0>=1))||(IsEndLoop_0_1_2>=1))||(IsEndLoop_3_1_1>=1))||(IsEndLoop_2_1_1>=1))||(IsEndLoop_1_1_1>=1))||(IsEndLoop_0_2_0>=1))||(IsEndLoop_3_1_2>=1))||(IsEndLoop_2_1_2>=1))||(IsEndLoop_1_1_2>=1))||(IsEndLoop_0_2_1>=1))||(IsEndLoop_3_2_0>=1))||(IsEndLoop_2_2_0>=1))||(IsEndLoop_1_2_0>=1))||(IsEndLoop_0_0_0>=1))||(IsEndLoop_3_0_0>=1))||(IsEndLoop_0_0_1>=1))||(IsEndLoop_1_0_0>=1))||(IsEndLoop_2_0_0>=1))||(IsEndLoop_3_0_1>=1))||(IsEndLoop_0_0_2>=1))||(IsEndLoop_1_0_1>=1))||(IsEndLoop_2_0_1>=1))||(IsEndLoop_3_0_2>=1))||(IsEndLoop_0_1_0>=1))||(IsEndLoop_1_0_2>=1))||(IsEndLoop_2_0_2>=1))||(IsEndLoop_1_2_1>=1))||(IsEndLoop_2_2_1>=1))||(IsEndLoop_3_2_1>=1))||(IsEndLoop_0_2_2>=1))||(IsEndLoop_1_2_2>=1))||(IsEndLoop_2_2_2>=1))||(IsEndLoop_3_2_2>=1))"))
LTSmin run took 248 ms.
FORMULA Peterson-PT-3-LTLFireability-00 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ((LTLAP1==true))U(X(((LTLAP1==true))U((LTLAP2==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 55 ms.
FORMULA Peterson-PT-3-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(<>((LTLAP3==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 849 ms.
FORMULA Peterson-PT-3-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>([]([](X(<>((LTLAP4==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 38 ms.
FORMULA Peterson-PT-3-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((((LTLAP2==true))U((LTLAP5==true)))U([]((LTLAP6==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 176 ms.
FORMULA Peterson-PT-3-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(([](X((LTLAP7==true))))U(X(<>((LTLAP5==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 38 ms.
FORMULA Peterson-PT-3-LTLFireability-05 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(<>(<>(X([]((LTLAP8==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 28 ms.
FORMULA Peterson-PT-3-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](X((<>((LTLAP9==true)))U([]((LTLAP10==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 20 ms.
FORMULA Peterson-PT-3-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (<>(<>(X((LTLAP11==true)))))U(<>(((LTLAP12==true))U((LTLAP13==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 67 ms.
FORMULA Peterson-PT-3-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP14==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 171 ms.
FORMULA Peterson-PT-3-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>((X(<>((LTLAP15==true))))U(X((LTLAP16==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 57 ms.
FORMULA Peterson-PT-3-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X(<>((LTLAP17==true))))U((LTLAP18==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 32 ms.
FORMULA Peterson-PT-3-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP19==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 185 ms.
FORMULA Peterson-PT-3-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, []([](([]((LTLAP20==true)))U(X((LTLAP21==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 100 ms.
FORMULA Peterson-PT-3-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([](X(X(<>((LTLAP22==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 49 ms.
FORMULA Peterson-PT-3-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>((X((LTLAP23==true)))U(X((LTLAP24==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 52 ms.
FORMULA Peterson-PT-3-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1527489635096

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 28, 2018 6:39:15 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 28, 2018 6:39:15 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 28, 2018 6:39:16 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 76 ms
May 28, 2018 6:39:16 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 244 places.
May 28, 2018 6:39:16 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 332 transitions.
May 28, 2018 6:39:16 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 28 ms
May 28, 2018 6:39:16 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 86 ms
May 28, 2018 6:39:16 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 6 ms
May 28, 2018 6:39:16 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 11 ms
May 28, 2018 6:39:16 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 332 transitions.
May 28, 2018 6:39:17 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 15 place invariants in 73 ms
May 28, 2018 6:39:17 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 244 variables to be positive in 450 ms
May 28, 2018 6:39:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 332 transitions.
May 28, 2018 6:39:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/332 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 6:39:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 25 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 6:39:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 332 transitions.
May 28, 2018 6:39:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 22 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 6:39:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 332 transitions.
May 28, 2018 6:39:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/332) took 81 ms. Total solver calls (SAT/UNSAT): 82(0/82)
May 28, 2018 6:39:30 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(31/332) took 3318 ms. Total solver calls (SAT/UNSAT): 2520(9/2511)
May 28, 2018 6:39:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(42/332) took 6852 ms. Total solver calls (SAT/UNSAT): 3394(24/3370)
May 28, 2018 6:39:37 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(66/332) took 10255 ms. Total solver calls (SAT/UNSAT): 5071(51/5020)
May 28, 2018 6:39:40 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(81/332) took 13777 ms. Total solver calls (SAT/UNSAT): 6029(51/5978)
May 28, 2018 6:39:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(99/332) took 17347 ms. Total solver calls (SAT/UNSAT): 7105(51/7054)
May 28, 2018 6:39:47 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(111/332) took 20508 ms. Total solver calls (SAT/UNSAT): 7801(80/7721)
May 28, 2018 6:39:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(119/332) took 23731 ms. Total solver calls (SAT/UNSAT): 8277(135/8142)
May 28, 2018 6:39:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(127/332) took 26931 ms. Total solver calls (SAT/UNSAT): 8705(156/8549)
May 28, 2018 6:39:56 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(138/332) took 30119 ms. Total solver calls (SAT/UNSAT): 9276(195/9081)
May 28, 2018 6:40:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(147/332) took 33467 ms. Total solver calls (SAT/UNSAT): 9747(241/9506)
May 28, 2018 6:40:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(158/332) took 36615 ms. Total solver calls (SAT/UNSAT): 10276(283/9993)
May 28, 2018 6:40:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(166/332) took 39755 ms. Total solver calls (SAT/UNSAT): 10634(304/10330)
May 28, 2018 6:40:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(184/332) took 43689 ms. Total solver calls (SAT/UNSAT): 11340(318/11022)
May 28, 2018 6:40:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(214/332) took 46960 ms. Total solver calls (SAT/UNSAT): 12375(345/12030)
May 28, 2018 6:40:16 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(245/332) took 50153 ms. Total solver calls (SAT/UNSAT): 13344(398/12946)
May 28, 2018 6:40:19 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(256/332) took 53181 ms. Total solver calls (SAT/UNSAT): 13780(452/13328)
May 28, 2018 6:40:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(276/332) took 56236 ms. Total solver calls (SAT/UNSAT): 14391(529/13862)
May 28, 2018 6:40:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(316/332) took 59299 ms. Total solver calls (SAT/UNSAT): 15011(594/14417)
May 28, 2018 6:40:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 60489 ms. Total solver calls (SAT/UNSAT): 15088(612/14476)
May 28, 2018 6:40:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 332 transitions.
May 28, 2018 6:40:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 270 ms. Total solver calls (SAT/UNSAT): 36(0/36)
May 28, 2018 6:40:27 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 70799ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Peterson-PT-3"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/Peterson-PT-3.tgz
mv Peterson-PT-3 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is Peterson-PT-3, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r260-csrt-152732585400162"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;