Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.................................
/home/mcc/execution
total 456K
-rw-r--r-- 1 mcc users 7.6K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 34K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 28K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 4.2K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.2K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 32K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 112 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 350 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 17K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.6K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 6.1K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 2 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 152K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is LamportFastMutEx-PT-5, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r260-csrt-152732585200038
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-PT-5-LTLFireability-00
FORMULA_NAME LamportFastMutEx-PT-5-LTLFireability-01
FORMULA_NAME LamportFastMutEx-PT-5-LTLFireability-02
FORMULA_NAME LamportFastMutEx-PT-5-LTLFireability-03
FORMULA_NAME LamportFastMutEx-PT-5-LTLFireability-04
FORMULA_NAME LamportFastMutEx-PT-5-LTLFireability-05
FORMULA_NAME LamportFastMutEx-PT-5-LTLFireability-06
FORMULA_NAME LamportFastMutEx-PT-5-LTLFireability-07
FORMULA_NAME LamportFastMutEx-PT-5-LTLFireability-08
FORMULA_NAME LamportFastMutEx-PT-5-LTLFireability-09
FORMULA_NAME LamportFastMutEx-PT-5-LTLFireability-10
FORMULA_NAME LamportFastMutEx-PT-5-LTLFireability-11
FORMULA_NAME LamportFastMutEx-PT-5-LTLFireability-12
FORMULA_NAME LamportFastMutEx-PT-5-LTLFireability-13
FORMULA_NAME LamportFastMutEx-PT-5-LTLFireability-14
FORMULA_NAME LamportFastMutEx-PT-5-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527484380250

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((F("((((((((((((((((((((((((((((((((((((((P_b_0_false>=1)&&(P_wait_0_0>=1))&&(P_await_13_0>=1))||(((P_b_1_false>=1)&&(P_wait_0_1>=1))&&(P_await_13_0>=1)))||(((P_b_2_false>=1)&&(P_wait_0_2>=1))&&(P_await_13_0>=1)))||(((P_b_3_false>=1)&&(P_wait_0_3>=1))&&(P_await_13_0>=1)))||(((P_b_4_false>=1)&&(P_wait_0_4>=1))&&(P_await_13_0>=1)))||(((P_b_5_false>=1)&&(P_wait_0_5>=1))&&(P_await_13_0>=1)))||(((P_b_0_false>=1)&&(P_wait_1_0>=1))&&(P_await_13_1>=1)))||(((P_b_1_false>=1)&&(P_wait_1_1>=1))&&(P_await_13_1>=1)))||(((P_b_2_false>=1)&&(P_wait_1_2>=1))&&(P_await_13_1>=1)))||(((P_b_3_false>=1)&&(P_wait_1_3>=1))&&(P_await_13_1>=1)))||(((P_b_4_false>=1)&&(P_wait_1_4>=1))&&(P_await_13_1>=1)))||(((P_b_5_false>=1)&&(P_wait_1_5>=1))&&(P_await_13_1>=1)))||(((P_b_0_false>=1)&&(P_wait_2_0>=1))&&(P_await_13_2>=1)))||(((P_b_1_false>=1)&&(P_wait_2_1>=1))&&(P_await_13_2>=1)))||(((P_b_2_false>=1)&&(P_wait_2_2>=1))&&(P_await_13_2>=1)))||(((P_b_3_false>=1)&&(P_wait_2_3>=1))&&(P_await_13_2>=1)))||(((P_b_4_false>=1)&&(P_wait_2_4>=1))&&(P_await_13_2>=1)))||(((P_b_5_false>=1)&&(P_wait_2_5>=1))&&(P_await_13_2>=1)))||(((P_b_0_false>=1)&&(P_wait_3_0>=1))&&(P_await_13_3>=1)))||(((P_b_1_false>=1)&&(P_wait_3_1>=1))&&(P_await_13_3>=1)))||(((P_b_2_false>=1)&&(P_wait_3_2>=1))&&(P_await_13_3>=1)))||(((P_b_3_false>=1)&&(P_wait_3_3>=1))&&(P_await_13_3>=1)))||(((P_b_4_false>=1)&&(P_wait_3_4>=1))&&(P_await_13_3>=1)))||(((P_b_5_false>=1)&&(P_wait_3_5>=1))&&(P_await_13_3>=1)))||(((P_b_0_false>=1)&&(P_wait_4_0>=1))&&(P_await_13_4>=1)))||(((P_b_1_false>=1)&&(P_wait_4_1>=1))&&(P_await_13_4>=1)))||(((P_b_2_false>=1)&&(P_wait_4_2>=1))&&(P_await_13_4>=1)))||(((P_b_3_false>=1)&&(P_wait_4_3>=1))&&(P_await_13_4>=1)))||(((P_b_4_false>=1)&&(P_wait_4_4>=1))&&(P_await_13_4>=1)))||(((P_b_5_false>=1)&&(P_wait_4_5>=1))&&(P_await_13_4>=1)))||(((P_b_0_false>=1)&&(P_wait_5_0>=1))&&(P_await_13_5>=1)))||(((P_b_1_false>=1)&&(P_wait_5_1>=1))&&(P_await_13_5>=1)))||(((P_b_2_false>=1)&&(P_wait_5_2>=1))&&(P_await_13_5>=1)))||(((P_b_3_false>=1)&&(P_wait_5_3>=1))&&(P_await_13_5>=1)))||(((P_b_4_false>=1)&&(P_wait_5_4>=1))&&(P_await_13_5>=1)))||(((P_b_5_false>=1)&&(P_wait_5_5>=1))&&(P_await_13_5>=1)))")))
Formula 0 simplified : !F"((((((((((((((((((((((((((((((((((((((P_b_0_false>=1)&&(P_wait_0_0>=1))&&(P_await_13_0>=1))||(((P_b_1_false>=1)&&(P_wait_0_1>=1))&&(P_await_13_0>=1)))||(((P_b_2_false>=1)&&(P_wait_0_2>=1))&&(P_await_13_0>=1)))||(((P_b_3_false>=1)&&(P_wait_0_3>=1))&&(P_await_13_0>=1)))||(((P_b_4_false>=1)&&(P_wait_0_4>=1))&&(P_await_13_0>=1)))||(((P_b_5_false>=1)&&(P_wait_0_5>=1))&&(P_await_13_0>=1)))||(((P_b_0_false>=1)&&(P_wait_1_0>=1))&&(P_await_13_1>=1)))||(((P_b_1_false>=1)&&(P_wait_1_1>=1))&&(P_await_13_1>=1)))||(((P_b_2_false>=1)&&(P_wait_1_2>=1))&&(P_await_13_1>=1)))||(((P_b_3_false>=1)&&(P_wait_1_3>=1))&&(P_await_13_1>=1)))||(((P_b_4_false>=1)&&(P_wait_1_4>=1))&&(P_await_13_1>=1)))||(((P_b_5_false>=1)&&(P_wait_1_5>=1))&&(P_await_13_1>=1)))||(((P_b_0_false>=1)&&(P_wait_2_0>=1))&&(P_await_13_2>=1)))||(((P_b_1_false>=1)&&(P_wait_2_1>=1))&&(P_await_13_2>=1)))||(((P_b_2_false>=1)&&(P_wait_2_2>=1))&&(P_await_13_2>=1)))||(((P_b_3_false>=1)&&(P_wait_2_3>=1))&&(P_await_13_2>=1)))||(((P_b_4_false>=1)&&(P_wait_2_4>=1))&&(P_await_13_2>=1)))||(((P_b_5_false>=1)&&(P_wait_2_5>=1))&&(P_await_13_2>=1)))||(((P_b_0_false>=1)&&(P_wait_3_0>=1))&&(P_await_13_3>=1)))||(((P_b_1_false>=1)&&(P_wait_3_1>=1))&&(P_await_13_3>=1)))||(((P_b_2_false>=1)&&(P_wait_3_2>=1))&&(P_await_13_3>=1)))||(((P_b_3_false>=1)&&(P_wait_3_3>=1))&&(P_await_13_3>=1)))||(((P_b_4_false>=1)&&(P_wait_3_4>=1))&&(P_await_13_3>=1)))||(((P_b_5_false>=1)&&(P_wait_3_5>=1))&&(P_await_13_3>=1)))||(((P_b_0_false>=1)&&(P_wait_4_0>=1))&&(P_await_13_4>=1)))||(((P_b_1_false>=1)&&(P_wait_4_1>=1))&&(P_await_13_4>=1)))||(((P_b_2_false>=1)&&(P_wait_4_2>=1))&&(P_await_13_4>=1)))||(((P_b_3_false>=1)&&(P_wait_4_3>=1))&&(P_await_13_4>=1)))||(((P_b_4_false>=1)&&(P_wait_4_4>=1))&&(P_await_13_4>=1)))||(((P_b_5_false>=1)&&(P_wait_4_5>=1))&&(P_await_13_4>=1)))||(((P_b_0_false>=1)&&(P_wait_5_0>=1))&&(P_await_13_5>=1)))||(((P_b_1_false>=1)&&(P_wait_5_1>=1))&&(P_await_13_5>=1)))||(((P_b_2_false>=1)&&(P_wait_5_2>=1))&&(P_await_13_5>=1)))||(((P_b_3_false>=1)&&(P_wait_5_3>=1))&&(P_await_13_5>=1)))||(((P_b_4_false>=1)&&(P_wait_5_4>=1))&&(P_await_13_5>=1)))||(((P_b_5_false>=1)&&(P_wait_5_5>=1))&&(P_await_13_5>=1)))"
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 246
// Phase 1: matrix 246 rows 174 cols
invariant :P_start_1_1 + P_setx_3_1 + P_setbi_5_1 + P_ify0_4_1 + P_sety_9_1 + P_ifxi_10_1 + P_setbi_11_1 + P_fordo_12_1 + P_await_13_1 + P_ifyi_15_1 + P_awaity_1 + P_CS_21_1 + P_setbi_24_1 = 1
invariant :P_wait_1_5 + -1'P_await_13_1 + P_done_1_5 = 0
invariant :P_wait_1_0 + P_done_1_0 = 0
invariant :P_wait_1_3 + -1'P_await_13_1 + P_done_1_3 = 0
invariant :P_wait_2_1 + -1'P_await_13_2 + P_done_2_1 = 0
invariant :P_wait_5_5 + -1'P_await_13_5 + P_done_5_5 = 0
invariant :P_wait_3_5 + -1'P_await_13_3 + P_done_3_5 = 0
invariant :P_wait_0_5 + -1'P_await_13_0 + P_done_0_5 = 0
invariant :P_wait_4_1 + -1'P_await_13_4 + P_done_4_1 = 0
invariant :P_wait_5_1 + -1'P_await_13_5 + P_done_5_1 = 0
invariant :P_wait_1_4 + -1'P_await_13_1 + P_done_1_4 = 0
invariant :y_0 + y_1 + y_2 + y_3 + y_4 + y_5 = 1
invariant :P_b_1_false + P_b_1_true = 1
invariant :P_wait_2_4 + -1'P_await_13_2 + P_done_2_4 = 0
invariant :P_wait_3_2 + -1'P_await_13_3 + P_done_3_2 = 0
invariant :P_wait_4_2 + -1'P_await_13_4 + P_done_4_2 = 0
invariant :P_wait_4_5 + -1'P_await_13_4 + P_done_4_5 = 0
invariant :P_start_1_5 + P_setx_3_5 + P_setbi_5_5 + P_ify0_4_5 + P_sety_9_5 + P_ifxi_10_5 + P_setbi_11_5 + P_fordo_12_5 + P_await_13_5 + P_ifyi_15_5 + P_awaity_5 + P_CS_21_5 + P_setbi_24_5 = 1
invariant :P_wait_5_0 + P_done_5_0 = 0
invariant :P_wait_3_4 + -1'P_await_13_3 + P_done_3_4 = 0
invariant :P_start_1_4 + P_setx_3_4 + P_setbi_5_4 + P_ify0_4_4 + P_sety_9_4 + P_ifxi_10_4 + P_setbi_11_4 + P_fordo_12_4 + P_await_13_4 + P_ifyi_15_4 + P_awaity_4 + P_CS_21_4 + P_setbi_24_4 = 1
invariant :P_wait_4_3 + -1'P_await_13_4 + P_done_4_3 = 0
invariant :P_wait_3_3 + -1'P_await_13_3 + P_done_3_3 = 0
invariant :P_wait_5_3 + -1'P_await_13_5 + P_done_5_3 = 0
invariant :x_0 + x_1 + x_2 + x_3 + x_4 + x_5 = 1
invariant :P_wait_0_1 + -1'P_await_13_0 + P_done_0_1 = 0
invariant :P_start_1_2 + P_setx_3_2 + P_setbi_5_2 + P_ify0_4_2 + P_sety_9_2 + P_ifxi_10_2 + P_setbi_11_2 + P_fordo_12_2 + P_await_13_2 + P_ifyi_15_2 + P_awaity_2 + P_CS_21_2 + P_setbi_24_2 = 1
invariant :P_wait_2_5 + -1'P_await_13_2 + P_done_2_5 = 0
invariant :P_wait_3_0 + P_done_3_0 = 0
invariant :P_start_1_3 + P_setx_3_3 + P_setbi_5_3 + P_ify0_4_3 + P_sety_9_3 + P_ifxi_10_3 + P_setbi_11_3 + P_fordo_12_3 + P_await_13_3 + P_ifyi_15_3 + P_awaity_3 + P_CS_21_3 + P_setbi_24_3 = 1
invariant :P_b_2_false + P_b_2_true = 1
invariant :P_wait_0_0 + P_done_0_0 = 0
invariant :P_b_5_false + P_b_5_true = 1
invariant :P_wait_1_2 + -1'P_await_13_1 + P_done_1_2 = 0
invariant :P_wait_1_1 + -1'P_await_13_1 + P_done_1_1 = 0
invariant :P_start_1_0 + P_setx_3_0 + P_setbi_5_0 + P_ify0_4_0 + P_sety_9_0 + P_ifxi_10_0 + P_setbi_11_0 + P_fordo_12_0 + P_await_13_0 + P_ifyi_15_0 + P_awaity_0 + P_CS_21_0 + P_setbi_24_0 = 0
invariant :P_wait_0_3 + -1'P_await_13_0 + P_done_0_3 = 0
invariant :P_wait_4_4 + -1'P_await_13_4 + P_done_4_4 = 0
invariant :P_wait_5_4 + -1'P_await_13_5 + P_done_5_4 = 0
invariant :P_b_4_false + P_b_4_true = 1
invariant :P_wait_3_1 + -1'P_await_13_3 + P_done_3_1 = 0
invariant :P_wait_2_2 + -1'P_await_13_2 + P_done_2_2 = 0
invariant :P_wait_4_0 + P_done_4_0 = 0
invariant :P_wait_0_4 + -1'P_await_13_0 + P_done_0_4 = 0
invariant :P_wait_5_2 + -1'P_await_13_5 + P_done_5_2 = 0
invariant :P_wait_2_0 + P_done_2_0 = 0
invariant :P_b_3_false + P_b_3_true = 1
invariant :P_b_0_false + P_b_0_true = 0
invariant :P_wait_0_2 + -1'P_await_13_0 + P_done_0_2 = 0
invariant :P_wait_2_3 + -1'P_await_13_2 + P_done_2_3 = 0
Reverse transition relation is NOT exact ! Due to transitions T_setx_3_7, T_setx_3_8, T_setx_3_9, T_setx_3_10, T_setx_3_11, T_setx_3_12, T_setx_3_13, T_setx_3_14, T_setx_3_15, T_setx_3_16, T_setx_3_17, T_setx_3_18, T_setx_3_19, T_setx_3_20, T_setx_3_21, T_setx_3_22, T_setx_3_23, T_setx_3_24, T_setx_3_25, T_setx_3_26, T_setx_3_27, T_setx_3_28, T_setx_3_29, T_setx_3_30, T_setx_3_31, T_setx_3_32, T_setx_3_33, T_setx_3_34, T_setx_3_35, T_setx_3_36, T_setbi_5_4, T_setbi_5_6, T_setbi_5_8, T_setbi_5_10, T_setbi_5_12, T_awaity_2, T_awaity_3, T_awaity_4, T_awaity_5, T_awaity_6, T_sety_9_7, T_sety_9_9, T_sety_9_10, T_sety_9_11, T_sety_9_12, T_sety_9_13, T_sety_9_14, T_sety_9_16, T_sety_9_17, T_sety_9_18, T_sety_9_19, T_sety_9_20, T_sety_9_21, T_sety_9_23, T_sety_9_24, T_sety_9_25, T_sety_9_26, T_sety_9_27, T_sety_9_28, T_sety_9_30, T_sety_9_31, T_sety_9_32, T_sety_9_33, T_sety_9_34, T_sety_9_35, T_setbi_11_4, T_setbi_11_6, T_setbi_11_8, T_setbi_11_10, T_setbi_11_12, T_ynei_15_7, T_ynei_15_9, T_ynei_15_10, T_ynei_15_11, T_ynei_15_12, T_ynei_15_13, T_ynei_15_14, T_ynei_15_16, T_ynei_15_17, T_ynei_15_18, T_ynei_15_19, T_ynei_15_20, T_ynei_15_21, T_ynei_15_23, T_ynei_15_24, T_ynei_15_25, T_ynei_15_26, T_ynei_15_27, T_ynei_15_28, T_ynei_15_30, T_ynei_15_31, T_ynei_15_32, T_ynei_15_33, T_ynei_15_34, T_ynei_15_35, T_yeqi_15_8, T_yeqi_15_15, T_yeqi_15_22, T_yeqi_15_29, T_yeqi_15_36, T_sety0_23_8, T_sety0_23_9, T_sety0_23_10, T_sety0_23_11, T_sety0_23_12, T_sety0_23_14, T_sety0_23_15, T_sety0_23_16, T_sety0_23_17, T_sety0_23_18, T_sety0_23_20, T_sety0_23_21, T_sety0_23_22, T_sety0_23_23, T_sety0_23_24, T_sety0_23_26, T_sety0_23_27, T_sety0_23_28, T_sety0_23_29, T_sety0_23_30, T_sety0_23_32, T_sety0_23_33, T_sety0_23_34, T_sety0_23_35, T_sety0_23_36, T_setbi_24_3, T_setbi_24_4, T_setbi_24_5, T_setbi_24_6, T_setbi_24_7, T_setbi_24_8, T_setbi_24_9, T_setbi_24_10, T_setbi_24_11, T_setbi_24_12, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :93/90/135/318
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
2 unique states visited
2 strongly connected components in search stack
2 transitions explored
2 items max in DFS search stack
16250 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,162.556,2294440,1,0,597,7.93005e+06,17,229,2722,1.18364e+07,208
an accepting run exists (use option '-e' to print it)
Formula 0 is FALSE accepting run found.
FORMULA LamportFastMutEx-PT-5-LTLFireability-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Checking formula 1 : !(((G("((((((P_fordo_12_0>=1)||(P_fordo_12_1>=1))||(P_fordo_12_2>=1))||(P_fordo_12_3>=1))||(P_fordo_12_4>=1))||(P_fordo_12_5>=1))"))U(("(((((((((((((P_b_0_false>=1)&&(P_setbi_11_0>=1))||((P_b_0_true>=1)&&(P_setbi_11_0>=1)))||((P_b_1_false>=1)&&(P_setbi_11_1>=1)))||((P_b_1_true>=1)&&(P_setbi_11_1>=1)))||((P_b_2_false>=1)&&(P_setbi_11_2>=1)))||((P_b_2_true>=1)&&(P_setbi_11_2>=1)))||((P_b_3_false>=1)&&(P_setbi_11_3>=1)))||((P_b_3_true>=1)&&(P_setbi_11_3>=1)))||((P_b_4_false>=1)&&(P_setbi_11_4>=1)))||((P_b_4_true>=1)&&(P_setbi_11_4>=1)))||((P_b_5_false>=1)&&(P_setbi_11_5>=1)))||((P_b_5_true>=1)&&(P_setbi_11_5>=1)))")U(X("(((((((((((P_await_13_0>=1)&&(P_done_0_1>=1))&&(P_done_0_2>=1))&&(P_done_0_3>=1))&&(P_done_0_4>=1))&&(P_done_0_5>=1))||((((((P_await_13_1>=1)&&(P_done_1_1>=1))&&(P_done_1_2>=1))&&(P_done_1_3>=1))&&(P_done_1_4>=1))&&(P_done_1_5>=1)))||((((((P_await_13_2>=1)&&(P_done_2_1>=1))&&(P_done_2_2>=1))&&(P_done_2_3>=1))&&(P_done_2_4>=1))&&(P_done_2_5>=1)))||((((((P_await_13_3>=1)&&(P_done_3_1>=1))&&(P_done_3_2>=1))&&(P_done_3_3>=1))&&(P_done_3_4>=1))&&(P_done_3_5>=1)))||((((((P_await_13_4>=1)&&(P_done_4_1>=1))&&(P_done_4_2>=1))&&(P_done_4_3>=1))&&(P_done_4_4>=1))&&(P_done_4_5>=1)))||((((((P_await_13_5>=1)&&(P_done_5_1>=1))&&(P_done_5_2>=1))&&(P_done_5_3>=1))&&(P_done_5_4>=1))&&(P_done_5_5>=1)))")))))
Formula 1 simplified : !(G"((((((P_fordo_12_0>=1)||(P_fordo_12_1>=1))||(P_fordo_12_2>=1))||(P_fordo_12_3>=1))||(P_fordo_12_4>=1))||(P_fordo_12_5>=1))" U ("(((((((((((((P_b_0_false>=1)&&(P_setbi_11_0>=1))||((P_b_0_true>=1)&&(P_setbi_11_0>=1)))||((P_b_1_false>=1)&&(P_setbi_11_1>=1)))||((P_b_1_true>=1)&&(P_setbi_11_1>=1)))||((P_b_2_false>=1)&&(P_setbi_11_2>=1)))||((P_b_2_true>=1)&&(P_setbi_11_2>=1)))||((P_b_3_false>=1)&&(P_setbi_11_3>=1)))||((P_b_3_true>=1)&&(P_setbi_11_3>=1)))||((P_b_4_false>=1)&&(P_setbi_11_4>=1)))||((P_b_4_true>=1)&&(P_setbi_11_4>=1)))||((P_b_5_false>=1)&&(P_setbi_11_5>=1)))||((P_b_5_true>=1)&&(P_setbi_11_5>=1)))" U X"(((((((((((P_await_13_0>=1)&&(P_done_0_1>=1))&&(P_done_0_2>=1))&&(P_done_0_3>=1))&&(P_done_0_4>=1))&&(P_done_0_5>=1))||((((((P_await_13_1>=1)&&(P_done_1_1>=1))&&(P_done_1_2>=1))&&(P_done_1_3>=1))&&(P_done_1_4>=1))&&(P_done_1_5>=1)))||((((((P_await_13_2>=1)&&(P_done_2_1>=1))&&(P_done_2_2>=1))&&(P_done_2_3>=1))&&(P_done_2_4>=1))&&(P_done_2_5>=1)))||((((((P_await_13_3>=1)&&(P_done_3_1>=1))&&(P_done_3_2>=1))&&(P_done_3_3>=1))&&(P_done_3_4>=1))&&(P_done_3_5>=1)))||((((((P_await_13_4>=1)&&(P_done_4_1>=1))&&(P_done_4_2>=1))&&(P_done_4_3>=1))&&(P_done_4_4>=1))&&(P_done_4_5>=1)))||((((((P_await_13_5>=1)&&(P_done_5_1>=1))&&(P_done_5_2>=1))&&(P_done_5_3>=1))&&(P_done_5_4>=1))&&(P_done_5_5>=1)))"))
Compilation finished in 4913 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 157 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ([]((LTLAP1==true)))U(((LTLAP2==true))U(X((LTLAP3==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 75 ms.
FORMULA LamportFastMutEx-PT-5-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ([](X((LTLAP4==true))))U(X(<>([]((LTLAP5==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 34 ms.
FORMULA LamportFastMutEx-PT-5-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []([]((LTLAP6==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 152 ms.
FORMULA LamportFastMutEx-PT-5-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(X([](X(X((LTLAP4==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 85 ms.
FORMULA LamportFastMutEx-PT-5-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(X(<>((LTLAP6==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 64 ms.
FORMULA LamportFastMutEx-PT-5-LTLFireability-05 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([]([]((LTLAP7==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 99 ms.
FORMULA LamportFastMutEx-PT-5-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP8==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 183 ms.
FORMULA LamportFastMutEx-PT-5-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](X((LTLAP9==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 72 ms.
FORMULA LamportFastMutEx-PT-5-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP10==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 170 ms.
FORMULA LamportFastMutEx-PT-5-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ((LTLAP11==true))U(<>((LTLAP12==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 194 ms.
FORMULA LamportFastMutEx-PT-5-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X(<>((LTLAP13==true))))U(<>([](<>((LTLAP14==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 35 ms.
FORMULA LamportFastMutEx-PT-5-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(X(X((LTLAP15==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 61 ms.
FORMULA LamportFastMutEx-PT-5-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((<>(X((LTLAP16==true))))U(X(<>((LTLAP17==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 22 ms.
FORMULA LamportFastMutEx-PT-5-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP18==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 161 ms.
FORMULA LamportFastMutEx-PT-5-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ([]((LTLAP19==true)))U([](<>(X((LTLAP20==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 581 ms.
FORMULA LamportFastMutEx-PT-5-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1527484550065

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 28, 2018 5:13:02 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 28, 2018 5:13:02 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 28, 2018 5:13:02 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 78 ms
May 28, 2018 5:13:02 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 174 places.
May 28, 2018 5:13:02 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 318 transitions.
May 28, 2018 5:13:02 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 24 ms
May 28, 2018 5:13:02 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 100 ms
May 28, 2018 5:13:02 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 6 ms
May 28, 2018 5:13:02 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 2 ms
May 28, 2018 5:13:03 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 318 transitions.
May 28, 2018 5:13:03 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 50 place invariants in 52 ms
May 28, 2018 5:13:03 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 174 variables to be positive in 328 ms
May 28, 2018 5:13:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 318 transitions.
May 28, 2018 5:13:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/318 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 5:13:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 30 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 5:13:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 318 transitions.
May 28, 2018 5:13:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 23 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 5:13:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 318 transitions.
May 28, 2018 5:13:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/318) took 338 ms. Total solver calls (SAT/UNSAT): 57(0/57)
May 28, 2018 5:13:34 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(3/318) took 3350 ms. Total solver calls (SAT/UNSAT): 226(5/221)
May 28, 2018 5:13:40 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(18/318) took 8944 ms. Total solver calls (SAT/UNSAT): 1427(34/1393)
May 28, 2018 5:13:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(24/318) took 14087 ms. Total solver calls (SAT/UNSAT): 2030(87/1943)
May 28, 2018 5:13:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(29/318) took 19661 ms. Total solver calls (SAT/UNSAT): 2505(127/2378)
May 28, 2018 5:13:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(34/318) took 24065 ms. Total solver calls (SAT/UNSAT): 2955(162/2793)
May 28, 2018 5:13:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(37/318) took 27406 ms. Total solver calls (SAT/UNSAT): 3213(181/3032)
May 28, 2018 5:14:04 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(42/318) took 32575 ms. Total solver calls (SAT/UNSAT): 3623(210/3413)
May 28, 2018 5:14:09 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(62/318) took 37879 ms. Total solver calls (SAT/UNSAT): 6438(420/6018)
May 28, 2018 5:14:12 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(100/318) took 41301 ms. Total solver calls (SAT/UNSAT): 10617(865/9752)
May 28, 2018 5:14:16 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(104/318) took 44749 ms. Total solver calls (SAT/UNSAT): 11115(880/10235)
May 28, 2018 5:14:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(108/318) took 49210 ms. Total solver calls (SAT/UNSAT): 11597(894/10703)
May 28, 2018 5:14:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(110/318) took 52440 ms. Total solver calls (SAT/UNSAT): 11832(922/10910)
May 28, 2018 5:14:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(113/318) took 56351 ms. Total solver calls (SAT/UNSAT): 12177(964/11213)
May 28, 2018 5:14:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(120/318) took 59435 ms. Total solver calls (SAT/UNSAT): 12947(1054/11893)
May 28, 2018 5:14:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(123/318) took 64342 ms. Total solver calls (SAT/UNSAT): 13262(1090/12172)
May 28, 2018 5:14:40 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(126/318) took 69146 ms. Total solver calls (SAT/UNSAT): 13568(1125/12443)
May 28, 2018 5:14:46 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(129/318) took 74498 ms. Total solver calls (SAT/UNSAT): 13865(1158/12707)
May 28, 2018 5:14:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(131/318) took 79443 ms. Total solver calls (SAT/UNSAT): 14058(1180/12878)
May 28, 2018 5:14:56 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(133/318) took 85243 ms. Total solver calls (SAT/UNSAT): 14247(1200/13047)
May 28, 2018 5:15:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(142/318) took 88536 ms. Total solver calls (SAT/UNSAT): 14898(1240/13658)
May 28, 2018 5:15:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(157/318) took 91566 ms. Total solver calls (SAT/UNSAT): 15603(1291/14312)
May 28, 2018 5:15:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(165/318) took 95099 ms. Total solver calls (SAT/UNSAT): 15887(1303/14584)
May 28, 2018 5:15:09 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(178/318) took 98128 ms. Total solver calls (SAT/UNSAT): 16262(1330/14932)
May 28, 2018 5:15:12 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(186/318) took 101312 ms. Total solver calls (SAT/UNSAT): 16448(1330/15118)
May 28, 2018 5:15:16 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(205/318) took 104845 ms. Total solver calls (SAT/UNSAT): 16906(1400/15506)
May 28, 2018 5:15:19 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(225/318) took 107879 ms. Total solver calls (SAT/UNSAT): 17298(1450/15848)
May 28, 2018 5:15:23 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(243/318) took 111427 ms. Total solver calls (SAT/UNSAT): 18392(1546/16846)
May 28, 2018 5:15:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(247/318) took 114788 ms. Total solver calls (SAT/UNSAT): 18618(1576/17042)
May 28, 2018 5:15:29 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(259/318) took 117818 ms. Total solver calls (SAT/UNSAT): 19200(1645/17555)
May 28, 2018 5:15:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(266/318) took 121124 ms. Total solver calls (SAT/UNSAT): 19398(1665/17733)
May 28, 2018 5:15:36 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(278/318) took 124541 ms. Total solver calls (SAT/UNSAT): 19722(1677/18045)
May 28, 2018 5:15:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(291/318) took 127591 ms. Total solver calls (SAT/UNSAT): 20008(1715/18293)
May 28, 2018 5:15:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(311/318) took 130595 ms. Total solver calls (SAT/UNSAT): 20130(1725/18405)
May 28, 2018 5:15:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 130710 ms. Total solver calls (SAT/UNSAT): 20133(1725/18408)
May 28, 2018 5:15:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 318 transitions.
May 28, 2018 5:15:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 38 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 5:15:42 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 159525ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-PT-5"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-PT-5.tgz
mv LamportFastMutEx-PT-5 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is LamportFastMutEx-PT-5, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r260-csrt-152732585200038"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;