Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
....................
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 6.9K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 29K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 55K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 167K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:49 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K May 15 18:49 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 13K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 14K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 39K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 5.5K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 22K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 121 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 359 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 34K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 102K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.4K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:49 equiv_col
-rw-r--r-- 1 mcc users 10 May 15 18:49 instance
-rw-r--r-- 1 mcc users 6 May 15 18:49 iscolored
-rw-r--r-- 1 mcc users 598K May 15 18:49 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is BridgeAndVehicles-PT-V20P10N10, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r224-ebro-152732378700078
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-00
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-01
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-02
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-03
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-04
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-05
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-06
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-07
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-08
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-09
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-10
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-11
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-12
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-13
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-14
FORMULA_NAME BridgeAndVehicles-PT-V20P10N10-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527565181873

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !(((X("(((CAPACITE>=10)&&(VIDANGE_1>=1))||((CAPACITE>=10)&&(VIDANGE_2>=1)))"))U(X(F(F("(((((((((((((((((((((((NB_ATTENTE_A_1>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1))||((((NB_ATTENTE_A_2>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_3>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_4>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_5>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_6>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_7>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_8>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_9>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_10>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_11>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_12>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_13>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_14>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_15>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_16>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_17>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_18>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_19>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_20>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))"))))))
Formula 0 simplified : !(X"(((CAPACITE>=10)&&(VIDANGE_1>=1))||((CAPACITE>=10)&&(VIDANGE_2>=1)))" U XF"(((((((((((((((((((((((NB_ATTENTE_A_1>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1))||((((NB_ATTENTE_A_2>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_3>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_4>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_5>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_6>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_7>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_8>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_9>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_10>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_11>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_12>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_13>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_14>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_15>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_16>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_17>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_18>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_19>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))||((((NB_ATTENTE_A_20>=1)&&(ATTENTE_A>=1))&&(CAPACITE>=1))&&(CONTROLEUR_1>=1)))")
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 130
// Phase 1: matrix 130 rows 68 cols
invariant :ATTENTE_B + SUR_PONT_B + SORTI_B + ROUTE_B = 20
invariant :SUR_PONT_A + CAPACITE + -1'ATTENTE_B + -1'SORTI_B + -1'ROUTE_B = -10
invariant :CONTROLEUR_1 + CONTROLEUR_2 + CHOIX_1 + CHOIX_2 + VIDANGE_1 + VIDANGE_2 = 1
invariant :COMPTEUR_0 + COMPTEUR_1 + COMPTEUR_2 + COMPTEUR_3 + COMPTEUR_4 + COMPTEUR_5 + COMPTEUR_6 + COMPTEUR_7 + COMPTEUR_8 + COMPTEUR_9 + COMPTEUR_10 = 1
invariant :ROUTE_A + ATTENTE_A + SORTI_A + -1'CAPACITE + ATTENTE_B + SORTI_B + ROUTE_B = 30
invariant :NB_ATTENTE_A_0 + NB_ATTENTE_A_1 + NB_ATTENTE_A_2 + NB_ATTENTE_A_3 + NB_ATTENTE_A_4 + NB_ATTENTE_A_5 + NB_ATTENTE_A_6 + NB_ATTENTE_A_7 + NB_ATTENTE_A_8 + NB_ATTENTE_A_9 + NB_ATTENTE_A_10 + NB_ATTENTE_A_11 + NB_ATTENTE_A_12 + NB_ATTENTE_A_13 + NB_ATTENTE_A_14 + NB_ATTENTE_A_15 + NB_ATTENTE_A_16 + NB_ATTENTE_A_17 + NB_ATTENTE_A_18 + NB_ATTENTE_A_19 + NB_ATTENTE_A_20 = 1
invariant :NB_ATTENTE_B_0 + NB_ATTENTE_B_1 + NB_ATTENTE_B_2 + NB_ATTENTE_B_3 + NB_ATTENTE_B_4 + NB_ATTENTE_B_5 + NB_ATTENTE_B_6 + NB_ATTENTE_B_7 + NB_ATTENTE_B_8 + NB_ATTENTE_B_9 + NB_ATTENTE_B_10 + NB_ATTENTE_B_11 + NB_ATTENTE_B_12 + NB_ATTENTE_B_13 + NB_ATTENTE_B_14 + NB_ATTENTE_B_15 + NB_ATTENTE_B_16 + NB_ATTENTE_B_17 + NB_ATTENTE_B_18 + NB_ATTENTE_B_19 + NB_ATTENTE_B_20 = 1
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 12809 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 84 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X((LTLAP0==true)))U(X(<>(<>((LTLAP1==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 7484 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-00 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((LTLAP0==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 54959 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-01 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](X((LTLAP1==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 97 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((LTLAP2==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 6107 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((<>((LTLAP3==true)))U((LTLAP4==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 102 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP1==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 461 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>([](([]((LTLAP5==true)))U(<>((LTLAP0==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 65187 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP6==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 57 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-07 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>(<>([](<>((LTLAP7==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 70 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP8==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 386 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(<>([]([]((LTLAP9==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 441 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>([](X([]((LTLAP10==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 63 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP11==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 373 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (<>(<>(<>((LTLAP12==true)))))U((<>((LTLAP13==true)))U((LTLAP14==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 440 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(<>((LTLAP5==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 11191 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-14 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP15==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 389 ms.
FORMULA BridgeAndVehicles-PT-V20P10N10-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1527565505403

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 29, 2018 3:39:45 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 29, 2018 3:39:45 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 29, 2018 3:39:45 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 263 ms
May 29, 2018 3:39:45 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 68 places.
May 29, 2018 3:39:46 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 548 transitions.
May 29, 2018 3:39:46 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 154 ms
May 29, 2018 3:39:47 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 355 ms
May 29, 2018 3:39:47 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 8 ms
May 29, 2018 3:39:47 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 35 ms
May 29, 2018 3:39:47 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 548 transitions.
May 29, 2018 3:39:48 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 7 place invariants in 128 ms
May 29, 2018 3:39:49 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 68 variables to be positive in 1180 ms
May 29, 2018 3:39:49 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 548 transitions.
May 29, 2018 3:39:49 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/548 took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 29, 2018 3:39:49 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 142 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 29, 2018 3:39:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 548 transitions.
May 29, 2018 3:39:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 42 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 29, 2018 3:40:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 548 transitions.
May 29, 2018 3:40:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/548) took 3055 ms. Total solver calls (SAT/UNSAT): 523(263/260)
May 29, 2018 3:40:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(2/548) took 6171 ms. Total solver calls (SAT/UNSAT): 1566(373/1193)
May 29, 2018 3:40:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(7/548) took 9695 ms. Total solver calls (SAT/UNSAT): 4156(648/3508)
May 29, 2018 3:40:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(12/548) took 13720 ms. Total solver calls (SAT/UNSAT): 6721(923/5798)
May 29, 2018 3:40:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(17/548) took 16884 ms. Total solver calls (SAT/UNSAT): 9261(1198/8063)
May 29, 2018 3:40:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(24/548) took 20085 ms. Total solver calls (SAT/UNSAT): 12408(1432/10976)
May 29, 2018 3:40:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(32/548) took 23257 ms. Total solver calls (SAT/UNSAT): 16556(1448/15108)
May 29, 2018 3:40:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(41/548) took 26574 ms. Total solver calls (SAT/UNSAT): 21146(1466/19680)
May 29, 2018 3:40:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(49/548) took 29881 ms. Total solver calls (SAT/UNSAT): 24564(1893/22671)
May 29, 2018 3:40:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(59/548) took 33013 ms. Total solver calls (SAT/UNSAT): 29269(2203/27066)
May 29, 2018 3:40:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(62/548) took 37853 ms. Total solver calls (SAT/UNSAT): 30661(2296/28365)
May 29, 2018 3:41:02 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(70/548) took 40895 ms. Total solver calls (SAT/UNSAT): 34439(2389/32050)
May 29, 2018 3:41:05 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(82/548) took 44133 ms. Total solver calls (SAT/UNSAT): 40085(2389/37696)
May 29, 2018 3:41:09 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(95/548) took 47250 ms. Total solver calls (SAT/UNSAT): 46039(2389/43650)
May 29, 2018 3:41:12 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(109/548) took 50485 ms. Total solver calls (SAT/UNSAT): 52262(2389/49873)
May 29, 2018 3:41:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(123/548) took 53667 ms. Total solver calls (SAT/UNSAT): 58289(2389/55900)
May 29, 2018 3:41:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(137/548) took 56725 ms. Total solver calls (SAT/UNSAT): 64120(2389/61731)
May 29, 2018 3:41:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(153/548) took 59895 ms. Total solver calls (SAT/UNSAT): 70544(2389/68155)
May 29, 2018 3:41:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(168/548) took 62950 ms. Total solver calls (SAT/UNSAT): 76334(2389/73945)
May 29, 2018 3:41:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(185/548) took 66100 ms. Total solver calls (SAT/UNSAT): 82624(2389/80235)
May 29, 2018 3:41:30 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(201/548) took 69175 ms. Total solver calls (SAT/UNSAT): 88280(2389/85891)
May 29, 2018 3:41:34 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(217/548) took 72253 ms. Total solver calls (SAT/UNSAT): 93680(2389/91291)
May 29, 2018 3:41:37 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(234/548) took 75358 ms. Total solver calls (SAT/UNSAT): 99137(2389/96748)
May 29, 2018 3:41:40 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(244/548) took 78780 ms. Total solver calls (SAT/UNSAT): 102212(2389/99823)
May 29, 2018 3:41:43 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(250/548) took 82019 ms. Total solver calls (SAT/UNSAT): 104009(2389/101620)
May 29, 2018 3:41:47 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(255/548) took 85342 ms. Total solver calls (SAT/UNSAT): 105479(2389/103090)
May 29, 2018 3:41:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(265/548) took 88343 ms. Total solver calls (SAT/UNSAT): 108344(2389/105955)
May 29, 2018 3:41:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(285/548) took 91381 ms. Total solver calls (SAT/UNSAT): 113774(2389/111385)
May 29, 2018 3:41:56 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(306/548) took 94515 ms. Total solver calls (SAT/UNSAT): 119045(2389/116656)
May 29, 2018 3:41:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(330/548) took 97634 ms. Total solver calls (SAT/UNSAT): 124529(2389/122140)
May 29, 2018 3:42:02 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(352/548) took 100777 ms. Total solver calls (SAT/UNSAT): 129050(2389/126661)
May 29, 2018 3:42:05 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(377/548) took 103799 ms. Total solver calls (SAT/UNSAT): 133600(2389/131211)
May 29, 2018 3:42:08 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(403/548) took 106806 ms. Total solver calls (SAT/UNSAT): 137669(2389/135280)
May 29, 2018 3:42:11 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(423/548) took 109856 ms. Total solver calls (SAT/UNSAT): 140339(2389/137950)
May 29, 2018 3:42:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(444/548) took 113000 ms. Total solver calls (SAT/UNSAT): 142712(2389/140323)
May 29, 2018 3:42:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(485/548) took 116017 ms. Total solver calls (SAT/UNSAT): 146074(2389/143685)
May 29, 2018 3:42:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(526/548) took 119019 ms. Total solver calls (SAT/UNSAT): 147755(2389/145366)
May 29, 2018 3:42:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 120119 ms. Total solver calls (SAT/UNSAT): 147965(2389/145576)
May 29, 2018 3:42:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 548 transitions.
May 29, 2018 3:42:23 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 1450 ms. Total solver calls (SAT/UNSAT): 85(0/85)
May 29, 2018 3:42:23 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 156205ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-PT-V20P10N10"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-PT-V20P10N10.tgz
mv BridgeAndVehicles-PT-V20P10N10 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is BridgeAndVehicles-PT-V20P10N10, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r224-ebro-152732378700078"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;