Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
..................
/home/mcc/execution
total 216K
-rw-r--r-- 1 mcc users 4.3K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 22K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 14K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:49 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K May 15 18:49 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.8K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 9.8K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.1K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 122 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 360 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 3.4K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:49 equiv_pt
-rw-r--r-- 1 mcc users 10 May 15 18:49 instance
-rw-r--r-- 1 mcc users 5 May 15 18:49 iscolored
-rw-r--r-- 1 mcc users 39K May 15 18:49 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is BridgeAndVehicles-COL-V20P20N10, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r224-ebro-152732378700044
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-COL-V20P20N10-LTLFireability-00
FORMULA_NAME BridgeAndVehicles-COL-V20P20N10-LTLFireability-01
FORMULA_NAME BridgeAndVehicles-COL-V20P20N10-LTLFireability-02
FORMULA_NAME BridgeAndVehicles-COL-V20P20N10-LTLFireability-03
FORMULA_NAME BridgeAndVehicles-COL-V20P20N10-LTLFireability-04
FORMULA_NAME BridgeAndVehicles-COL-V20P20N10-LTLFireability-05
FORMULA_NAME BridgeAndVehicles-COL-V20P20N10-LTLFireability-06
FORMULA_NAME BridgeAndVehicles-COL-V20P20N10-LTLFireability-07
FORMULA_NAME BridgeAndVehicles-COL-V20P20N10-LTLFireability-08
FORMULA_NAME BridgeAndVehicles-COL-V20P20N10-LTLFireability-09
FORMULA_NAME BridgeAndVehicles-COL-V20P20N10-LTLFireability-10
FORMULA_NAME BridgeAndVehicles-COL-V20P20N10-LTLFireability-11
FORMULA_NAME BridgeAndVehicles-COL-V20P20N10-LTLFireability-12
FORMULA_NAME BridgeAndVehicles-COL-V20P20N10-LTLFireability-13
FORMULA_NAME BridgeAndVehicles-COL-V20P20N10-LTLFireability-14
FORMULA_NAME BridgeAndVehicles-COL-V20P20N10-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527550437813

23:34:01.261 [main] ERROR PNML validation - The rng grammar file can't be accessed : www.pnml.org
23:34:01.264 [main] ERROR import - Grammar file errors have been raised, the validation can't be done, process will continue without Grammar validation
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((F(F((F("(((CAPACITE.CAPACITE_0>=20)&&(sens0.VIDANGE_0>=1))||((CAPACITE.CAPACITE_0>=20)&&(sens1.VIDANGE_1>=1)))"))U(X("(((((((((((((((((((((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA1.NB_ATTENTE_A_1>=1))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA2.NB_ATTENTE_A_2>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA3.NB_ATTENTE_A_3>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA4.NB_ATTENTE_A_4>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA5.NB_ATTENTE_A_5>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA6.NB_ATTENTE_A_6>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA7.NB_ATTENTE_A_7>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA8.NB_ATTENTE_A_8>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA9.NB_ATTENTE_A_9>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA10.NB_ATTENTE_A_10>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA11.NB_ATTENTE_A_11>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA12.NB_ATTENTE_A_12>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA13.NB_ATTENTE_A_13>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA14.NB_ATTENTE_A_14>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA15.NB_ATTENTE_A_15>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA16.NB_ATTENTE_A_16>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA17.NB_ATTENTE_A_17>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA18.NB_ATTENTE_A_18>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA19.NB_ATTENTE_A_19>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA20.NB_ATTENTE_A_20>=1)))"))))))
Formula 0 simplified : !F(F"(((CAPACITE.CAPACITE_0>=20)&&(sens0.VIDANGE_0>=1))||((CAPACITE.CAPACITE_0>=20)&&(sens1.VIDANGE_1>=1)))" U X"(((((((((((((((((((((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA1.NB_ATTENTE_A_1>=1))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA2.NB_ATTENTE_A_2>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA3.NB_ATTENTE_A_3>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA4.NB_ATTENTE_A_4>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA5.NB_ATTENTE_A_5>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA6.NB_ATTENTE_A_6>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA7.NB_ATTENTE_A_7>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA8.NB_ATTENTE_A_8>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA9.NB_ATTENTE_A_9>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA10.NB_ATTENTE_A_10>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA11.NB_ATTENTE_A_11>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA12.NB_ATTENTE_A_12>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA13.NB_ATTENTE_A_13>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA14.NB_ATTENTE_A_14>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA15.NB_ATTENTE_A_15>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA16.NB_ATTENTE_A_16>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA17.NB_ATTENTE_A_17>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA18.NB_ATTENTE_A_18>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA19.NB_ATTENTE_A_19>=1)))||((((ATTENTE_A.ATTENTE_A_0>=1)&&(sens0.CONTROLEUR_0>=1))&&(CAPACITE.CAPACITE_0>=1))&&(voitureA20.NB_ATTENTE_A_20>=1)))")
built 159 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 130
// Phase 1: matrix 130 rows 68 cols
invariant :sens0:CONTROLEUR_0 + sens0:CHOIX_0 + sens0:VIDANGE_0 + sens1:CONTROLEUR_1 + sens1:CHOIX_1 + sens1:VIDANGE_1 = 1
invariant :SUR_PONT_B:SUR_PONT_B_0 + ATTENTE_B:ATTENTE_B_0 + ROUTE_B:ROUTE_B_0 + SORTI_B:SORTI_B_0 = 20
invariant :SORTI_A:SORTI_A_0 + ROUTE_A:ROUTE_A_0 + ATTENTE_A:ATTENTE_A_0 + SUR_PONT_A:SUR_PONT_A_0 = 20
invariant :compteur0:COMPTEUR_0 + compteur1:COMPTEUR_1 + compteur2:COMPTEUR_2 + compteur3:COMPTEUR_3 + compteur4:COMPTEUR_4 + compteur5:COMPTEUR_5 + compteur6:COMPTEUR_6 + compteur7:COMPTEUR_7 + compteur8:COMPTEUR_8 + compteur9:COMPTEUR_9 + compteur10:COMPTEUR_10 = 1
invariant :voitureA0:NB_ATTENTE_A_0 + voitureA1:NB_ATTENTE_A_1 + voitureA2:NB_ATTENTE_A_2 + voitureA3:NB_ATTENTE_A_3 + voitureA4:NB_ATTENTE_A_4 + voitureA5:NB_ATTENTE_A_5 + voitureA6:NB_ATTENTE_A_6 + voitureA7:NB_ATTENTE_A_7 + voitureA8:NB_ATTENTE_A_8 + voitureA9:NB_ATTENTE_A_9 + voitureA10:NB_ATTENTE_A_10 + voitureA11:NB_ATTENTE_A_11 + voitureA12:NB_ATTENTE_A_12 + voitureA13:NB_ATTENTE_A_13 + voitureA14:NB_ATTENTE_A_14 + voitureA15:NB_ATTENTE_A_15 + voitureA16:NB_ATTENTE_A_16 + voitureA17:NB_ATTENTE_A_17 + voitureA18:NB_ATTENTE_A_18 + voitureA19:NB_ATTENTE_A_19 + voitureA20:NB_ATTENTE_A_20 = 1
invariant :CAPACITE:CAPACITE_0 + SUR_PONT_A:SUR_PONT_A_0 + -1'ATTENTE_B:ATTENTE_B_0 + -1'ROUTE_B:ROUTE_B_0 + -1'SORTI_B:SORTI_B_0 = 0
invariant :voitureB0:NB_ATTENTE_B_0 + voitureB1:NB_ATTENTE_B_1 + voitureB2:NB_ATTENTE_B_2 + voitureB3:NB_ATTENTE_B_3 + voitureB4:NB_ATTENTE_B_4 + voitureB5:NB_ATTENTE_B_5 + voitureB6:NB_ATTENTE_B_6 + voitureB7:NB_ATTENTE_B_7 + voitureB8:NB_ATTENTE_B_8 + voitureB9:NB_ATTENTE_B_9 + voitureB10:NB_ATTENTE_B_10 + voitureB11:NB_ATTENTE_B_11 + voitureB12:NB_ATTENTE_B_12 + voitureB13:NB_ATTENTE_B_13 + voitureB14:NB_ATTENTE_B_14 + voitureB15:NB_ATTENTE_B_15 + voitureB16:NB_ATTENTE_B_16 + voitureB17:NB_ATTENTE_B_17 + voitureB18:NB_ATTENTE_B_18 + voitureB19:NB_ATTENTE_B_19 + voitureB20:NB_ATTENTE_B_20 = 1
Reverse transition relation is NOT exact ! Due to transitions enregistrement_A, liberation_A, basculement, liberation_B, enregistrement_B, altern_cpt, timeout_A, timeout_B, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :0/3/8/11
Computing Next relation with stutter on 20 deadlock states
2 unique states visited
0 strongly connected components in search stack
1 transitions explored
2 items max in DFS search stack
7679 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,76.8542,989952,1,0,2.16625e+06,1031,1452,2.57301e+06,91,3284,8547798
no accepting run found
Formula 0 is TRUE no accepting run found.
FORMULA BridgeAndVehicles-COL-V20P20N10-LTLFireability-00 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 1 : !(("(SUR_PONT_B.SUR_PONT_B_0>=1)"))
Formula 1 simplified : !"(SUR_PONT_B.SUR_PONT_B_0>=1)"
Computing Next relation with stutter on 20 deadlock states
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 13294 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 79 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP2==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 389 ms.
FORMULA BridgeAndVehicles-COL-V20P20N10-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP3==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 37 ms.
FORMULA BridgeAndVehicles-COL-V20P20N10-LTLFireability-02 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []([](((LTLAP4==true))U(<>((LTLAP0==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 91989 ms.
FORMULA BridgeAndVehicles-COL-V20P20N10-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>((<>((LTLAP0==true)))U((LTLAP1==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 9793 ms.
FORMULA BridgeAndVehicles-COL-V20P20N10-LTLFireability-04 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, [](([](<>((LTLAP4==true))))U(((LTLAP5==true))U((LTLAP6==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 451 ms.
FORMULA BridgeAndVehicles-COL-V20P20N10-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (<>(X(<>((LTLAP7==true)))))U((X((LTLAP4==true)))U((LTLAP6==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 11738 ms.
FORMULA BridgeAndVehicles-COL-V20P20N10-LTLFireability-06 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP5==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 330 ms.
FORMULA BridgeAndVehicles-COL-V20P20N10-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP7==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 251 ms.
FORMULA BridgeAndVehicles-COL-V20P20N10-LTLFireability-08 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>((((LTLAP8==true))U((LTLAP9==true)))U([]([]((LTLAP5==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 416 ms.
FORMULA BridgeAndVehicles-COL-V20P20N10-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP0==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 98 ms.
FORMULA BridgeAndVehicles-COL-V20P20N10-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, [](<>([](<>((LTLAP2==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 18015 ms.
FORMULA BridgeAndVehicles-COL-V20P20N10-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP0==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 394 ms.
FORMULA BridgeAndVehicles-COL-V20P20N10-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ((LTLAP1==true))U(X(((LTLAP1==true))U((LTLAP9==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 113 ms.
FORMULA BridgeAndVehicles-COL-V20P20N10-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(X((LTLAP4==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 64 ms.
FORMULA BridgeAndVehicles-COL-V20P20N10-LTLFireability-14 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ((X((LTLAP1==true)))U((LTLAP4==true)))U(X(<>([]((LTLAP10==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 85 ms.
FORMULA BridgeAndVehicles-COL-V20P20N10-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1527550779397

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 28, 2018 11:34:00 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 28, 2018 11:34:00 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 28, 2018 11:34:00 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
May 28, 2018 11:34:01 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Load time of PNML (colored model parsed with PNMLFW) : 1333 ms
May 28, 2018 11:34:01 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 15 places.
May 28, 2018 11:34:01 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Computed order using colors.
May 28, 2018 11:34:01 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: sort/places :sens->CONTROLEUR,CHOIX,VIDANGE,
compteur->COMPTEUR,
Dot->CAPACITE,SORTI_A,ROUTE_A,ATTENTE_A,SUR_PONT_A,SUR_PONT_B,ATTENTE_B,ROUTE_B,SORTI_B,
voitureA->NB_ATTENTE_A,
voitureB->NB_ATTENTE_B,

May 28, 2018 11:34:02 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 11 transitions.
May 28, 2018 11:34:02 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Computed order based on color domains.
May 28, 2018 11:34:02 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 11 ms
May 28, 2018 11:34:02 PM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 28, 2018 11:34:02 PM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 28, 2018 11:34:02 PM fr.lip6.move.gal.instantiate.Instantiator instantiateParameters
INFO: On-the-fly reduction of False transitions avoided exploring 59.0 instantiations of transitions. Total transitions/syncs built is 178
May 28, 2018 11:34:02 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 110 ms
May 28, 2018 11:34:04 PM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays NB_ATTENTE_A, NB_ATTENTE_B, CONTROLEUR, CHOIX, COMPTEUR, VIDANGE to variables to allow decomposition.
May 28, 2018 11:34:04 PM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 125 redundant transitions.
May 28, 2018 11:34:06 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 13 ms
May 28, 2018 11:34:06 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 51 ms
May 28, 2018 11:34:06 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 11 transitions. Expanding to a total of 631 deterministic transitions.
May 28, 2018 11:34:06 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 8 ms.
May 28, 2018 11:34:07 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 7 place invariants in 59 ms
May 28, 2018 11:34:07 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 68 variables to be positive in 450 ms
May 28, 2018 11:34:07 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 548 transitions.
May 28, 2018 11:34:07 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/548 took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 11:34:07 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 110 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 11:34:07 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 548 transitions.
May 28, 2018 11:34:07 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 41 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 28, 2018 11:34:26 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 548 transitions.
May 28, 2018 11:34:26 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/548) took 611 ms. Total solver calls (SAT/UNSAT): 481(221/260)
May 28, 2018 11:34:30 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(6/548) took 3893 ms. Total solver calls (SAT/UNSAT): 3346(299/3047)
May 28, 2018 11:34:33 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(10/548) took 7684 ms. Total solver calls (SAT/UNSAT): 5236(351/4885)
May 28, 2018 11:34:37 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(19/548) took 10820 ms. Total solver calls (SAT/UNSAT): 9430(468/8962)
May 28, 2018 11:34:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(30/548) took 14349 ms. Total solver calls (SAT/UNSAT): 14643(562/14081)
May 28, 2018 11:34:44 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(35/548) took 17822 ms. Total solver calls (SAT/UNSAT): 17213(572/16641)
May 28, 2018 11:34:47 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(40/548) took 21609 ms. Total solver calls (SAT/UNSAT): 19758(582/19176)
May 28, 2018 11:34:50 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(45/548) took 24611 ms. Total solver calls (SAT/UNSAT): 21772(887/20885)
May 28, 2018 11:34:54 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(48/548) took 27743 ms. Total solver calls (SAT/UNSAT): 23206(980/22226)
May 28, 2018 11:34:57 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(52/548) took 30780 ms. Total solver calls (SAT/UNSAT): 25104(1104/24000)
May 28, 2018 11:35:00 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(55/548) took 33856 ms. Total solver calls (SAT/UNSAT): 26517(1197/25320)
May 28, 2018 11:35:04 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(61/548) took 37716 ms. Total solver calls (SAT/UNSAT): 29316(1383/27933)
May 28, 2018 11:35:07 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(70/548) took 41020 ms. Total solver calls (SAT/UNSAT): 33557(1507/32050)
May 28, 2018 11:35:10 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(75/548) took 44100 ms. Total solver calls (SAT/UNSAT): 35927(1507/34420)
May 28, 2018 11:35:13 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(79/548) took 47392 ms. Total solver calls (SAT/UNSAT): 37805(1507/36298)
May 28, 2018 11:35:16 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(84/548) took 50612 ms. Total solver calls (SAT/UNSAT): 40130(1507/38623)
May 28, 2018 11:35:20 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(86/548) took 53900 ms. Total solver calls (SAT/UNSAT): 41053(1507/39546)
May 28, 2018 11:35:24 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(90/548) took 58092 ms. Total solver calls (SAT/UNSAT): 42887(1507/41380)
May 28, 2018 11:35:27 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(101/548) took 61176 ms. Total solver calls (SAT/UNSAT): 47848(1507/46341)
May 28, 2018 11:35:30 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(114/548) took 64519 ms. Total solver calls (SAT/UNSAT): 53555(1507/52048)
May 28, 2018 11:35:34 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(117/548) took 67947 ms. Total solver calls (SAT/UNSAT): 54848(1507/53341)
May 28, 2018 11:35:37 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(123/548) took 71665 ms. Total solver calls (SAT/UNSAT): 57407(1507/55900)
May 28, 2018 11:35:41 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(129/548) took 75125 ms. Total solver calls (SAT/UNSAT): 59930(1507/58423)
May 28, 2018 11:35:45 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(133/548) took 79167 ms. Total solver calls (SAT/UNSAT): 61592(1507/60085)
May 28, 2018 11:35:48 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(136/548) took 82345 ms. Total solver calls (SAT/UNSAT): 62828(1507/61321)
May 28, 2018 11:35:51 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(142/548) took 85641 ms. Total solver calls (SAT/UNSAT): 65273(1507/63766)
May 28, 2018 11:35:55 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(150/548) took 89153 ms. Total solver calls (SAT/UNSAT): 68477(1507/66970)
May 28, 2018 11:35:58 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(157/548) took 92192 ms. Total solver calls (SAT/UNSAT): 71228(1507/69721)
May 28, 2018 11:36:01 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(165/548) took 95578 ms. Total solver calls (SAT/UNSAT): 74312(1507/72805)
May 28, 2018 11:36:04 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(173/548) took 98684 ms. Total solver calls (SAT/UNSAT): 77332(1507/75825)
May 28, 2018 11:36:08 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(188/548) took 101708 ms. Total solver calls (SAT/UNSAT): 82822(1507/81315)
May 28, 2018 11:36:11 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(198/548) took 104986 ms. Total solver calls (SAT/UNSAT): 86357(1507/84850)
May 28, 2018 11:36:14 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(207/548) took 108027 ms. Total solver calls (SAT/UNSAT): 89453(1507/87946)
May 28, 2018 11:36:17 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(220/548) took 111686 ms. Total solver calls (SAT/UNSAT): 93782(1507/92275)
May 28, 2018 11:36:21 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(235/548) took 114753 ms. Total solver calls (SAT/UNSAT): 98567(1507/97060)
May 28, 2018 11:36:24 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(253/548) took 117790 ms. Total solver calls (SAT/UNSAT): 104012(1507/102505)
May 28, 2018 11:36:27 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(270/548) took 120897 ms. Total solver calls (SAT/UNSAT): 108857(1507/107350)
May 28, 2018 11:36:30 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(284/548) took 124264 ms. Total solver calls (SAT/UNSAT): 112630(1507/111123)
May 28, 2018 11:36:34 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(293/548) took 127794 ms. Total solver calls (SAT/UNSAT): 114952(1507/113445)
May 28, 2018 11:36:37 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(303/548) took 131393 ms. Total solver calls (SAT/UNSAT): 117437(1507/115930)
May 28, 2018 11:36:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(317/548) took 134536 ms. Total solver calls (SAT/UNSAT): 120748(1507/119241)
May 28, 2018 11:36:43 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(330/548) took 137680 ms. Total solver calls (SAT/UNSAT): 123647(1507/122140)
May 28, 2018 11:36:47 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(346/548) took 140701 ms. Total solver calls (SAT/UNSAT): 126983(1507/125476)
May 28, 2018 11:36:50 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(360/548) took 144128 ms. Total solver calls (SAT/UNSAT): 129692(1507/128185)
May 28, 2018 11:36:54 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(371/548) took 147711 ms. Total solver calls (SAT/UNSAT): 131683(1507/130176)
May 28, 2018 11:36:57 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(388/548) took 150764 ms. Total solver calls (SAT/UNSAT): 134522(1507/133015)
May 28, 2018 11:37:00 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(405/548) took 153881 ms. Total solver calls (SAT/UNSAT): 137072(1507/135565)
May 28, 2018 11:37:03 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(429/548) took 156919 ms. Total solver calls (SAT/UNSAT): 140180(1507/138673)
May 28, 2018 11:37:06 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(472/548) took 159950 ms. Total solver calls (SAT/UNSAT): 144308(1507/142801)
May 28, 2018 11:37:09 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 162831 ms. Total solver calls (SAT/UNSAT): 147083(1507/145576)
May 28, 2018 11:37:09 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 548 transitions.
May 28, 2018 11:37:10 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 1728 ms. Total solver calls (SAT/UNSAT): 85(0/85)
May 28, 2018 11:37:11 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 184738ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-COL-V20P20N10"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-COL-V20P20N10.tgz
mv BridgeAndVehicles-COL-V20P20N10 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is BridgeAndVehicles-COL-V20P20N10, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r224-ebro-152732378700044"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;