fond
Model Checking Contest 2018
8th edition, Bratislava, Slovakia, June 26, 2018
Execution of r213-smll-152732264100256
Last Updated
June 26, 2018

About the Execution of ITS-Tools.L for DNAwalker-PT-15ringRRLarge

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15753.070 27010.00 56435.00 513.30 FFFFFFFFFFFFFFFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.....................
/home/mcc/execution
total 300K
-rw-r--r-- 1 mcc users 3.4K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 19K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.6K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.5K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 7.4K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.4K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 117 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 355 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 3.2K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 19K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 14 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 135K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is DNAwalker-PT-15ringRRLarge, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r213-smll-152732264100256
=====================================================================


--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DNAwalker-PT-15ringRRLarge-LTLFireability-00
FORMULA_NAME DNAwalker-PT-15ringRRLarge-LTLFireability-01
FORMULA_NAME DNAwalker-PT-15ringRRLarge-LTLFireability-02
FORMULA_NAME DNAwalker-PT-15ringRRLarge-LTLFireability-03
FORMULA_NAME DNAwalker-PT-15ringRRLarge-LTLFireability-04
FORMULA_NAME DNAwalker-PT-15ringRRLarge-LTLFireability-05
FORMULA_NAME DNAwalker-PT-15ringRRLarge-LTLFireability-06
FORMULA_NAME DNAwalker-PT-15ringRRLarge-LTLFireability-07
FORMULA_NAME DNAwalker-PT-15ringRRLarge-LTLFireability-08
FORMULA_NAME DNAwalker-PT-15ringRRLarge-LTLFireability-09
FORMULA_NAME DNAwalker-PT-15ringRRLarge-LTLFireability-10
FORMULA_NAME DNAwalker-PT-15ringRRLarge-LTLFireability-11
FORMULA_NAME DNAwalker-PT-15ringRRLarge-LTLFireability-12
FORMULA_NAME DNAwalker-PT-15ringRRLarge-LTLFireability-13
FORMULA_NAME DNAwalker-PT-15ringRRLarge-LTLFireability-14
FORMULA_NAME DNAwalker-PT-15ringRRLarge-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527915629022

Converted graph to binary with : CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.louvain.binaries_1.0.0.201805241334/bin/convert-linux64, -i, /tmp/graph585597869292491018.txt, -o, /tmp/graph585597869292491018.bin, -w, /tmp/graph585597869292491018.weights], workingDir=null]
Built communities with : CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.louvain.binaries_1.0.0.201805241334/bin/louvain-linux64, /tmp/graph585597869292491018.bin, -l, -1, -v, -w, /tmp/graph585597869292491018.weights, -q, 0, -e, 0.001], workingDir=null]
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((G(G("((u18.A19>=2)&&(u16.A17>=1))"))))
Formula 0 simplified : !G"((u18.A19>=2)&&(u16.A17>=1))"
built 163 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 311
// Phase 1: matrix 311 rows 33 cols
Reverse transition relation is NOT exact ! Due to transitions t1_2, t1_3, t1_4, t1_5, t1_6, t1_7, t1_8, t1_9, t1_10, t1_12, t1_13, t1_14, t1_15, t1_16, t1_17, t1_18, t1_19, t1_20, t1_21, t1_22, t1_23, t1_25, t1_26, t1_27, t2_3, t2_4, t2_5, t2_6, t2_7, t2_8, t2_9, t2_14, t2_15, t2_16, t2_17, t2_21, t2_22, t2_23, t2_24, t2_25, t2_26, t2_27, t3_2, t3_4, t3_5, t3_6, t3_7, t3_8, t3_16, t3_22, t3_23, t3_24, t3_25, t3_26, t3_27, t4_2, t4_3, t4_5, t4_6, t4_7, t4_8, t4_9, t4_16, t4_25, t4_26, t4_27, t5_2, t5_3, t5_4, t5_6, t5_7, t5_8, t5_9, t5_26, t5_27, t6_2, t6_3, t6_4, t6_5, t6_7, t6_8, t6_9, t6_10, t6_27, t7_2, t7_3, t7_4, t7_5, t7_6, t7_8, t7_9, t7_10, t8_2, t8_3, t8_4, t8_5, t8_6, t8_7, t8_9, t8_10, t8_11, t8_12, t8_16, t10_6, t10_7, t10_8, t10_9, t10_11, t10_12, t10_13, t10_14, t10_15, t10_16, t11_8, t11_9, t11_10, t11_12, t11_13, t11_14, t11_15, t11_16, t12_8, t12_9, t12_10, t12_11, t12_13, t12_14, t12_15, t12_16, t12_17, t13_9, t13_10, t13_11, t13_12, t13_14, t13_15, t13_16, t13_17, t13_18, t14_2, t14_9, t14_10, t14_11, t14_12, t14_13, t14_15, t14_16, t14_17, t14_18, t14_19, t15_2, t15_9, t15_10, t15_11, t15_12, t15_13, t15_14, t15_16, t15_17, t15_18, t15_19, t15_20, t15_21, t16_2, t16_3, t16_4, t16_8, t16_9, t16_10, t16_11, t16_12, t16_13, t16_14, t16_15, t16_17, t16_18, t16_19, t16_20, t16_21, t16_22, t16_27, t17_2, t17_12, t17_13, t17_14, t17_15, t17_16, t17_18, t17_19, t17_20, t17_21, t17_22, t18_13, t18_14, t18_15, t18_16, t18_17, t18_19, t18_20, t18_21, t18_22, t19_14, t19_15, t19_16, t19_17, t19_18, t19_20, t19_21, t19_22, t19_23, t20_15, t20_16, t20_17, t20_18, t20_19, t20_21, t20_22, t20_23, t21_2, t21_15, t21_16, t21_17, t21_18, t21_19, t21_20, t21_22, t21_23, t21_24, t21_25, t23_2, t23_3, t23_19, t23_20, t23_21, t23_22, t23_24, t23_25, t23_26, t23_27, t24_2, t24_3, t24_21, t24_22, t24_23, t24_25, t24_26, t24_27, t25_2, t25_3, t25_4, t25_21, t25_22, t25_23, t25_24, t25_26, t25_27, t26_2, t26_3, t26_4, t26_5, t26_22, t26_23, t26_24, t26_25, t26_27, t27_2, t27_3, t27_4, t27_5, t27_6, t27_16, t27_22, t27_23, t27_24, t27_25, t27_26, u12.tb13, u12.tAb13, u13.tb14, u13.tAb14, u14.tb15, u14.tAb15, u15.tb16, u15.tAb16, u25.tb26, u25.tAb26, u26.tb27, u26.tAb27, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :22/2/288/312
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 3958 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 47 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []([]((LTLAP0==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 73 ms.
FORMULA DNAwalker-PT-15ringRRLarge-LTLFireability-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (<>(X(<>((LTLAP1==true)))))U((LTLAP2==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 19 ms.
FORMULA DNAwalker-PT-15ringRRLarge-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, []((X(<>((LTLAP3==true))))U((LTLAP4==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 18 ms.
FORMULA DNAwalker-PT-15ringRRLarge-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP5==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 57 ms.
FORMULA DNAwalker-PT-15ringRRLarge-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(X(X(<>((LTLAP6==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 23 ms.
FORMULA DNAwalker-PT-15ringRRLarge-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP7==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 56 ms.
FORMULA DNAwalker-PT-15ringRRLarge-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ((LTLAP8==true))U(([]((LTLAP9==true)))U((LTLAP10==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 57 ms.
FORMULA DNAwalker-PT-15ringRRLarge-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP11==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 60 ms.
FORMULA DNAwalker-PT-15ringRRLarge-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ((LTLAP12==true))U(((LTLAP13==true))U(<>((LTLAP14==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 85 ms.
FORMULA DNAwalker-PT-15ringRRLarge-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP15==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 64 ms.
FORMULA DNAwalker-PT-15ringRRLarge-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP16==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 18 ms.
FORMULA DNAwalker-PT-15ringRRLarge-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP17==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 56 ms.
FORMULA DNAwalker-PT-15ringRRLarge-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, [](((LTLAP18==true))U((LTLAP19==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 60 ms.
FORMULA DNAwalker-PT-15ringRRLarge-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP20==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 74 ms.
FORMULA DNAwalker-PT-15ringRRLarge-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP21==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 18 ms.
FORMULA DNAwalker-PT-15ringRRLarge-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(X(X(X(X((LTLAP22==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 66 ms.
FORMULA DNAwalker-PT-15ringRRLarge-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1527915656032

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 02, 2018 5:00:31 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
Jun 02, 2018 5:00:31 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 02, 2018 5:00:32 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 111 ms
Jun 02, 2018 5:00:32 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 33 places.
Jun 02, 2018 5:00:32 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 312 transitions.
Jun 02, 2018 5:00:32 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 21 ms
Jun 02, 2018 5:00:32 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Jun 02, 2018 5:00:32 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 108 ms
Jun 02, 2018 5:00:32 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 63 ms
Begin: Sat Jun 2 05:00:32 2018

Computation of communities with the Newman-Girvan Modularity quality function

level 0:
start computation: Sat Jun 2 05:00:32 2018
network size: 33 nodes, 12 links, 12 weight
quality increased from -0.0833333 to 0.833333
end computation: Sat Jun 2 05:00:32 2018
level 1:
start computation: Sat Jun 2 05:00:32 2018
network size: 27 nodes, 6 links, 12 weight
quality increased from 0.833333 to 0.833333
end computation: Sat Jun 2 05:00:32 2018
End: Sat Jun 2 05:00:32 2018
Total duration: 0 sec
0.833333
Jun 02, 2018 5:00:32 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Jun 02, 2018 5:00:32 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 80 ms
Jun 02, 2018 5:00:32 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
Jun 02, 2018 5:00:32 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 544 redundant transitions.
Jun 02, 2018 5:00:32 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 5 ms
Jun 02, 2018 5:00:32 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 2 ms
Jun 02, 2018 5:00:33 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 312 transitions.
Jun 02, 2018 5:00:33 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 0 place invariants in 16 ms
Jun 02, 2018 5:00:33 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 33 variables to be positive in 160 ms
Jun 02, 2018 5:00:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 312 transitions.
Jun 02, 2018 5:00:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/312 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 02, 2018 5:00:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 44 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 02, 2018 5:00:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 312 transitions.
Jun 02, 2018 5:00:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 10 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 02, 2018 5:00:36 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 312 transitions.
Jun 02, 2018 5:00:36 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(8/312) took 403 ms. Total solver calls (SAT/UNSAT): 552(552/0)
Jun 02, 2018 5:00:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(119/312) took 3405 ms. Total solver calls (SAT/UNSAT): 3975(3975/0)
Jun 02, 2018 5:00:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(276/312) took 6408 ms. Total solver calls (SAT/UNSAT): 6728(6728/0)
Jun 02, 2018 5:00:43 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 6784 ms. Total solver calls (SAT/UNSAT): 6866(6866/0)
Jun 02, 2018 5:00:43 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 312 transitions.
Jun 02, 2018 5:00:49 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 6614 ms. Total solver calls (SAT/UNSAT): 1822(0/1822)
Jun 02, 2018 5:00:49 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 16714ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DNAwalker-PT-15ringRRLarge"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/DNAwalker-PT-15ringRRLarge.tgz
mv DNAwalker-PT-15ringRRLarge execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is DNAwalker-PT-15ringRRLarge, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r213-smll-152732264100256"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;