fond
Model Checking Contest 2018
8th edition, Bratislava, Slovakia, June 26, 2018
Execution of r200-qhx1-152732197100034
Last Updated
June 26, 2018

About the Execution of ITS-Tools for AutoFlight-PT-05b

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15782.230 2627447.00 3836981.00 7918.70 FFF?FFF?FF?F?F?? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
......................................
/home/mcc/execution
total 280K
-rw-r--r-- 1 mcc users 3.5K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 20K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:49 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K May 15 18:49 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.4K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.8K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 9.0K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 19K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 108 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 346 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.5K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:49 equiv_col
-rw-r--r-- 1 mcc users 4 May 15 18:49 instance
-rw-r--r-- 1 mcc users 6 May 15 18:49 iscolored
-rw-r--r-- 1 mcc users 113K May 15 18:49 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is AutoFlight-PT-05b, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r200-qhx1-152732197100034
=====================================================================


--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME AutoFlight-PT-05b-LTLFireability-00
FORMULA_NAME AutoFlight-PT-05b-LTLFireability-01
FORMULA_NAME AutoFlight-PT-05b-LTLFireability-02
FORMULA_NAME AutoFlight-PT-05b-LTLFireability-03
FORMULA_NAME AutoFlight-PT-05b-LTLFireability-04
FORMULA_NAME AutoFlight-PT-05b-LTLFireability-05
FORMULA_NAME AutoFlight-PT-05b-LTLFireability-06
FORMULA_NAME AutoFlight-PT-05b-LTLFireability-07
FORMULA_NAME AutoFlight-PT-05b-LTLFireability-08
FORMULA_NAME AutoFlight-PT-05b-LTLFireability-09
FORMULA_NAME AutoFlight-PT-05b-LTLFireability-10
FORMULA_NAME AutoFlight-PT-05b-LTLFireability-11
FORMULA_NAME AutoFlight-PT-05b-LTLFireability-12
FORMULA_NAME AutoFlight-PT-05b-LTLFireability-13
FORMULA_NAME AutoFlight-PT-05b-LTLFireability-14
FORMULA_NAME AutoFlight-PT-05b-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1527406443067

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !(("(u34.p147>=1)"))
Formula 0 simplified : !"(u34.p147>=1)"
built 79 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 480 rows 482 cols
invariant :u39:p205 + u39:p206 + u39:p207 + u39:p208 + u39:p209 + u39:p210 + u39:p211 + u39:p212 + u39:p213 + u39:p214 + u39:p215 + u39:p216 + u39:p217 + u39:p218 + u39:p219 + u39:p220 + u39:p221 + u69:p13 + u71:p12 + u91:p11 + u90:p10 + u89:p9 + u88:p8 + u87:p7 + u86:p6 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u25:p27 + u25:p28 + u25:p29 + u25:p30 + u25:p31 + u25:p32 + u25:p33 + u25:p34 + u25:p35 + u25:p36 + u25:p37 + u95:p26 + u96:p25 + u93:p24 + u94:p23 + u92:p22 + u82:p21 + u84:p20 + u78:p19 + u80:p18 + u76:p17 + u77:p16 + u73:p15 + u74:p14 + u69:p13 + u71:p12 + u91:p11 + u90:p10 + u89:p9 + u88:p8 + u87:p7 + u86:p6 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u57:p316 + u57:p317 + u57:p318 + u57:p319 + u57:p320 + u57:p321 + u57:p322 + u57:p323 + u57:p324 + u57:p325 + u57:p326 + u57:p327 + u57:p328 + u57:p329 + u57:p330 + u57:p331 + u57:p332 + u57:p333 + u57:p334 + u57:p335 + u57:p336 + u57:p337 + u57:p338 + u57:p339 + u57:p340 + u57:p341 + u57:p342 + u57:p343 + u58:p364 + u58:p365 + u58:p366 + u58:p367 + u58:p368 + u58:p369 + u58:p370 + u58:p371 + u58:p372 + u58:p373 + u58:p374 + u58:p375 + u58:p376 + u58:p377 + u58:p378 + u58:p379 + u58:p380 + u58:p381 + u58:p382 + u58:p383 + u58:p384 + u58:p385 + u58:p386 + u59:p395 + u59:p396 + u59:p397 + u59:p398 + u59:p399 + u59:p400 + u59:p401 + u60:p412 + u60:p413 + u60:p414 + u60:p415 + u60:p416 + u60:p417 + u60:p418 + u61:p429 + u61:p430 + u61:p431 + u61:p432 + u61:p433 + u61:p434 + u61:p435 + u62:p446 + u62:p447 + u62:p448 + u62:p449 + u62:p450 + u62:p451 + u62:p452 + u63:p463 + u63:p464 + u63:p465 + u63:p466 + u63:p467 + u63:p468 + u63:p469 + u64:p478 + u64:p479 + u66:p307 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u26:p38 + u26:p39 + u26:p40 + u26:p41 + u26:p42 + u26:p43 + u26:p44 + u26:p45 + u26:p46 + u26:p47 + u26:p48 + u95:p26 + u96:p25 + u93:p24 + u94:p23 + u92:p22 + u82:p21 + u84:p20 + u78:p19 + u80:p18 + u76:p17 + u77:p16 + u73:p15 + u74:p14 + u69:p13 + u71:p12 + u91:p11 + u90:p10 + u89:p9 + u88:p8 + u87:p7 + u86:p6 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u45:p269 + u45:p270 + u45:p271 + u45:p272 + u87:p7 + u86:p6 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u37:p183 + u37:p184 + u37:p185 + u37:p186 + u37:p187 + u37:p188 + u37:p189 + u37:p190 + u37:p191 + u37:p192 + u37:p193 + u73:p15 + u74:p14 + u69:p13 + u71:p12 + u91:p11 + u90:p10 + u89:p9 + u88:p8 + u87:p7 + u86:p6 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u49:p303 + u49:p304 + u49:p305 + u49:p306 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u28:p66 + u28:p67 + u28:p68 + u28:p69 + u28:p70 + u28:p71 + u28:p72 + u28:p73 + u28:p74 + u28:p75 + u28:p76 + u93:p24 + u94:p23 + u92:p22 + u82:p21 + u84:p20 + u78:p19 + u80:p18 + u76:p17 + u77:p16 + u73:p15 + u74:p14 + u69:p13 + u71:p12 + u91:p11 + u90:p10 + u89:p9 + u88:p8 + u87:p7 + u86:p6 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u47:p286 + u47:p287 + u47:p288 + u47:p289 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u48:p290 + u48:p291 + u48:p292 + u48:p293 + u48:p294 + u48:p295 + u48:p296 + u48:p297 + u48:p298 + u48:p299 + u48:p300 + u48:p301 + u48:p302 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u59:p393 + u59:p394 + u59:p395 + u59:p396 + u59:p397 + u59:p398 + u59:p399 + u59:p400 + u59:p401 + u59:p402 + u59:p403 + u59:p404 + u59:p405 + u59:p406 + u59:p407 + u59:p408 + u59:p409 + u70:p312 + u72:p311 + u67:p310 + u68:p309 + u65:p308 + u66:p307 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u42:p239 + u42:p240 + u42:p241 + u42:p242 + u42:p243 + u42:p244 + u42:p245 + u42:p246 + u42:p247 + u42:p248 + u42:p249 + u42:p250 + u42:p251 + u90:p10 + u89:p9 + u88:p8 + u87:p7 + u86:p6 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u33:p127 + u33:p128 + u33:p129 + u33:p130 + u33:p131 + u33:p132 + u33:p133 + u33:p134 + u33:p135 + u33:p136 + u33:p137 + u33:p138 + u33:p139 + u33:p140 + u33:p141 + u33:p142 + u33:p143 + u78:p19 + u80:p18 + u76:p17 + u77:p16 + u73:p15 + u74:p14 + u69:p13 + u71:p12 + u91:p11 + u90:p10 + u89:p9 + u88:p8 + u87:p7 + u86:p6 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u63:p461 + u63:p462 + u63:p463 + u63:p464 + u63:p465 + u63:p466 + u63:p467 + u63:p468 + u63:p469 + u63:p470 + u63:p471 + u63:p472 + u63:p473 + u63:p474 + u63:p475 + u63:p476 + u63:p477 + u65:p308 + u66:p307 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u35:p155 + u35:p156 + u35:p157 + u35:p158 + u35:p159 + u35:p160 + u35:p161 + u35:p162 + u35:p163 + u35:p164 + u35:p165 + u76:p17 + u77:p16 + u73:p15 + u74:p14 + u69:p13 + u71:p12 + u91:p11 + u90:p10 + u89:p9 + u88:p8 + u87:p7 + u86:p6 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u62:p444 + u62:p445 + u62:p446 + u62:p447 + u62:p448 + u62:p449 + u62:p450 + u62:p451 + u62:p452 + u62:p453 + u62:p454 + u62:p455 + u62:p456 + u62:p457 + u62:p458 + u62:p459 + u62:p460 + u68:p309 + u65:p308 + u66:p307 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u60:p410 + u60:p411 + u60:p412 + u60:p413 + u60:p414 + u60:p415 + u60:p416 + u60:p417 + u60:p418 + u60:p419 + u60:p420 + u60:p421 + u60:p422 + u60:p423 + u60:p424 + u60:p425 + u60:p426 + u72:p311 + u67:p310 + u68:p309 + u65:p308 + u66:p307 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u31:p105 + u31:p106 + u31:p107 + u31:p108 + u31:p109 + u31:p110 + u31:p111 + u31:p112 + u31:p113 + u31:p114 + u31:p115 + u82:p21 + u84:p20 + u78:p19 + u80:p18 + u76:p17 + u77:p16 + u73:p15 + u74:p14 + u69:p13 + u71:p12 + u91:p11 + u90:p10 + u89:p9 + u88:p8 + u87:p7 + u86:p6 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u36:p166 + u36:p167 + u36:p168 + u36:p169 + u36:p170 + u36:p171 + u36:p172 + u36:p173 + u36:p174 + u36:p175 + u36:p176 + u36:p177 + u36:p178 + u36:p179 + u36:p180 + u36:p181 + u36:p182 + u77:p16 + u73:p15 + u74:p14 + u69:p13 + u71:p12 + u91:p11 + u90:p10 + u89:p9 + u88:p8 + u87:p7 + u86:p6 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u43:p252 + u43:p253 + u43:p254 + u43:p255 + u89:p9 + u88:p8 + u87:p7 + u86:p6 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u44:p256 + u44:p257 + u44:p258 + u44:p259 + u44:p260 + u44:p261 + u44:p262 + u44:p263 + u44:p264 + u44:p265 + u44:p266 + u44:p267 + u44:p268 + u88:p8 + u87:p7 + u86:p6 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u29:p77 + u29:p78 + u29:p79 + u29:p80 + u29:p81 + u29:p82 + u29:p83 + u29:p84 + u29:p85 + u29:p86 + u29:p87 + u94:p23 + u92:p22 + u82:p21 + u84:p20 + u78:p19 + u80:p18 + u76:p17 + u77:p16 + u73:p15 + u74:p14 + u69:p13 + u71:p12 + u91:p11 + u90:p10 + u89:p9 + u88:p8 + u87:p7 + u86:p6 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u40:p222 + u40:p223 + u40:p224 + u40:p225 + u40:p226 + u40:p227 + u40:p228 + u40:p229 + u40:p230 + u40:p231 + u40:p232 + u40:p233 + u40:p234 + u71:p12 + u91:p11 + u90:p10 + u89:p9 + u88:p8 + u87:p7 + u86:p6 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u57:p314 + u57:p315 + u57:p316 + u57:p317 + u57:p318 + u57:p319 + u57:p320 + u57:p321 + u57:p322 + u57:p323 + u57:p324 + u57:p325 + u57:p326 + u57:p327 + u57:p328 + u57:p329 + u57:p330 + u57:p331 + u57:p332 + u57:p333 + u57:p334 + u57:p335 + u57:p336 + u57:p337 + u57:p338 + u57:p339 + u57:p340 + u57:p341 + u57:p342 + u57:p343 + u57:p344 + u57:p345 + u57:p346 + u57:p347 + u57:p348 + u57:p349 + u57:p350 + u57:p351 + u57:p352 + u57:p353 + u57:p354 + u57:p355 + u57:p356 + u57:p357 + u57:p358 + u57:p359 + u57:p360 + u57:p361 + u75:p313 + u70:p312 + u72:p311 + u67:p310 + u68:p309 + u65:p308 + u66:p307 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u34:p144 + u34:p145 + u34:p146 + u34:p147 + u34:p148 + u34:p149 + u34:p150 + u34:p151 + u34:p152 + u34:p153 + u34:p154 + u80:p18 + u76:p17 + u77:p16 + u73:p15 + u74:p14 + u69:p13 + u71:p12 + u91:p11 + u90:p10 + u89:p9 + u88:p8 + u87:p7 + u86:p6 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u30:p88 + u30:p89 + u30:p90 + u30:p91 + u30:p92 + u30:p93 + u30:p94 + u30:p95 + u30:p96 + u30:p97 + u30:p98 + u30:p99 + u30:p100 + u30:p101 + u30:p102 + u30:p103 + u30:p104 + u92:p22 + u82:p21 + u84:p20 + u78:p19 + u80:p18 + u76:p17 + u77:p16 + u73:p15 + u74:p14 + u69:p13 + u71:p12 + u91:p11 + u90:p10 + u89:p9 + u88:p8 + u87:p7 + u86:p6 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u41:p235 + u41:p236 + u41:p237 + u41:p238 + u91:p11 + u90:p10 + u89:p9 + u88:p8 + u87:p7 + u86:p6 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :-1'u57:p316 + -1'u57:p317 + -1'u57:p318 + -1'u57:p319 + -1'u57:p320 + -1'u57:p321 + -1'u57:p322 + -1'u57:p323 + -1'u57:p324 + -1'u57:p325 + -1'u57:p326 + -1'u57:p327 + -1'u57:p328 + -1'u57:p329 + -1'u57:p330 + -1'u57:p331 + -1'u57:p332 + -1'u57:p333 + -1'u57:p334 + -1'u57:p335 + -1'u57:p336 + -1'u57:p337 + -1'u57:p338 + -1'u57:p339 + -1'u57:p340 + -1'u57:p341 + -1'u57:p342 + -1'u57:p343 + -1'u58:p364 + -1'u58:p365 + -1'u58:p366 + -1'u58:p367 + -1'u58:p368 + -1'u58:p369 + -1'u58:p370 + -1'u58:p371 + -1'u58:p372 + -1'u58:p373 + -1'u58:p374 + -1'u58:p375 + -1'u58:p376 + -1'u58:p377 + -1'u58:p378 + -1'u58:p379 + -1'u58:p380 + -1'u58:p381 + -1'u58:p382 + -1'u58:p383 + -1'u58:p384 + -1'u58:p385 + -1'u58:p386 + -1'u59:p395 + -1'u59:p396 + -1'u59:p397 + -1'u59:p398 + -1'u59:p399 + -1'u59:p400 + -1'u59:p401 + -1'u60:p412 + -1'u60:p413 + -1'u60:p414 + -1'u60:p415 + -1'u60:p416 + -1'u60:p417 + -1'u60:p418 + -1'u61:p429 + -1'u61:p430 + -1'u61:p431 + -1'u61:p432 + -1'u61:p433 + -1'u61:p434 + -1'u61:p435 + -1'u62:p446 + -1'u62:p447 + -1'u62:p448 + -1'u62:p449 + -1'u62:p450 + -1'u62:p451 + -1'u62:p452 + -1'u63:p463 + -1'u63:p464 + -1'u63:p465 + -1'u63:p466 + -1'u63:p467 + -1'u63:p468 + -1'u63:p469 + u64:p480 + u64:p481 = 0
invariant :u27:p49 + u27:p50 + u27:p51 + u27:p52 + u27:p53 + u27:p54 + u27:p55 + u27:p56 + u27:p57 + u27:p58 + u27:p59 + u27:p60 + u27:p61 + u27:p62 + u27:p63 + u27:p64 + u27:p65 + u96:p25 + u93:p24 + u94:p23 + u92:p22 + u82:p21 + u84:p20 + u78:p19 + u80:p18 + u76:p17 + u77:p16 + u73:p15 + u74:p14 + u69:p13 + u71:p12 + u91:p11 + u90:p10 + u89:p9 + u88:p8 + u87:p7 + u86:p6 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u46:p273 + u46:p274 + u46:p275 + u46:p276 + u46:p277 + u46:p278 + u46:p279 + u46:p280 + u46:p281 + u46:p282 + u46:p283 + u46:p284 + u46:p285 + u86:p6 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u38:p194 + u38:p195 + u38:p196 + u38:p197 + u38:p198 + u38:p199 + u38:p200 + u38:p201 + u38:p202 + u38:p203 + u38:p204 + u74:p14 + u69:p13 + u71:p12 + u91:p11 + u90:p10 + u89:p9 + u88:p8 + u87:p7 + u86:p6 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u32:p116 + u32:p117 + u32:p118 + u32:p119 + u32:p120 + u32:p121 + u32:p122 + u32:p123 + u32:p124 + u32:p125 + u32:p126 + u84:p20 + u78:p19 + u80:p18 + u76:p17 + u77:p16 + u73:p15 + u74:p14 + u69:p13 + u71:p12 + u91:p11 + u90:p10 + u89:p9 + u88:p8 + u87:p7 + u86:p6 + u85:p5 + u83:p4 + u81:p3 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u58:p362 + u58:p363 + u58:p364 + u58:p365 + u58:p366 + u58:p367 + u58:p368 + u58:p369 + u58:p370 + u58:p371 + u58:p372 + u58:p373 + u58:p374 + u58:p375 + u58:p376 + u58:p377 + u58:p378 + u58:p379 + u58:p380 + u58:p381 + u58:p382 + u58:p383 + u58:p384 + u58:p385 + u58:p386 + u58:p387 + u58:p388 + u58:p389 + u58:p390 + u58:p391 + u58:p392 + u75:p313 + u70:p312 + u72:p311 + u67:p310 + u68:p309 + u65:p308 + u66:p307 + u79:p0 + u79:p1 + u79:p2 = 1
invariant :u61:p427 + u61:p428 + u61:p429 + u61:p430 + u61:p431 + u61:p432 + u61:p433 + u61:p434 + u61:p435 + u61:p436 + u61:p437 + u61:p438 + u61:p439 + u61:p440 + u61:p441 + u61:p442 + u61:p443 + u67:p310 + u68:p309 + u65:p308 + u66:p307 + u79:p0 + u79:p1 + u79:p2 = 1
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 11123 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 112 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP0==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1009 ms.
FORMULA AutoFlight-PT-05b-LTLFireability-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, [](<>([]([]([]((LTLAP1==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 981 ms.
FORMULA AutoFlight-PT-05b-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ([]([](X((LTLAP2==true)))))U(<>((LTLAP3==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 310 ms.
FORMULA AutoFlight-PT-05b-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (<>([](<>((LTLAP4==true)))))U(((LTLAP5==true))U(X((LTLAP6==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (<>([](<>((LTLAP4==true)))))U(((LTLAP5==true))U(X((LTLAP6==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((LTLAP7==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1175 ms.
FORMULA AutoFlight-PT-05b-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP8==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 311 ms.
FORMULA AutoFlight-PT-05b-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ([](((LTLAP9==true))U((LTLAP10==true))))U([](((LTLAP11==true))U((LTLAP12==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 992 ms.
FORMULA AutoFlight-PT-05b-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>(<>(<>((LTLAP13==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>(<>(<>((LTLAP13==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP14==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1038 ms.
FORMULA AutoFlight-PT-05b-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP15==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1039 ms.
FORMULA AutoFlight-PT-05b-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](<>(X(X((LTLAP16==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](<>(X(X((LTLAP16==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(<>(<>(<>([]((LTLAP17==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1031 ms.
FORMULA AutoFlight-PT-05b-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((((LTLAP18==true))U((LTLAP19==true)))U(X(<>((LTLAP20==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((((LTLAP18==true))U((LTLAP19==true)))U(X(<>((LTLAP20==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>([](<>([](<>((LTLAP21==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1000 ms.
FORMULA AutoFlight-PT-05b-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X(<>(X((LTLAP22==true)))))U(((LTLAP23==true))U(<>((LTLAP24==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X(<>(X((LTLAP22==true)))))U(((LTLAP23==true))U(<>((LTLAP24==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP25==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread failed on error :java.lang.RuntimeException: Unexpected exception when executing ltsmin :CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP25==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
255
Reverse transition relation is NOT exact ! Due to transitions t157, t173, t189, t205, t221, t466, t467, t468, t469, t470, t471, t472, u25.t0, u25.t1, u25.t2, u25.t393, u25.t400, u26.t3, u26.t4, u26.t5, u26.t384, u26.t391, u27.t6, u27.t7, u27.t8, u27.t9, u27.t373, u27.t381, u28.t10, u28.t11, u28.t12, u28.t361, u28.t368, u29.t13, u29.t14, u29.t15, u29.t351, u29.t358, u30.t16, u30.t17, u30.t18, u30.t19, u30.t340, u30.t348, u31.t20, u31.t21, u31.t22, u31.t328, u31.t335, u32.t23, u32.t24, u32.t25, u32.t318, u32.t325, u33.t26, u33.t27, u33.t28, u33.t29, u33.t307, u33.t315, u34.t30, u34.t31, u34.t32, u34.t295, u34.t302, u35.t33, u35.t34, u35.t35, u35.t285, u35.t292, u36.t36, u36.t37, u36.t38, u36.t39, u36.t274, u36.t282, u37.t40, u37.t41, u37.t42, u37.t262, u37.t269, u38.t43, u38.t44, u38.t45, u38.t252, u38.t259, u39.t46, u39.t47, u39.t48, u39.t49, u39.t241, u39.t249, u40.t226, u40.t236, u41.t223, u42.t210, u42.t220, u43.t207, u44.t194, u44.t204, u45.t191, u46.t178, u46.t188, u47.t175, u48.t162, u48.t172, u49.t159, u57.t153, u57.t156, u58.t132, u58.t135, u59.t122, u59.t125, u60.t110, u60.t113, u61.t98, u61.t101, u62.t86, u62.t89, u63.t74, u63.t77, u64.t65, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :0/358/122/480
Computing Next relation with stutter on 800 deadlock states
3 unique states visited
3 strongly connected components in search stack
3 transitions explored
3 items max in DFS search stack
243199 ticks for the emptiness check
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
STATS,0,2432.21,14773124,1,0,3.18255e+07,60721,1523,5.49158e+07,1002,396022,45804266
an accepting run exists (use option '-e' to print it)
Formula 0 is FALSE accepting run found.
FORMULA AutoFlight-PT-05b-LTLFireability-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Checking formula 1 : !((G(F(G(G(G("(u29.p78>=1)")))))))
Formula 1 simplified : !GFG"(u29.p78>=1)"
terminate called after throwing an instance of 'std::bad_alloc'
what(): std::bad_alloc

BK_STOP 1527409070514

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 27, 2018 7:34:17 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 27, 2018 7:34:17 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 27, 2018 7:34:17 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 140 ms
May 27, 2018 7:34:17 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 482 places.
May 27, 2018 7:34:17 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 480 transitions.
May 27, 2018 7:34:17 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 27, 2018 7:34:17 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 32 ms
May 27, 2018 7:34:18 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 27, 2018 7:34:18 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 27, 2018 7:34:18 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 126 ms
May 27, 2018 7:34:18 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 27, 2018 7:34:18 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 12 redundant transitions.
May 27, 2018 7:34:18 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 18 ms
May 27, 2018 7:34:18 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 1 ms
May 27, 2018 7:34:19 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 480 transitions.
May 27, 2018 7:34:20 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 34 place invariants in 218 ms
May 27, 2018 7:34:22 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 482 variables to be positive in 2077 ms
May 27, 2018 7:34:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 480 transitions.
May 27, 2018 7:34:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/480 took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 27, 2018 7:34:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 60 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 27, 2018 7:34:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 480 transitions.
May 27, 2018 7:34:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 15 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 27, 2018 7:34:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 480 transitions.
May 27, 2018 7:34:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/480) took 1230 ms. Total solver calls (SAT/UNSAT): 478(0/478)
May 27, 2018 7:34:30 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(10/480) took 4818 ms. Total solver calls (SAT/UNSAT): 2447(0/2447)
May 27, 2018 7:34:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(18/480) took 8148 ms. Total solver calls (SAT/UNSAT): 4787(0/4787)
SMT solver raised 'unknown', retrying with same input.
May 27, 2018 7:34:36 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(33/480) took 11237 ms. Total solver calls (SAT/UNSAT): 6752(2/6750)
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown' twice, overapproximating result to 1.
May 27, 2018 7:34:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 13219 ms. Total solver calls (SAT/UNSAT): 6937(7/6930)
May 27, 2018 7:34:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 480 transitions.
May 27, 2018 7:34:40 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 1793 ms. Total solver calls (SAT/UNSAT): 660(0/660)
May 27, 2018 7:34:40 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 21650ms conformant to PINS in folder :/home/mcc/execution
pins2lts-mc, 0.000: Registering PINS so language module
pins2lts-mc, 0.000, ** error **: out of memory trying to get 4294967296
java.lang.RuntimeException: Unexpected exception when executing ltsmin :CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP25==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
255
at fr.lip6.move.gal.application.LTSminRunner.checkProperty(LTSminRunner.java:167)
at fr.lip6.move.gal.application.LTSminRunner.access$9(LTSminRunner.java:122)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:91)
at java.lang.Thread.run(Thread.java:748)
ITS-tools command line returned an error code 134

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AutoFlight-PT-05b"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/AutoFlight-PT-05b.tgz
mv AutoFlight-PT-05b execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is AutoFlight-PT-05b, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r200-qhx1-152732197100034"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;