Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.............................................................................................................................
/home/mcc/execution
total 400K
-rw-r--r-- 1 mcc users 5.9K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 30K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 31K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.2K May 26 09:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 14K May 26 09:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.1K May 26 09:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K May 26 09:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.1K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 33K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 116 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 354 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 5.0K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 26K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.6K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 6.3K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 3 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 153K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is QuasiCertifProtocol-PT-06, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r188-qhx2-152732140200058
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME QuasiCertifProtocol-PT-06-LTLFireability-00
FORMULA_NAME QuasiCertifProtocol-PT-06-LTLFireability-01
FORMULA_NAME QuasiCertifProtocol-PT-06-LTLFireability-02
FORMULA_NAME QuasiCertifProtocol-PT-06-LTLFireability-03
FORMULA_NAME QuasiCertifProtocol-PT-06-LTLFireability-04
FORMULA_NAME QuasiCertifProtocol-PT-06-LTLFireability-05
FORMULA_NAME QuasiCertifProtocol-PT-06-LTLFireability-06
FORMULA_NAME QuasiCertifProtocol-PT-06-LTLFireability-07
FORMULA_NAME QuasiCertifProtocol-PT-06-LTLFireability-08
FORMULA_NAME QuasiCertifProtocol-PT-06-LTLFireability-09
FORMULA_NAME QuasiCertifProtocol-PT-06-LTLFireability-10
FORMULA_NAME QuasiCertifProtocol-PT-06-LTLFireability-11
FORMULA_NAME QuasiCertifProtocol-PT-06-LTLFireability-12
FORMULA_NAME QuasiCertifProtocol-PT-06-LTLFireability-13
FORMULA_NAME QuasiCertifProtocol-PT-06-LTLFireability-14
FORMULA_NAME QuasiCertifProtocol-PT-06-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1528284999309

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((X(G((G("((((((((((((((n8_4_6>=1)&&(n8_4_5>=1))&&(n8_4_4>=1))&&(n8_4_3>=1))&&(n8_4_2>=1))&&(n8_4_1>=1))&&(n8_4_0>=1))&&(s5_4>=1))||((((((((n8_3_3>=1)&&(n8_3_4>=1))&&(n8_3_5>=1))&&(n8_3_6>=1))&&(s5_3>=1))&&(n8_3_0>=1))&&(n8_3_1>=1))&&(n8_3_2>=1)))||((((((((n8_6_6>=1)&&(n8_6_4>=1))&&(n8_6_5>=1))&&(n8_6_2>=1))&&(n8_6_3>=1))&&(n8_6_0>=1))&&(n8_6_1>=1))&&(s5_6>=1)))||((((((((n8_5_4>=1)&&(n8_5_3>=1))&&(n8_5_2>=1))&&(n8_5_1>=1))&&(n8_5_0>=1))&&(s5_5>=1))&&(n8_5_5>=1))&&(n8_5_6>=1)))||((((((((n8_0_1>=1)&&(n8_0_0>=1))&&(s5_0>=1))&&(n8_0_6>=1))&&(n8_0_3>=1))&&(n8_0_2>=1))&&(n8_0_5>=1))&&(n8_0_4>=1)))||((((((((s5_2>=1)&&(n8_2_4>=1))&&(n8_2_5>=1))&&(n8_2_6>=1))&&(n8_2_0>=1))&&(n8_2_1>=1))&&(n8_2_2>=1))&&(n8_2_3>=1)))||((((((((n8_1_6>=1)&&(n8_1_5>=1))&&(n8_1_2>=1))&&(n8_1_1>=1))&&(n8_1_4>=1))&&(n8_1_3>=1))&&(n8_1_0>=1))&&(s5_1>=1)))"))U(F("((((((((malicious_reservoir>=1)&&(s6_3>=1))||((malicious_reservoir>=1)&&(s6_2>=1)))||((s6_1>=1)&&(malicious_reservoir>=1)))||((malicious_reservoir>=1)&&(s6_0>=1)))||((malicious_reservoir>=1)&&(s6_6>=1)))||((malicious_reservoir>=1)&&(s6_5>=1)))||((malicious_reservoir>=1)&&(s6_4>=1)))"))))))
Formula 0 simplified : !XG(G"((((((((((((((n8_4_6>=1)&&(n8_4_5>=1))&&(n8_4_4>=1))&&(n8_4_3>=1))&&(n8_4_2>=1))&&(n8_4_1>=1))&&(n8_4_0>=1))&&(s5_4>=1))||((((((((n8_3_3>=1)&&(n8_3_4>=1))&&(n8_3_5>=1))&&(n8_3_6>=1))&&(s5_3>=1))&&(n8_3_0>=1))&&(n8_3_1>=1))&&(n8_3_2>=1)))||((((((((n8_6_6>=1)&&(n8_6_4>=1))&&(n8_6_5>=1))&&(n8_6_2>=1))&&(n8_6_3>=1))&&(n8_6_0>=1))&&(n8_6_1>=1))&&(s5_6>=1)))||((((((((n8_5_4>=1)&&(n8_5_3>=1))&&(n8_5_2>=1))&&(n8_5_1>=1))&&(n8_5_0>=1))&&(s5_5>=1))&&(n8_5_5>=1))&&(n8_5_6>=1)))||((((((((n8_0_1>=1)&&(n8_0_0>=1))&&(s5_0>=1))&&(n8_0_6>=1))&&(n8_0_3>=1))&&(n8_0_2>=1))&&(n8_0_5>=1))&&(n8_0_4>=1)))||((((((((s5_2>=1)&&(n8_2_4>=1))&&(n8_2_5>=1))&&(n8_2_6>=1))&&(n8_2_0>=1))&&(n8_2_1>=1))&&(n8_2_2>=1))&&(n8_2_3>=1)))||((((((((n8_1_6>=1)&&(n8_1_5>=1))&&(n8_1_2>=1))&&(n8_1_1>=1))&&(n8_1_4>=1))&&(n8_1_3>=1))&&(n8_1_0>=1))&&(s5_1>=1)))" U F"((((((((malicious_reservoir>=1)&&(s6_3>=1))||((malicious_reservoir>=1)&&(s6_2>=1)))||((s6_1>=1)&&(malicious_reservoir>=1)))||((malicious_reservoir>=1)&&(s6_0>=1)))||((malicious_reservoir>=1)&&(s6_6>=1)))||((malicious_reservoir>=1)&&(s6_5>=1)))||((malicious_reservoir>=1)&&(s6_4>=1)))")
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 116 rows 270 cols
invariant :n7_6_0 + -1'n7_6_6 + n8_4_0 + -1'n8_4_5 + -1'n8_0_6 + n8_0_5 = 0
invariant :malicious_reservoir + CstopAbort + -1's6_0 + -1's6_1 + -1's6_2 + -1's6_3 + -1's6_5 + -1's6_4 + -1's6_6 + -1's5_1 + -1's5_0 + -1's5_3 + -1's5_2 + -1's5_5 + -1's5_4 + -1's4_0 + -1's5_6 + -1's4_2 + -1's4_1 + -1's4_4 + -1's4_3 + -1's3_0 + -1's3_1 + -1's4_5 + -1's4_6 + -1's3_4 + -1's3_5 + -1's3_2 + -1's3_3 + -1's2_1 + -1's2_2 + -1's3_6 + -1's2_0 + -1's2_5 + -1's2_6 + -1's2_3 + -1's2_4 + -1'Sstart_3 + -1'Sstart_2 + -1'Sstart_1 + -1'Sstart_0 + -1'Sstart_6 + -1'Sstart_5 + -1'Sstart_4 + -1'SstopOK_2 + -1'SstopOK_3 + -1'SstopOK_0 + -1'SstopOK_1 + -1'SstopOK_6 + -1'SstopOK_4 + -1'SstopOK_5 = -4
invariant :n9_5_6 + CstopOK_6 + -1'SstopOK_5 = 0
invariant :n7_0_2 + -1'n7_0_4 + -1'n8_1_4 + n8_5_2 + -1'n8_5_5 + n8_1_5 = 0
invariant :n2_4 + -1'n2_2 + n1_4 + -1'n1_2 = 0
invariant :n9_4_1 + CstopOK_1 + -1'SstopOK_4 = 0
invariant :n9_2_1 + CstopOK_1 + -1'SstopOK_2 = 0
invariant :n9_5_2 + CstopOK_2 + -1'SstopOK_5 = 0
invariant :n3_3 + n4_3 + -1'n4_4 + -1'n3_4 = 0
invariant :n7_4_2 + -1'n7_4_6 + n8_5_2 + -1'n8_5_5 + -1'n8_0_6 + n8_0_5 = 0
invariant :n7_4_0 + -1'n7_4_6 + n8_4_0 + -1'n8_4_5 + -1'n8_0_6 + n8_0_5 = 0
invariant :n7_3_1 + -1'n7_3_6 + n8_1_1 + -1'n8_0_6 + n8_0_5 + -1'n8_1_5 = 0
invariant :n8_4_6 + -1'n8_4_5 + -1'n8_0_6 + n8_0_5 = 0
invariant :n4_5 + -1'n4_4 + -1'n3_4 + n3_5 = 0
invariant :n7_5_3 + -1'n7_5_6 + n8_0_3 + -1'n8_0_6 = 0
invariant :n7_6_2 + -1'n7_6_6 + n8_5_2 + -1'n8_5_5 + -1'n8_0_6 + n8_0_5 = 0
invariant :n8_6_2 + -1'n8_5_2 + n8_5_5 + -1'n8_6_5 = 0
invariant :n8_2_1 + -1'n8_1_1 + n8_1_5 + -1'n8_2_5 = 0
invariant :n7_6_1 + -1'n7_6_6 + n8_1_1 + -1'n8_0_6 + n8_0_5 + -1'n8_1_5 = 0
invariant :n5_3 + -1'n5_6 + -1'n6_6 + n6_3 = 0
invariant :n9_0_6 + CstopOK_6 + -1'SstopOK_0 = 0
invariant :Cstart_1 + -1'Cstart_0 + -1'n8_4_0 + n8_1_1 + n8_4_5 + -1'n8_1_5 = 0
invariant :n8_4_4 + -1'n8_1_4 + -1'n8_4_5 + n8_1_5 = 0
invariant :n3_0 + -1'n4_4 + n4_0 + -1'n3_4 = 0
invariant :n9_6_6 + CstopOK_6 + -1'SstopOK_6 = 0
invariant :n9_5_5 + CstopOK_5 + -1'SstopOK_5 = 0
invariant :Cstart_4 + -1'Cstart_0 + -1'n8_4_0 + n8_1_4 + n8_4_5 + -1'n8_1_5 = 0
invariant :n8_3_2 + -1'n8_5_2 + n8_5_5 + -1'n8_3_5 = 0
invariant :n9_2_3 + CstopOK_3 + -1'SstopOK_2 = 0
invariant :n8_3_3 + -1'n8_0_3 + n8_0_5 + -1'n8_3_5 = 0
invariant :n7_3_2 + -1'n7_3_6 + n8_5_2 + -1'n8_5_5 + -1'n8_0_6 + n8_0_5 = 0
invariant :n8_5_6 + -1'n8_5_5 + -1'n8_0_6 + n8_0_5 = 0
invariant :n8_1_0 + -1'n8_4_0 + n8_4_5 + -1'n8_1_5 = 0
invariant :n8_1_3 + -1'n8_0_3 + n8_0_5 + -1'n8_1_5 = 0
invariant :n9_6_1 + CstopOK_1 + -1'SstopOK_6 = 0
invariant :n2_6 + -1'n2_2 + n1_6 + -1'n1_2 = 0
invariant :n7_6_5 + -1'n7_6_6 + -1'n8_0_6 + n8_0_5 = 0
invariant :n8_1_2 + -1'n8_5_2 + n8_5_5 + -1'n8_1_5 = 0
invariant :n9_3_2 + CstopOK_2 + -1'SstopOK_3 = 0
invariant :n8_5_0 + -1'n8_4_0 + n8_4_5 + -1'n8_5_5 = 0
invariant :n7_0_6 + -1'n7_0_4 + -1'n8_1_4 + n8_0_6 + -1'n8_0_5 + n8_1_5 = 0
invariant :n9_0_2 + CstopOK_2 + -1'SstopOK_0 = 0
invariant :n9_0_5 + CstopOK_5 + -1'SstopOK_0 = 0
invariant :n9_1_1 + CstopOK_1 + -1'SstopOK_1 = 0
invariant :n8_0_0 + -1'n8_4_0 + n8_4_5 + -1'n8_0_5 = 0
invariant :n7_3_5 + -1'n7_3_6 + -1'n8_0_6 + n8_0_5 = 0
invariant :n8_2_4 + -1'n8_1_4 + n8_1_5 + -1'n8_2_5 = 0
invariant :n8_2_3 + -1'n8_0_3 + n8_0_5 + -1'n8_2_5 = 0
invariant :n7_2_3 + -1'n7_2_6 + n8_0_3 + -1'n8_0_6 = 0
invariant :n8_3_0 + -1'n8_4_0 + n8_4_5 + -1'n8_3_5 = 0
invariant :n7_5_1 + -1'n7_5_6 + n8_1_1 + -1'n8_0_6 + n8_0_5 + -1'n8_1_5 = 0
invariant :n7_4_3 + -1'n7_4_6 + n8_0_3 + -1'n8_0_6 = 0
invariant :n5_5 + -1'n5_6 + n6_5 + -1'n6_6 = 0
invariant :n7_2_2 + -1'n7_2_6 + n8_5_2 + -1'n8_5_5 + -1'n8_0_6 + n8_0_5 = 0
invariant :n7_2_4 + -1'n7_2_6 + n8_1_4 + -1'n8_0_6 + n8_0_5 + -1'n8_1_5 = 0
invariant :n7_1_1 + -1'n7_1_6 + n8_1_1 + -1'n8_0_6 + n8_0_5 + -1'n8_1_5 = 0
invariant :Cstart_6 + -1'Cstart_0 + -1'n8_4_0 + n8_4_5 + n8_0_6 + -1'n8_0_5 = 0
invariant :Cstart_2 + -1'Cstart_0 + -1'n8_4_0 + n8_5_2 + n8_4_5 + -1'n8_5_5 = 0
invariant :n9_2_5 + CstopOK_5 + -1'SstopOK_2 = 0
invariant :n9_3_6 + CstopOK_6 + -1'SstopOK_3 = 0
invariant :n9_6_4 + CstopOK_4 + -1'SstopOK_6 = 0
invariant :n8_3_1 + -1'n8_1_1 + n8_1_5 + -1'n8_3_5 = 0
invariant :n7_5_5 + -1'n7_5_6 + -1'n8_0_6 + n8_0_5 = 0
invariant :n9_3_1 + CstopOK_1 + -1'SstopOK_3 = 0
invariant :n7_0_1 + -1'n7_0_4 + n8_1_1 + -1'n8_1_4 = 0
invariant :n9_6_5 + CstopOK_5 + -1'SstopOK_6 = 0
invariant :n7_3_0 + -1'n7_3_6 + n8_4_0 + -1'n8_4_5 + -1'n8_0_6 + n8_0_5 = 0
invariant :n8_2_6 + -1'n8_0_6 + n8_0_5 + -1'n8_2_5 = 0
invariant :n9_6_3 + CstopOK_3 + -1'SstopOK_6 = 0
invariant :n7_0_5 + -1'n7_0_4 + -1'n8_1_4 + n8_1_5 = 0
invariant :n9_1_3 + CstopOK_3 + -1'SstopOK_1 = 0
invariant :Cstart_3 + -1'Cstart_0 + -1'n8_4_0 + n8_0_3 + n8_4_5 + -1'n8_0_5 = 0
invariant :n5_2 + n6_2 + -1'n5_6 + -1'n6_6 = 0
invariant :n9_0_4 + CstopOK_4 + -1'SstopOK_0 = 0
invariant :n7_0_0 + -1'n7_0_4 + n8_4_0 + -1'n8_1_4 + -1'n8_4_5 + n8_1_5 = 0
invariant :n9_3_0 + CstopOK_0 + -1'SstopOK_3 = 0
invariant :n8_5_1 + -1'n8_1_1 + -1'n8_5_5 + n8_1_5 = 0
invariant :n8_3_4 + -1'n8_1_4 + n8_1_5 + -1'n8_3_5 = 0
invariant :n8_1_6 + -1'n8_0_6 + n8_0_5 + -1'n8_1_5 = 0
invariant :n5_4 + -1'n5_6 + -1'n6_6 + n6_4 = 0
invariant :n7_3_4 + -1'n7_3_6 + n8_1_4 + -1'n8_0_6 + n8_0_5 + -1'n8_1_5 = 0
invariant :n9_1_0 + CstopOK_0 + -1'SstopOK_1 = 0
invariant :n8_0_4 + -1'n8_1_4 + -1'n8_0_5 + n8_1_5 = 0
invariant :n9_0_0 + CstopOK_0 + -1'SstopOK_0 = 0
invariant :n2_3 + -1'n2_2 + n1_3 + -1'n1_2 = 0
invariant :n9_4_4 + CstopOK_4 + -1'SstopOK_4 = 0
invariant :n7_5_4 + -1'n7_5_6 + n8_1_4 + -1'n8_0_6 + n8_0_5 + -1'n8_1_5 = 0
invariant :n9_1_4 + CstopOK_4 + -1'SstopOK_1 = 0
invariant :n7_2_1 + -1'n7_2_6 + n8_1_1 + -1'n8_0_6 + n8_0_5 + -1'n8_1_5 = 0
invariant :n4_6 + -1'n4_4 + n3_6 + -1'n3_4 = 0
invariant :n9_2_4 + CstopOK_4 + -1'SstopOK_2 = 0
invariant :c1_0 + c1_1 + c1_2 + c1_3 + c1_4 + c1_5 + c1_6 + CstopAbort + CstopOK_0 + CstopOK_1 + CstopOK_6 + CstopOK_5 + CstopOK_4 + CstopOK_3 + CstopOK_2 + 7'Cstart_0 + 6'n8_4_0 + -1'n8_1_1 + -1'n8_1_4 + -1'n8_5_2 + -1'n8_0_3 + -6'n8_4_5 + n8_5_5 + -1'n8_0_6 + 2'n8_0_5 + 2'n8_1_5 = 7
invariant :n3_2 + -1'n4_4 + n4_2 + -1'n3_4 = 0
invariant :n5_1 + n6_1 + -1'n5_6 + -1'n6_6 = 0
invariant :n9_3_3 + CstopOK_3 + -1'SstopOK_3 = 0
invariant :n9_4_2 + CstopOK_2 + -1'SstopOK_4 = 0
invariant :n7_1_4 + -1'n7_1_6 + n8_1_4 + -1'n8_0_6 + n8_0_5 + -1'n8_1_5 = 0
invariant :Cstart_5 + -1'Cstart_0 + -1'n8_4_0 + n8_4_5 = 0
invariant :n9_4_3 + CstopOK_3 + -1'SstopOK_4 = 0
invariant :n8_0_1 + -1'n8_1_1 + -1'n8_0_5 + n8_1_5 = 0
invariant :n9_6_0 + CstopOK_0 + -1'SstopOK_6 = 0
invariant :a5 + a2 + a4 + a3 + AstopAbort + a1 + Astart + AstopOK = 1
invariant :n9_0_3 + CstopOK_3 + -1'SstopOK_0 = 0
invariant :n5_0 + -1'n5_6 + n6_0 + -1'n6_6 = 0
invariant :n9_5_0 + CstopOK_0 + -1'SstopOK_5 = 0
invariant :n9_1_2 + CstopOK_2 + -1'SstopOK_1 = 0
invariant :n7_1_2 + -1'n7_1_6 + n8_5_2 + -1'n8_5_5 + -1'n8_0_6 + n8_0_5 = 0
invariant :n8_6_4 + -1'n8_1_4 + -1'n8_6_5 + n8_1_5 = 0
invariant :n9_2_0 + CstopOK_0 + -1'SstopOK_2 = 0
invariant :n8_6_1 + -1'n8_1_1 + -1'n8_6_5 + n8_1_5 = 0
invariant :n9_2_6 + CstopOK_6 + -1'SstopOK_2 = 0
invariant :n2_5 + -1'n2_2 + n1_5 + -1'n1_2 = 0
invariant :n8_2_0 + -1'n8_4_0 + n8_4_5 + -1'n8_2_5 = 0
invariant :n9_3_4 + CstopOK_4 + -1'SstopOK_3 = 0
invariant :n7_2_5 + -1'n7_2_6 + -1'n8_0_6 + n8_0_5 = 0
invariant :n7_6_4 + -1'n7_6_6 + n8_1_4 + -1'n8_0_6 + n8_0_5 + -1'n8_1_5 = 0
invariant :n7_6_3 + -1'n7_6_6 + n8_0_3 + -1'n8_0_6 = 0
invariant :n8_3_6 + -1'n8_0_6 + n8_0_5 + -1'n8_3_5 = 0
invariant :n8_6_6 + -1'n8_6_5 + -1'n8_0_6 + n8_0_5 = 0
invariant :n8_5_4 + -1'n8_1_4 + -1'n8_5_5 + n8_1_5 = 0
invariant :n9_6_2 + CstopOK_2 + -1'SstopOK_6 = 0
invariant :n7_1_5 + -1'n7_1_6 + -1'n8_0_6 + n8_0_5 = 0
invariant :n9_4_5 + CstopOK_5 + -1'SstopOK_4 = 0
invariant :n8_5_3 + -1'n8_0_3 + -1'n8_5_5 + n8_0_5 = 0
invariant :n7_4_4 + -1'n7_4_6 + n8_1_4 + -1'n8_0_6 + n8_0_5 + -1'n8_1_5 = 0
invariant :n9_1_5 + CstopOK_5 + -1'SstopOK_1 = 0
invariant :n7_1_3 + -1'n7_1_6 + n8_0_3 + -1'n8_0_6 = 0
invariant :n8_6_3 + -1'n8_0_3 + -1'n8_6_5 + n8_0_5 = 0
invariant :n9_4_6 + CstopOK_6 + -1'SstopOK_4 = 0
invariant :n8_2_2 + -1'n8_5_2 + n8_5_5 + -1'n8_2_5 = 0
invariant :n9_5_4 + CstopOK_4 + -1'SstopOK_5 = 0
invariant :n9_0_1 + CstopOK_1 + -1'SstopOK_0 = 0
invariant :n8_4_3 + -1'n8_0_3 + -1'n8_4_5 + n8_0_5 = 0
invariant :n7_5_0 + -1'n7_5_6 + n8_4_0 + -1'n8_4_5 + -1'n8_0_6 + n8_0_5 = 0
invariant :n8_4_1 + -1'n8_1_1 + -1'n8_4_5 + n8_1_5 = 0
invariant :n7_2_0 + -1'n7_2_6 + n8_4_0 + -1'n8_4_5 + -1'n8_0_6 + n8_0_5 = 0
invariant :n7_5_2 + -1'n7_5_6 + n8_5_2 + -1'n8_5_5 + -1'n8_0_6 + n8_0_5 = 0
invariant :n1_1 + -1'n2_2 + n2_1 + -1'n1_2 = 0
invariant :n3_1 + -1'n4_4 + n4_1 + -1'n3_4 = 0
invariant :n7_4_1 + -1'n7_4_6 + n8_1_1 + -1'n8_0_6 + n8_0_5 + -1'n8_1_5 = 0
invariant :n9_2_2 + CstopOK_2 + -1'SstopOK_2 = 0
invariant :n7_4_5 + -1'n7_4_6 + -1'n8_0_6 + n8_0_5 = 0
invariant :n7_0_3 + -1'n7_0_4 + -1'n8_1_4 + n8_0_3 + -1'n8_0_5 + n8_1_5 = 0
invariant :n8_0_2 + -1'n8_5_2 + n8_5_5 + -1'n8_0_5 = 0
invariant :n1_0 + -1'n2_2 + n2_0 + -1'n1_2 = 0
invariant :n9_3_5 + CstopOK_5 + -1'SstopOK_3 = 0
invariant :n8_6_0 + -1'n8_4_0 + n8_4_5 + -1'n8_6_5 = 0
invariant :s6_0 + s6_1 + s6_2 + s6_3 + s6_5 + s6_4 + SstopAbort + s6_6 + s5_1 + s5_0 + s5_3 + s5_2 + s5_5 + s5_4 + s4_0 + s5_6 + s4_2 + s4_1 + s4_4 + s4_3 + s3_0 + s3_1 + s4_5 + s4_6 + s3_4 + s3_5 + s3_2 + s3_3 + s2_1 + s2_2 + s3_6 + s2_0 + s2_5 + s2_6 + s2_3 + s2_4 + Sstart_3 + Sstart_2 + Sstart_1 + Sstart_0 + Sstart_6 + Sstart_5 + Sstart_4 + SstopOK_2 + SstopOK_3 + SstopOK_0 + SstopOK_1 + SstopOK_6 + SstopOK_4 + SstopOK_5 = 7
invariant :n9_1_6 + CstopOK_6 + -1'SstopOK_1 = 0
invariant :n9_5_3 + CstopOK_3 + -1'SstopOK_5 = 0
invariant :n9_4_0 + CstopOK_0 + -1'SstopOK_4 = 0
invariant :n7_1_0 + -1'n7_1_6 + n8_4_0 + -1'n8_4_5 + -1'n8_0_6 + n8_0_5 = 0
invariant :n8_4_2 + -1'n8_5_2 + -1'n8_4_5 + n8_5_5 = 0
invariant :n7_3_3 + -1'n7_3_6 + n8_0_3 + -1'n8_0_6 = 0
invariant :n9_5_1 + CstopOK_1 + -1'SstopOK_5 = 0
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 4844 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 95 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([](([]((LTLAP0==true)))U(<>((LTLAP1==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 116 ms.
FORMULA QuasiCertifProtocol-PT-06-LTLFireability-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>((<>((LTLAP2==true)))U((LTLAP3==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 78 ms.
FORMULA QuasiCertifProtocol-PT-06-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ((LTLAP4==true))U(X(((LTLAP5==true))U((LTLAP6==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 73 ms.
FORMULA QuasiCertifProtocol-PT-06-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(X((LTLAP7==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 71 ms.
FORMULA QuasiCertifProtocol-PT-06-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ((LTLAP0==true))U(X((LTLAP3==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 71 ms.
FORMULA QuasiCertifProtocol-PT-06-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ([](((LTLAP0==true))U((LTLAP2==true))))U([](X([]((LTLAP8==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 89 ms.
FORMULA QuasiCertifProtocol-PT-06-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP9==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 149 ms.
FORMULA QuasiCertifProtocol-PT-06-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(([](<>((LTLAP7==true))))U((LTLAP10==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 147 ms.
FORMULA QuasiCertifProtocol-PT-06-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (<>([](<>((LTLAP11==true)))))U(X(X([]((LTLAP12==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 97 ms.
FORMULA QuasiCertifProtocol-PT-06-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X(((LTLAP13==true))U((LTLAP14==true))))U(([]((LTLAP15==true)))U([]((LTLAP16==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 92 ms.
FORMULA QuasiCertifProtocol-PT-06-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, ((LTLAP17==true))U([]((LTLAP18==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 154 ms.
FORMULA QuasiCertifProtocol-PT-06-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, [](<>(<>(X([]((LTLAP17==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 76 ms.
FORMULA QuasiCertifProtocol-PT-06-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([]([](X([]((LTLAP19==true)))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 78 ms.
FORMULA QuasiCertifProtocol-PT-06-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X(X(<>((LTLAP20==true)))))U(<>(<>((LTLAP21==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 71 ms.
FORMULA QuasiCertifProtocol-PT-06-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(((LTLAP12==true))U(X(X((LTLAP3==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 77 ms.
FORMULA QuasiCertifProtocol-PT-06-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP22==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 137 ms.
FORMULA QuasiCertifProtocol-PT-06-LTLFireability-15 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1528285041503

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 06, 2018 11:36:41 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Jun 06, 2018 11:36:42 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 06, 2018 11:36:42 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 120 ms
Jun 06, 2018 11:36:42 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 270 places.
Jun 06, 2018 11:36:42 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 116 transitions.
Jun 06, 2018 11:36:42 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 23 ms
Jun 06, 2018 11:36:42 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 97 ms
Jun 06, 2018 11:36:42 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 9 ms
Jun 06, 2018 11:36:42 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 4 ms
Jun 06, 2018 11:36:43 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 116 transitions.
Jun 06, 2018 11:36:43 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 155 place invariants in 104 ms
Jun 06, 2018 11:36:44 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 270 variables to be positive in 818 ms
Jun 06, 2018 11:36:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 116 transitions.
Jun 06, 2018 11:36:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/116 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 06, 2018 11:36:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 11 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 06, 2018 11:36:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 116 transitions.
Jun 06, 2018 11:36:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 10 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 06, 2018 11:36:49 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 116 transitions.
Jun 06, 2018 11:36:49 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/116) took 214 ms. Total solver calls (SAT/UNSAT): 98(98/0)
Jun 06, 2018 11:36:52 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(11/116) took 3568 ms. Total solver calls (SAT/UNSAT): 1070(1070/0)
Jun 06, 2018 11:36:56 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(24/116) took 6851 ms. Total solver calls (SAT/UNSAT): 1720(1684/36)
Jun 06, 2018 11:36:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(34/116) took 10083 ms. Total solver calls (SAT/UNSAT): 2375(2339/36)
Jun 06, 2018 11:37:02 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(43/116) took 13122 ms. Total solver calls (SAT/UNSAT): 2879(2843/36)
Jun 06, 2018 11:37:05 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(55/116) took 16167 ms. Total solver calls (SAT/UNSAT): 3395(3359/36)
Jun 06, 2018 11:37:08 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(81/116) took 19200 ms. Total solver calls (SAT/UNSAT): 3842(3792/50)
Jun 06, 2018 11:37:11 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(99/116) took 22208 ms. Total solver calls (SAT/UNSAT): 4203(4153/50)
Jun 06, 2018 11:37:12 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 23532 ms. Total solver calls (SAT/UNSAT): 4323(4273/50)
Jun 06, 2018 11:37:12 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 116 transitions.
Jun 06, 2018 11:37:13 AM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Skipping mayMatrices nes/nds SMT solver raised an error :unknown
java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.computeDoNotAccord(NecessaryEnablingsolver.java:628)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:538)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
Jun 06, 2018 11:37:13 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 30459ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="QuasiCertifProtocol-PT-06"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/QuasiCertifProtocol-PT-06.tgz
mv QuasiCertifProtocol-PT-06 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is QuasiCertifProtocol-PT-06, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r188-qhx2-152732140200058"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;