Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
...........................................................................................................................................................................
/home/mcc/execution
total 244K
-rw-r--r-- 1 mcc users 3.6K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 19K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 3.1K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 21K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.5K May 26 09:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 26 09:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K May 26 09:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 12K May 26 09:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 22K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 117 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 355 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 3.0K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_pt
-rw-r--r-- 1 mcc users 3 May 15 18:50 instance
-rw-r--r-- 1 mcc users 5 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 61K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is QuasiCertifProtocol-COL-06, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r188-qhx2-152732140200044
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLFireability-00
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLFireability-01
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLFireability-02
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLFireability-03
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLFireability-04
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLFireability-05
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLFireability-06
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLFireability-07
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLFireability-08
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLFireability-09
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLFireability-10
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLFireability-11
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLFireability-12
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLFireability-13
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLFireability-14
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1528280873370

10:28:22.541 [main] ERROR PNML validation - The rng grammar file can't be accessed : www.pnml.org
10:28:22.545 [main] ERROR import - Grammar file errors have been raised, the validation can't be done, process will continue without Grammar validation
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLFireability.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLFireability.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLFireability.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLFireability.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((X(G((G("((((((((((((((tsid0.s5_0>=1)&&(tsidxtsid0.n8_0>=1))&&(tsidxtsid1.n8_1>=1))&&(tsidxtsid4.n8_4>=1))&&(tsidxtsid3.n8_3>=1))&&(tsidxtsid5.n8_5>=1))&&(tsidxtsid6.n8_6>=1))&&(tsidxtsid2.n8_2>=1))||((((((((tsid1.s5_1>=1)&&(tsidxtsid7.n8_7>=1))&&(tsidxtsid8.n8_8>=1))&&(tsidxtsid11.n8_11>=1))&&(tsidxtsid10.n8_10>=1))&&(tsidxtsid12.n8_12>=1))&&(tsidxtsid13.n8_13>=1))&&(tsidxtsid9.n8_9>=1)))||((((((((tsid2.s5_2>=1)&&(tsidxtsid14.n8_14>=1))&&(tsidxtsid15.n8_15>=1))&&(tsidxtsid18.n8_18>=1))&&(tsidxtsid17.n8_17>=1))&&(tsidxtsid19.n8_19>=1))&&(tsidxtsid20.n8_20>=1))&&(tsidxtsid16.n8_16>=1)))||((((((((tsid3.s5_3>=1)&&(tsidxtsid21.n8_21>=1))&&(tsidxtsid22.n8_22>=1))&&(tsidxtsid25.n8_25>=1))&&(tsidxtsid24.n8_24>=1))&&(tsidxtsid26.n8_26>=1))&&(tsidxtsid27.n8_27>=1))&&(tsidxtsid23.n8_23>=1)))||((((((((tsid4.s5_4>=1)&&(tsidxtsid28.n8_28>=1))&&(tsidxtsid29.n8_29>=1))&&(tsidxtsid32.n8_32>=1))&&(tsidxtsid31.n8_31>=1))&&(tsidxtsid33.n8_33>=1))&&(tsidxtsid34.n8_34>=1))&&(tsidxtsid30.n8_30>=1)))||((((((((tsid5.s5_5>=1)&&(tsidxtsid35.n8_35>=1))&&(tsidxtsid36.n8_36>=1))&&(tsidxtsid39.n8_39>=1))&&(tsidxtsid38.n8_38>=1))&&(tsidxtsid40.n8_40>=1))&&(tsidxtsid41.n8_41>=1))&&(tsidxtsid37.n8_37>=1)))||((((((((tsid6.s5_6>=1)&&(tsidxtsid42.n8_42>=1))&&(tsidxtsid43.n8_43>=1))&&(tsidxtsid46.n8_46>=1))&&(tsidxtsid45.n8_45>=1))&&(tsidxtsid47.n8_47>=1))&&(tsidxtsid48.n8_48>=1))&&(tsidxtsid44.n8_44>=1)))"))U(F("((((((((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid0.s6_0>=1))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid1.s6_1>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid2.s6_2>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid3.s6_3>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid4.s6_4>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid5.s6_5>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid6.s6_6>=1)))"))))))
Formula 0 simplified : !XG(G"((((((((((((((tsid0.s5_0>=1)&&(tsidxtsid0.n8_0>=1))&&(tsidxtsid1.n8_1>=1))&&(tsidxtsid4.n8_4>=1))&&(tsidxtsid3.n8_3>=1))&&(tsidxtsid5.n8_5>=1))&&(tsidxtsid6.n8_6>=1))&&(tsidxtsid2.n8_2>=1))||((((((((tsid1.s5_1>=1)&&(tsidxtsid7.n8_7>=1))&&(tsidxtsid8.n8_8>=1))&&(tsidxtsid11.n8_11>=1))&&(tsidxtsid10.n8_10>=1))&&(tsidxtsid12.n8_12>=1))&&(tsidxtsid13.n8_13>=1))&&(tsidxtsid9.n8_9>=1)))||((((((((tsid2.s5_2>=1)&&(tsidxtsid14.n8_14>=1))&&(tsidxtsid15.n8_15>=1))&&(tsidxtsid18.n8_18>=1))&&(tsidxtsid17.n8_17>=1))&&(tsidxtsid19.n8_19>=1))&&(tsidxtsid20.n8_20>=1))&&(tsidxtsid16.n8_16>=1)))||((((((((tsid3.s5_3>=1)&&(tsidxtsid21.n8_21>=1))&&(tsidxtsid22.n8_22>=1))&&(tsidxtsid25.n8_25>=1))&&(tsidxtsid24.n8_24>=1))&&(tsidxtsid26.n8_26>=1))&&(tsidxtsid27.n8_27>=1))&&(tsidxtsid23.n8_23>=1)))||((((((((tsid4.s5_4>=1)&&(tsidxtsid28.n8_28>=1))&&(tsidxtsid29.n8_29>=1))&&(tsidxtsid32.n8_32>=1))&&(tsidxtsid31.n8_31>=1))&&(tsidxtsid33.n8_33>=1))&&(tsidxtsid34.n8_34>=1))&&(tsidxtsid30.n8_30>=1)))||((((((((tsid5.s5_5>=1)&&(tsidxtsid35.n8_35>=1))&&(tsidxtsid36.n8_36>=1))&&(tsidxtsid39.n8_39>=1))&&(tsidxtsid38.n8_38>=1))&&(tsidxtsid40.n8_40>=1))&&(tsidxtsid41.n8_41>=1))&&(tsidxtsid37.n8_37>=1)))||((((((((tsid6.s5_6>=1)&&(tsidxtsid42.n8_42>=1))&&(tsidxtsid43.n8_43>=1))&&(tsidxtsid46.n8_46>=1))&&(tsidxtsid45.n8_45>=1))&&(tsidxtsid47.n8_47>=1))&&(tsidxtsid48.n8_48>=1))&&(tsidxtsid44.n8_44>=1)))" U F"((((((((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid0.s6_0>=1))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid1.s6_1>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid2.s6_2>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid3.s6_3>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid4.s6_4>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid5.s6_5>=1)))||((malicious_reservoir.malicious_reservoir_0>=1)&&(tsid6.s6_6>=1)))")
built 41 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 116 rows 270 cols
invariant :tsidxtsid22:n9_22 + tsid1:CstopOK_1 + -1'tsid3:SstopOK_3 = 0
invariant :tsidxtsid48:n9_48 + -1'tsid6:SstopOK_6 + tsid6:CstopOK_6 = 0
invariant :tsid2:n6_2 + tsid2:n5_2 + -1'tsid6:n6_6 + -1'tsid6:n5_6 = 0
invariant :tsidxtsid14:n9_14 + tsid0:CstopOK_0 + -1'tsid2:SstopOK_2 = 0
invariant :tsidxtsid12:n9_12 + -1'tsid1:SstopOK_1 + tsid5:CstopOK_5 = 0
invariant :tsid4:n4_4 + tsid4:n3_4 + -1'tsid6:n4_6 + -1'tsid6:n3_6 = 0
invariant :tsidxtsid8:n7_8 + -1'tsidxtsid13:n7_13 + -1'tsid1:Cstart_1 + tsid6:Cstart_6 = 0
invariant :tsidxtsid26:n9_26 + -1'tsid3:SstopOK_3 + tsid5:CstopOK_5 = 0
invariant :tsidxtsid3:n9_3 + -1'tsid0:SstopOK_0 + tsid3:CstopOK_3 = 0
invariant :tsidxtsid29:n7_29 + -1'tsidxtsid34:n7_34 + -1'tsid1:Cstart_1 + tsid6:Cstart_6 = 0
invariant :tsidxtsid24:n8_24 + -1'tsidxtsid27:n8_27 + tsid3:Cstart_3 + -1'tsid6:Cstart_6 = 0
invariant :tsid4:n6_4 + tsid4:n5_4 + -1'tsid6:n6_6 + -1'tsid6:n5_6 = 0
invariant :tsidxtsid2:n9_2 + -1'tsid0:SstopOK_0 + tsid2:CstopOK_2 = 0
invariant :tsidxtsid24:n9_24 + -1'tsid3:SstopOK_3 + tsid3:CstopOK_3 = 0
invariant :tsidxtsid10:n7_10 + -1'tsidxtsid13:n7_13 + -1'tsid3:Cstart_3 + tsid6:Cstart_6 = 0
invariant :tsidxtsid27:n9_27 + -1'tsid3:SstopOK_3 + tsid6:CstopOK_6 = 0
invariant :tsidxtsid7:n7_7 + -1'tsidxtsid13:n7_13 + -1'tsid0:Cstart_0 + tsid6:Cstart_6 = 0
invariant :tsidxtsid4:n9_4 + -1'tsid0:SstopOK_0 + tsid4:CstopOK_4 = 0
invariant :tsidxtsid14:n8_14 + -1'tsidxtsid20:n8_20 + tsid0:Cstart_0 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid26:n8_26 + -1'tsidxtsid27:n8_27 + tsid5:Cstart_5 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid30:n8_30 + -1'tsidxtsid34:n8_34 + tsid2:Cstart_2 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid46:n8_46 + -1'tsidxtsid48:n8_48 + tsid4:Cstart_4 + -1'tsid6:Cstart_6 = 0
invariant :tsid2:n4_2 + tsid2:n3_2 + -1'tsid6:n4_6 + -1'tsid6:n3_6 = 0
invariant :tsidxtsid23:n8_23 + -1'tsidxtsid27:n8_27 + tsid2:Cstart_2 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid18:n7_18 + -1'tsidxtsid20:n7_20 + -1'tsid4:Cstart_4 + tsid6:Cstart_6 = 0
invariant :tsid0:n6_0 + tsid0:n5_0 + -1'tsid6:n6_6 + -1'tsid6:n5_6 = 0
invariant :tsidxtsid9:n9_9 + -1'tsid1:SstopOK_1 + tsid2:CstopOK_2 = 0
invariant :tsidxtsid47:n7_47 + -1'tsidxtsid48:n7_48 + -1'tsid5:Cstart_5 + tsid6:Cstart_6 = 0
invariant :tsid5:n2_5 + tsid5:n1_5 + -1'tsid6:n2_6 + -1'tsid6:n1_6 = 0
invariant :tsidxtsid42:n9_42 + tsid0:CstopOK_0 + -1'tsid6:SstopOK_6 = 0
invariant :tsidxtsid8:n9_8 + -1'tsid1:SstopOK_1 + tsid1:CstopOK_1 = 0
invariant :tsidxtsid41:n9_41 + -1'tsid5:SstopOK_5 + tsid6:CstopOK_6 = 0
invariant :tsid4:n2_4 + tsid4:n1_4 + -1'tsid6:n2_6 + -1'tsid6:n1_6 = 0
invariant :tsidxtsid3:n8_3 + -1'tsidxtsid6:n8_6 + tsid3:Cstart_3 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid17:n9_17 + -1'tsid2:SstopOK_2 + tsid3:CstopOK_3 = 0
invariant :tsid5:n4_5 + tsid5:n3_5 + -1'tsid6:n4_6 + -1'tsid6:n3_6 = 0
invariant :tsidxtsid38:n8_38 + -1'tsidxtsid41:n8_41 + tsid3:Cstart_3 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid42:n7_42 + -1'tsidxtsid48:n7_48 + -1'tsid0:Cstart_0 + tsid6:Cstart_6 = 0
invariant :tsidxtsid22:n7_22 + -1'tsidxtsid27:n7_27 + -1'tsid1:Cstart_1 + tsid6:Cstart_6 = 0
invariant :tsid5:n6_5 + tsid5:n5_5 + -1'tsid6:n6_6 + -1'tsid6:n5_6 = 0
invariant :tsidxtsid12:n8_12 + -1'tsidxtsid13:n8_13 + tsid5:Cstart_5 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid29:n8_29 + -1'tsidxtsid34:n8_34 + tsid1:Cstart_1 + -1'tsid6:Cstart_6 = 0
invariant :AstopAbort:AstopAbort_0 + a5:a5_0 + a4:a4_0 + a3:a3_0 + a2:a2_0 + a1:a1_0 + Astart:Astart_0 + AstopOK:AstopOK_0 = 1
invariant :tsidxtsid22:n8_22 + -1'tsidxtsid27:n8_27 + tsid1:Cstart_1 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid28:n9_28 + tsid0:CstopOK_0 + -1'tsid4:SstopOK_4 = 0
invariant :tsidxtsid31:n9_31 + tsid3:CstopOK_3 + -1'tsid4:SstopOK_4 = 0
invariant :tsidxtsid4:n8_4 + -1'tsidxtsid6:n8_6 + tsid4:Cstart_4 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid33:n7_33 + -1'tsidxtsid34:n7_34 + -1'tsid5:Cstart_5 + tsid6:Cstart_6 = 0
invariant :tsidxtsid16:n9_16 + -1'tsid2:SstopOK_2 + tsid2:CstopOK_2 = 0
invariant :tsidxtsid21:n7_21 + -1'tsidxtsid27:n7_27 + -1'tsid0:Cstart_0 + tsid6:Cstart_6 = 0
invariant :tsidxtsid5:n7_5 + -1'tsidxtsid6:n7_6 + -1'tsid5:Cstart_5 + tsid6:Cstart_6 = 0
invariant :tsidxtsid37:n8_37 + -1'tsidxtsid41:n8_41 + tsid2:Cstart_2 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid0:n8_0 + -1'tsidxtsid6:n8_6 + tsid0:Cstart_0 + -1'tsid6:Cstart_6 = 0
invariant :tsid3:n4_3 + tsid3:n3_3 + -1'tsid6:n4_6 + -1'tsid6:n3_6 = 0
invariant :tsidxtsid40:n7_40 + -1'tsidxtsid41:n7_41 + -1'tsid5:Cstart_5 + tsid6:Cstart_6 = 0
invariant :tsidxtsid45:n9_45 + tsid3:CstopOK_3 + -1'tsid6:SstopOK_6 = 0
invariant :tsidxtsid19:n7_19 + -1'tsidxtsid20:n7_20 + -1'tsid5:Cstart_5 + tsid6:Cstart_6 = 0
invariant :tsidxtsid21:n8_21 + -1'tsidxtsid27:n8_27 + tsid0:Cstart_0 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid2:n8_2 + -1'tsidxtsid6:n8_6 + tsid2:Cstart_2 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid5:n9_5 + -1'tsid0:SstopOK_0 + tsid5:CstopOK_5 = 0
invariant :tsidxtsid36:n8_36 + -1'tsidxtsid41:n8_41 + tsid1:Cstart_1 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid44:n8_44 + -1'tsidxtsid48:n8_48 + tsid2:Cstart_2 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid26:n7_26 + -1'tsidxtsid27:n7_27 + -1'tsid5:Cstart_5 + tsid6:Cstart_6 = 0
invariant :tsidxtsid1:n7_1 + -1'tsidxtsid6:n7_6 + -1'tsid1:Cstart_1 + tsid6:Cstart_6 = 0
invariant :tsidxtsid43:n9_43 + tsid1:CstopOK_1 + -1'tsid6:SstopOK_6 = 0
invariant :tsidxtsid6:n9_6 + -1'tsid0:SstopOK_0 + tsid6:CstopOK_6 = 0
invariant :tsidxtsid1:n8_1 + -1'tsidxtsid6:n8_6 + tsid1:Cstart_1 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid25:n7_25 + -1'tsidxtsid27:n7_27 + -1'tsid4:Cstart_4 + tsid6:Cstart_6 = 0
invariant :tsidxtsid40:n8_40 + -1'tsidxtsid41:n8_41 + tsid5:Cstart_5 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid20:n9_20 + -1'tsid2:SstopOK_2 + tsid6:CstopOK_6 = 0
invariant :tsidxtsid12:n7_12 + -1'tsidxtsid13:n7_13 + -1'tsid5:Cstart_5 + tsid6:Cstart_6 = 0
invariant :tsidxtsid39:n9_39 + tsid4:CstopOK_4 + -1'tsid5:SstopOK_5 = 0
invariant :malicious_reservoir:malicious_reservoir_0 + -1'tsid0:c1_0 + -1'tsid0:Cstart_0 + -1'tsid0:Sstart_0 + -1'tsid0:s2_0 + -1'tsid0:s3_0 + -1'tsid0:s4_0 + -1'tsid0:s5_0 + -1'tsid0:s6_0 + -1'tsid0:SstopOK_0 + -1'tsid0:CstopOK_0 + -1'tsid1:c1_1 + -1'tsid1:Cstart_1 + -1'tsid1:Sstart_1 + -1'tsid1:s2_1 + -1'tsid1:s3_1 + -1'tsid1:s4_1 + -1'tsid1:s5_1 + -1'tsid1:s6_1 + -1'tsid1:SstopOK_1 + -1'tsid1:CstopOK_1 + -1'tsid2:c1_2 + -1'tsid2:Cstart_2 + -1'tsid2:Sstart_2 + -1'tsid2:s2_2 + -1'tsid2:s3_2 + -1'tsid2:s4_2 + -1'tsid2:s5_2 + -1'tsid2:s6_2 + -1'tsid2:SstopOK_2 + -1'tsid2:CstopOK_2 + -1'tsid3:c1_3 + -1'tsid3:Cstart_3 + -1'tsid3:Sstart_3 + -1'tsid3:s2_3 + -1'tsid3:s3_3 + -1'tsid3:s4_3 + -1'tsid3:s5_3 + -1'tsid3:s6_3 + -1'tsid3:SstopOK_3 + -1'tsid3:CstopOK_3 + -1'tsid4:c1_4 + -1'tsid4:Cstart_4 + -1'tsid4:Sstart_4 + -1'tsid4:s2_4 + -1'tsid4:s3_4 + -1'tsid4:s4_4 + -1'tsid4:s5_4 + -1'tsid4:s6_4 + -1'tsid4:SstopOK_4 + -1'tsid4:CstopOK_4 + -1'tsid5:c1_5 + -1'tsid5:Cstart_5 + -1'tsid5:Sstart_5 + -1'tsid5:s2_5 + -1'tsid5:s3_5 + -1'tsid5:s4_5 + -1'tsid5:s5_5 + -1'tsid5:s6_5 + -1'tsid5:SstopOK_5 + -1'tsid5:CstopOK_5 + -1'tsid6:c1_6 + -1'tsid6:Cstart_6 + -1'tsid6:Sstart_6 + -1'tsid6:s2_6 + -1'tsid6:s3_6 + -1'tsid6:s4_6 + -1'tsid6:s5_6 + -1'tsid6:s6_6 + -1'tsid6:SstopOK_6 + -1'tsid6:CstopOK_6 = -11
invariant :SstopAbort:SstopAbort_0 + tsid0:Sstart_0 + tsid0:s2_0 + tsid0:s3_0 + tsid0:s4_0 + tsid0:s5_0 + tsid0:s6_0 + tsid0:SstopOK_0 + tsid1:Sstart_1 + tsid1:s2_1 + tsid1:s3_1 + tsid1:s4_1 + tsid1:s5_1 + tsid1:s6_1 + tsid1:SstopOK_1 + tsid2:Sstart_2 + tsid2:s2_2 + tsid2:s3_2 + tsid2:s4_2 + tsid2:s5_2 + tsid2:s6_2 + tsid2:SstopOK_2 + tsid3:Sstart_3 + tsid3:s2_3 + tsid3:s3_3 + tsid3:s4_3 + tsid3:s5_3 + tsid3:s6_3 + tsid3:SstopOK_3 + tsid4:Sstart_4 + tsid4:s2_4 + tsid4:s3_4 + tsid4:s4_4 + tsid4:s5_4 + tsid4:s6_4 + tsid4:SstopOK_4 + tsid5:Sstart_5 + tsid5:s2_5 + tsid5:s3_5 + tsid5:s4_5 + tsid5:s5_5 + tsid5:s6_5 + tsid5:SstopOK_5 + tsid6:Sstart_6 + tsid6:s2_6 + tsid6:s3_6 + tsid6:s4_6 + tsid6:s5_6 + tsid6:s6_6 + tsid6:SstopOK_6 = 7
invariant :tsidxtsid8:n8_8 + -1'tsidxtsid13:n8_13 + tsid1:Cstart_1 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid47:n9_47 + tsid5:CstopOK_5 + -1'tsid6:SstopOK_6 = 0
invariant :tsidxtsid45:n8_45 + -1'tsidxtsid48:n8_48 + tsid3:Cstart_3 + -1'tsid6:Cstart_6 = 0
invariant :tsid3:n2_3 + tsid3:n1_3 + -1'tsid6:n2_6 + -1'tsid6:n1_6 = 0
invariant :tsidxtsid11:n9_11 + -1'tsid1:SstopOK_1 + tsid4:CstopOK_4 = 0
invariant :tsidxtsid15:n8_15 + -1'tsidxtsid20:n8_20 + tsid1:Cstart_1 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid19:n8_19 + -1'tsidxtsid20:n8_20 + tsid5:Cstart_5 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid28:n7_28 + -1'tsidxtsid34:n7_34 + -1'tsid0:Cstart_0 + tsid6:Cstart_6 = 0
invariant :tsid1:n2_1 + tsid1:n1_1 + -1'tsid6:n2_6 + -1'tsid6:n1_6 = 0
invariant :tsidxtsid29:n9_29 + tsid1:CstopOK_1 + -1'tsid4:SstopOK_4 = 0
invariant :tsid0:n2_0 + tsid0:n1_0 + -1'tsid6:n2_6 + -1'tsid6:n1_6 = 0
invariant :tsidxtsid32:n8_32 + -1'tsidxtsid34:n8_34 + tsid4:Cstart_4 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid46:n7_46 + -1'tsidxtsid48:n7_48 + -1'tsid4:Cstart_4 + tsid6:Cstart_6 = 0
invariant :tsidxtsid16:n7_16 + -1'tsidxtsid20:n7_20 + -1'tsid2:Cstart_2 + tsid6:Cstart_6 = 0
invariant :tsidxtsid23:n9_23 + tsid2:CstopOK_2 + -1'tsid3:SstopOK_3 = 0
invariant :tsidxtsid25:n9_25 + -1'tsid3:SstopOK_3 + tsid4:CstopOK_4 = 0
invariant :tsidxtsid11:n8_11 + -1'tsidxtsid13:n8_13 + tsid4:Cstart_4 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid15:n9_15 + tsid1:CstopOK_1 + -1'tsid2:SstopOK_2 = 0
invariant :tsidxtsid36:n9_36 + tsid1:CstopOK_1 + -1'tsid5:SstopOK_5 = 0
invariant :tsidxtsid17:n8_17 + -1'tsidxtsid20:n8_20 + tsid3:Cstart_3 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid10:n9_10 + -1'tsid1:SstopOK_1 + tsid3:CstopOK_3 = 0
invariant :tsidxtsid15:n7_15 + -1'tsidxtsid20:n7_20 + -1'tsid1:Cstart_1 + tsid6:Cstart_6 = 0
invariant :tsidxtsid31:n8_31 + -1'tsidxtsid34:n8_34 + tsid3:Cstart_3 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid24:n7_24 + -1'tsidxtsid27:n7_27 + -1'tsid3:Cstart_3 + tsid6:Cstart_6 = 0
invariant :tsidxtsid32:n7_32 + -1'tsidxtsid34:n7_34 + -1'tsid4:Cstart_4 + tsid6:Cstart_6 = 0
invariant :tsidxtsid32:n9_32 + -1'tsid4:SstopOK_4 + tsid4:CstopOK_4 = 0
invariant :tsidxtsid21:n9_21 + tsid0:CstopOK_0 + -1'tsid3:SstopOK_3 = 0
invariant :tsidxtsid37:n7_37 + -1'tsidxtsid41:n7_41 + -1'tsid2:Cstart_2 + tsid6:Cstart_6 = 0
invariant :tsidxtsid38:n9_38 + tsid3:CstopOK_3 + -1'tsid5:SstopOK_5 = 0
invariant :tsidxtsid39:n7_39 + -1'tsidxtsid41:n7_41 + -1'tsid4:Cstart_4 + tsid6:Cstart_6 = 0
invariant :tsidxtsid9:n8_9 + -1'tsidxtsid13:n8_13 + tsid2:Cstart_2 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid10:n8_10 + -1'tsidxtsid13:n8_13 + tsid3:Cstart_3 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid31:n7_31 + -1'tsidxtsid34:n7_34 + -1'tsid3:Cstart_3 + tsid6:Cstart_6 = 0
invariant :tsidxtsid3:n7_3 + -1'tsidxtsid6:n7_6 + -1'tsid3:Cstart_3 + tsid6:Cstart_6 = 0
invariant :tsid3:n6_3 + tsid3:n5_3 + -1'tsid6:n6_6 + -1'tsid6:n5_6 = 0
invariant :tsidxtsid4:n7_4 + -1'tsidxtsid6:n7_6 + -1'tsid4:Cstart_4 + tsid6:Cstart_6 = 0
invariant :tsidxtsid2:n7_2 + -1'tsidxtsid6:n7_6 + -1'tsid2:Cstart_2 + tsid6:Cstart_6 = 0
invariant :tsidxtsid35:n8_35 + -1'tsidxtsid41:n8_41 + tsid0:Cstart_0 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid16:n8_16 + -1'tsidxtsid20:n8_20 + tsid2:Cstart_2 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid14:n7_14 + -1'tsidxtsid20:n7_20 + -1'tsid0:Cstart_0 + tsid6:Cstart_6 = 0
invariant :tsidxtsid5:n8_5 + -1'tsidxtsid6:n8_6 + tsid5:Cstart_5 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid1:n9_1 + -1'tsid0:SstopOK_0 + tsid1:CstopOK_1 = 0
invariant :tsidxtsid47:n8_47 + -1'tsidxtsid48:n8_48 + tsid5:Cstart_5 + -1'tsid6:Cstart_6 = 0
invariant :tsid2:n2_2 + tsid2:n1_2 + -1'tsid6:n2_6 + -1'tsid6:n1_6 = 0
invariant :tsidxtsid0:n7_0 + -1'tsidxtsid6:n7_6 + -1'tsid0:Cstart_0 + tsid6:Cstart_6 = 0
invariant :tsidxtsid18:n9_18 + -1'tsid2:SstopOK_2 + tsid4:CstopOK_4 = 0
invariant :tsidxtsid46:n9_46 + tsid4:CstopOK_4 + -1'tsid6:SstopOK_6 = 0
invariant :tsidxtsid18:n8_18 + -1'tsidxtsid20:n8_20 + tsid4:Cstart_4 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid28:n8_28 + -1'tsidxtsid34:n8_34 + tsid0:Cstart_0 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid33:n9_33 + -1'tsid4:SstopOK_4 + tsid5:CstopOK_5 = 0
invariant :tsidxtsid25:n8_25 + -1'tsidxtsid27:n8_27 + tsid4:Cstart_4 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid9:n7_9 + -1'tsidxtsid13:n7_13 + -1'tsid2:Cstart_2 + tsid6:Cstart_6 = 0
invariant :tsidxtsid23:n7_23 + -1'tsidxtsid27:n7_27 + -1'tsid2:Cstart_2 + tsid6:Cstart_6 = 0
invariant :tsidxtsid42:n8_42 + -1'tsidxtsid48:n8_48 + tsid0:Cstart_0 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid35:n7_35 + -1'tsidxtsid41:n7_41 + -1'tsid0:Cstart_0 + tsid6:Cstart_6 = 0
invariant :tsidxtsid17:n7_17 + -1'tsidxtsid20:n7_20 + -1'tsid3:Cstart_3 + tsid6:Cstart_6 = 0
invariant :tsid1:n6_1 + tsid1:n5_1 + -1'tsid6:n6_6 + -1'tsid6:n5_6 = 0
invariant :tsidxtsid13:n9_13 + -1'tsid1:SstopOK_1 + tsid6:CstopOK_6 = 0
invariant :tsidxtsid33:n8_33 + -1'tsidxtsid34:n8_34 + tsid5:Cstart_5 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid45:n7_45 + -1'tsidxtsid48:n7_48 + -1'tsid3:Cstart_3 + tsid6:Cstart_6 = 0
invariant :CstopAbort:CstopAbort_0 + tsid0:c1_0 + tsid0:Cstart_0 + tsid0:CstopOK_0 + tsid1:c1_1 + tsid1:Cstart_1 + tsid1:CstopOK_1 + tsid2:c1_2 + tsid2:Cstart_2 + tsid2:CstopOK_2 + tsid3:c1_3 + tsid3:Cstart_3 + tsid3:CstopOK_3 + tsid4:c1_4 + tsid4:Cstart_4 + tsid4:CstopOK_4 + tsid5:c1_5 + tsid5:Cstart_5 + tsid5:CstopOK_5 + tsid6:c1_6 + tsid6:Cstart_6 + tsid6:CstopOK_6 = 7
invariant :tsidxtsid43:n8_43 + -1'tsidxtsid48:n8_48 + tsid1:Cstart_1 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid35:n9_35 + tsid0:CstopOK_0 + -1'tsid5:SstopOK_5 = 0
invariant :tsidxtsid7:n8_7 + -1'tsidxtsid13:n8_13 + tsid0:Cstart_0 + -1'tsid6:Cstart_6 = 0
invariant :tsidxtsid44:n7_44 + -1'tsidxtsid48:n7_48 + -1'tsid2:Cstart_2 + tsid6:Cstart_6 = 0
invariant :tsidxtsid30:n9_30 + tsid2:CstopOK_2 + -1'tsid4:SstopOK_4 = 0
invariant :tsidxtsid37:n9_37 + tsid2:CstopOK_2 + -1'tsid5:SstopOK_5 = 0
invariant :tsidxtsid0:n9_0 + -1'tsid0:SstopOK_0 + tsid0:CstopOK_0 = 0
invariant :tsidxtsid36:n7_36 + -1'tsidxtsid41:n7_41 + -1'tsid1:Cstart_1 + tsid6:Cstart_6 = 0
invariant :tsidxtsid30:n7_30 + -1'tsidxtsid34:n7_34 + -1'tsid2:Cstart_2 + tsid6:Cstart_6 = 0
invariant :tsidxtsid39:n8_39 + -1'tsidxtsid41:n8_41 + tsid4:Cstart_4 + -1'tsid6:Cstart_6 = 0
invariant :tsid1:n4_1 + tsid1:n3_1 + -1'tsid6:n4_6 + -1'tsid6:n3_6 = 0
invariant :tsidxtsid38:n7_38 + -1'tsidxtsid41:n7_41 + -1'tsid3:Cstart_3 + tsid6:Cstart_6 = 0
invariant :tsidxtsid11:n7_11 + -1'tsidxtsid13:n7_13 + -1'tsid4:Cstart_4 + tsid6:Cstart_6 = 0
invariant :tsidxtsid34:n9_34 + -1'tsid4:SstopOK_4 + tsid6:CstopOK_6 = 0
invariant :tsidxtsid40:n9_40 + -1'tsid5:SstopOK_5 + tsid5:CstopOK_5 = 0
invariant :tsidxtsid44:n9_44 + tsid2:CstopOK_2 + -1'tsid6:SstopOK_6 = 0
invariant :tsidxtsid43:n7_43 + -1'tsidxtsid48:n7_48 + -1'tsid1:Cstart_1 + tsid6:Cstart_6 = 0
invariant :tsidxtsid7:n9_7 + tsid0:CstopOK_0 + -1'tsid1:SstopOK_1 = 0
invariant :tsid0:n4_0 + tsid0:n3_0 + -1'tsid6:n4_6 + -1'tsid6:n3_6 = 0
invariant :tsidxtsid19:n9_19 + -1'tsid2:SstopOK_2 + tsid5:CstopOK_5 = 0
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 6893 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 79 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([](([]((LTLAP0==true)))U(<>((LTLAP1==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 116 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLFireability-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>((<>((LTLAP2==true)))U((LTLAP3==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 59 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLFireability-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ((LTLAP4==true))U(X(((LTLAP5==true))U((LTLAP6==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 60 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLFireability-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(X((LTLAP7==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 64 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLFireability-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ((LTLAP0==true))U(X((LTLAP3==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 75 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLFireability-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ([](((LTLAP0==true))U((LTLAP2==true))))U([](X([]((LTLAP8==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 75 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLFireability-05 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP9==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 133 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLFireability-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(([](<>((LTLAP7==true))))U((LTLAP10==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 141 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLFireability-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(([]((LTLAP4==true)))U([](<>((LTLAP0==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 138 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLFireability-08 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X(X(<>((LTLAP3==true)))))U(((LTLAP11==true))U(<>((LTLAP12==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 58 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLFireability-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(<>(<>((LTLAP1==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 138 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLFireability-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>((<>(X((LTLAP7==true))))U([](<>((LTLAP5==true))))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 74 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLFireability-11 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X(((LTLAP10==true))U((LTLAP12==true))))U(((LTLAP8==true))U((LTLAP9==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 78 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLFireability-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, <>(((LTLAP13==true))U(X((LTLAP11==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 59 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLFireability-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, (X(<>([]((LTLAP14==true)))))U((LTLAP15==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 64 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLFireability-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ((X((LTLAP1==true)))U((LTLAP3==true)))U(X(<>((LTLAP7==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 61 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLFireability-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1528281041624

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 06, 2018 10:28:01 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Jun 06, 2018 10:28:01 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 06, 2018 10:28:01 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
Jun 06, 2018 10:28:23 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Load time of PNML (colored model parsed with PNMLFW) : 21776 ms
Jun 06, 2018 10:28:23 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 30 places.
Jun 06, 2018 10:28:23 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Computed order using colors.
Jun 06, 2018 10:28:23 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: sort/places :tsidxtsid->n9,n8,n7,
Dot->malicious_reservoir,CstopAbort,SstopAbort,AstopAbort,a5,a4,a3,a2,a1,Astart,AstopOK,
tsid->n6,n5,n4,n3,n2,n1,c1,Cstart,Sstart,s2,s3,s4,s5,s6,SstopOK,CstopOK,

Jun 06, 2018 10:28:23 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 26 transitions.
Jun 06, 2018 10:28:23 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Computed order based on color domains.
Jun 06, 2018 10:28:23 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 24 ms
Jun 06, 2018 10:28:23 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Jun 06, 2018 10:28:23 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Jun 06, 2018 10:28:24 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 172 ms
Jun 06, 2018 10:28:26 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays n9, n8, n7, n6, n5, n4, n3, n2, n1, c1, Cstart, Sstart, s2, s3, s4, s5, s6, SstopOK, CstopOK to variables to allow decomposition.
Jun 06, 2018 10:28:26 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 20 redundant transitions.
Jun 06, 2018 10:28:27 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLFireability.pnml.gal : 21 ms
Jun 06, 2018 10:28:27 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLFireability.ltl : 13 ms
Jun 06, 2018 10:28:27 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 74 transitions. Expanding to a total of 123 deterministic transitions.
Jun 06, 2018 10:28:27 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 11 ms.
Jun 06, 2018 10:28:28 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 155 place invariants in 148 ms
Jun 06, 2018 10:28:31 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 270 variables to be positive in 3063 ms
Jun 06, 2018 10:28:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 116 transitions.
Jun 06, 2018 10:28:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/116 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 06, 2018 10:28:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 22 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 06, 2018 10:28:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 116 transitions.
Jun 06, 2018 10:28:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 20 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 06, 2018 10:28:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 116 transitions.
Jun 06, 2018 10:28:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/116) took 2495 ms. Total solver calls (SAT/UNSAT): 104(104/0)
Jun 06, 2018 10:28:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(2/116) took 5688 ms. Total solver calls (SAT/UNSAT): 309(309/0)
Jun 06, 2018 10:28:49 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(5/116) took 10426 ms. Total solver calls (SAT/UNSAT): 609(609/0)
Jun 06, 2018 10:28:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(7/116) took 15617 ms. Total solver calls (SAT/UNSAT): 804(804/0)
Jun 06, 2018 10:28:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(9/116) took 20471 ms. Total solver calls (SAT/UNSAT): 995(995/0)
Jun 06, 2018 10:29:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(11/116) took 24744 ms. Total solver calls (SAT/UNSAT): 1182(1182/0)
Jun 06, 2018 10:29:07 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(13/116) took 28663 ms. Total solver calls (SAT/UNSAT): 1365(1365/0)
Jun 06, 2018 10:29:11 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(15/116) took 32923 ms. Total solver calls (SAT/UNSAT): 1544(1544/0)
Jun 06, 2018 10:29:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(17/116) took 36916 ms. Total solver calls (SAT/UNSAT): 1719(1719/0)
Jun 06, 2018 10:29:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(19/116) took 41055 ms. Total solver calls (SAT/UNSAT): 1890(1890/0)
Jun 06, 2018 10:29:23 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(21/116) took 44321 ms. Total solver calls (SAT/UNSAT): 2057(2057/0)
Jun 06, 2018 10:29:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(24/116) took 48232 ms. Total solver calls (SAT/UNSAT): 2300(2300/0)
Jun 06, 2018 10:29:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(27/116) took 52345 ms. Total solver calls (SAT/UNSAT): 2534(2534/0)
Jun 06, 2018 10:29:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(30/116) took 56826 ms. Total solver calls (SAT/UNSAT): 2759(2759/0)
Jun 06, 2018 10:29:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(33/116) took 60853 ms. Total solver calls (SAT/UNSAT): 2975(2975/0)
Jun 06, 2018 10:29:43 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(36/116) took 64599 ms. Total solver calls (SAT/UNSAT): 3182(3182/0)
Jun 06, 2018 10:29:47 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(39/116) took 68063 ms. Total solver calls (SAT/UNSAT): 3380(3380/0)
Jun 06, 2018 10:29:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(42/116) took 72014 ms. Total solver calls (SAT/UNSAT): 3569(3569/0)
Jun 06, 2018 10:29:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(45/116) took 75249 ms. Total solver calls (SAT/UNSAT): 3749(3749/0)
Jun 06, 2018 10:29:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(48/116) took 79087 ms. Total solver calls (SAT/UNSAT): 3920(3920/0)
Jun 06, 2018 10:30:01 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(61/116) took 82400 ms. Total solver calls (SAT/UNSAT): 4372(4337/35)
Jun 06, 2018 10:30:04 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(66/116) took 85952 ms. Total solver calls (SAT/UNSAT): 4597(4562/35)
Jun 06, 2018 10:30:08 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(69/116) took 89412 ms. Total solver calls (SAT/UNSAT): 4720(4685/35)
Jun 06, 2018 10:30:12 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(73/116) took 93591 ms. Total solver calls (SAT/UNSAT): 4870(4835/35)
Jun 06, 2018 10:30:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(78/116) took 96961 ms. Total solver calls (SAT/UNSAT): 5035(5000/35)
Jun 06, 2018 10:30:19 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(83/116) took 100050 ms. Total solver calls (SAT/UNSAT): 5175(5140/35)
Jun 06, 2018 10:30:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(87/116) took 103167 ms. Total solver calls (SAT/UNSAT): 5269(5234/35)
Jun 06, 2018 10:30:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(99/116) took 106214 ms. Total solver calls (SAT/UNSAT): 5416(5366/50)
Jun 06, 2018 10:30:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 109157 ms. Total solver calls (SAT/UNSAT): 5536(5486/50)
Jun 06, 2018 10:30:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 116 transitions.
Jun 06, 2018 10:30:30 AM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Jun 06, 2018 10:30:31 AM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Skipping mayMatrices nes/nds SMT solver raised an error :unknown
java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.computeDoNotAccord(NecessaryEnablingsolver.java:628)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:538)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
Jun 06, 2018 10:30:31 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 124439ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="QuasiCertifProtocol-COL-06"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/QuasiCertifProtocol-COL-06.tgz
mv QuasiCertifProtocol-COL-06 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is QuasiCertifProtocol-COL-06, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r188-qhx2-152732140200044"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;