fond
Model Checking Contest 2018
8th edition, Bratislava, Slovakia, June 26, 2018
Execution of r188-qhx2-152732140200043
Last Updated
June 26, 2018

About the Execution of ITS-Tools for QuasiCertifProtocol-COL-06

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15730.740 101432.00 189821.00 572.80 FTFFFTFFTFFTTTFT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
....................................
/home/mcc/execution
total 244K
-rw-r--r-- 1 mcc users 3.6K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 19K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 3.1K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 21K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.5K May 26 09:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 26 09:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K May 26 09:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 12K May 26 09:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 22K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 117 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 355 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 3.0K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_pt
-rw-r--r-- 1 mcc users 3 May 15 18:50 instance
-rw-r--r-- 1 mcc users 5 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 61K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is QuasiCertifProtocol-COL-06, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r188-qhx2-152732140200043
=====================================================================


--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLCardinality-00
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLCardinality-01
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLCardinality-02
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLCardinality-03
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLCardinality-04
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLCardinality-05
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLCardinality-06
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLCardinality-07
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLCardinality-08
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLCardinality-09
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLCardinality-10
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLCardinality-11
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLCardinality-12
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLCardinality-13
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLCardinality-14
FORMULA_NAME QuasiCertifProtocol-COL-06-LTLCardinality-15

=== Now, execution of the tool begins

BK_START 1528280863171

10:28:07.841 [main] ERROR PNML validation - The rng grammar file can't be accessed : www.pnml.org
10:28:07.845 [main] ERROR import - Grammar file errors have been raised, the validation can't be done, process will continue without Grammar validation
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64, --gc-threshold, 2000000, -i, /home/mcc/execution/LTLCardinality.pnml.gal, -t, CGAL, -LTL, /home/mcc/execution/LTLCardinality.ltl, -c, -stutter-deadlock], workingDir=/home/mcc/execution]

its-ltl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ltl-linux64 --gc-threshold 2000000 -i /home/mcc/execution/LTLCardinality.pnml.gal -t CGAL -LTL /home/mcc/execution/LTLCardinality.ltl -c -stutter-deadlock
Read 16 LTL properties
Checking formula 0 : !((G((F("(a1_0>=1)"))U(G("(((((((n3_0+n3_1)+n3_2)+n3_3)+n3_4)+n3_5)+n3_6)>=1)")))))
Formula 0 simplified : !G(F"(a1_0>=1)" U G"(((((((n3_0+n3_1)+n3_2)+n3_3)+n3_4)+n3_5)+n3_6)>=1)")
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 116 rows 270 cols
invariant :n9_34 + -1'SstopOK_4 + CstopOK_6 = 0
invariant :n8_11 + -1'n8_13 + Cstart_4 + -1'Cstart_6 = 0
invariant :n7_11 + -1'n7_13 + -1'Cstart_4 + Cstart_6 = 0
invariant :n8_31 + -1'n8_34 + Cstart_3 + -1'Cstart_6 = 0
invariant :n7_47 + -1'n7_48 + -1'Cstart_5 + Cstart_6 = 0
invariant :n9_20 + -1'SstopOK_2 + CstopOK_6 = 0
invariant :n6_4 + -1'n6_6 + n5_4 + -1'n5_6 = 0
invariant :n9_9 + -1'SstopOK_1 + CstopOK_2 = 0
invariant :n7_4 + -1'n7_6 + -1'Cstart_4 + Cstart_6 = 0
invariant :n9_16 + -1'SstopOK_2 + CstopOK_2 = 0
invariant :n8_3 + -1'n8_6 + Cstart_3 + -1'Cstart_6 = 0
invariant :n9_35 + -1'SstopOK_5 + CstopOK_0 = 0
invariant :n8_17 + -1'n8_20 + Cstart_3 + -1'Cstart_6 = 0
invariant :n8_14 + -1'n8_20 + Cstart_0 + -1'Cstart_6 = 0
invariant :n8_25 + -1'n8_27 + Cstart_4 + -1'Cstart_6 = 0
invariant :n9_38 + -1'SstopOK_5 + CstopOK_3 = 0
invariant :n9_24 + -1'SstopOK_3 + CstopOK_3 = 0
invariant :n7_29 + -1'n7_34 + -1'Cstart_1 + Cstart_6 = 0
invariant :n8_19 + -1'n8_20 + Cstart_5 + -1'Cstart_6 = 0
invariant :n8_36 + -1'n8_41 + Cstart_1 + -1'Cstart_6 = 0
invariant :n9_11 + -1'SstopOK_1 + CstopOK_4 = 0
invariant :n7_24 + -1'n7_27 + -1'Cstart_3 + Cstart_6 = 0
invariant :n2_4 + -1'n2_6 + n1_4 + -1'n1_6 = 0
invariant :n7_7 + -1'n7_13 + -1'Cstart_0 + Cstart_6 = 0
invariant :n7_9 + -1'n7_13 + -1'Cstart_2 + Cstart_6 = 0
invariant :n2_5 + -1'n2_6 + n1_5 + -1'n1_6 = 0
invariant :n8_21 + -1'n8_27 + Cstart_0 + -1'Cstart_6 = 0
invariant :n7_46 + -1'n7_48 + -1'Cstart_4 + Cstart_6 = 0
invariant :n2_3 + -1'n2_6 + n1_3 + -1'n1_6 = 0
invariant :n8_12 + -1'n8_13 + Cstart_5 + -1'Cstart_6 = 0
invariant :n7_37 + -1'n7_41 + -1'Cstart_2 + Cstart_6 = 0
invariant :n8_18 + -1'n8_20 + Cstart_4 + -1'Cstart_6 = 0
invariant :n8_28 + -1'n8_34 + Cstart_0 + -1'Cstart_6 = 0
invariant :n7_38 + -1'n7_41 + -1'Cstart_3 + Cstart_6 = 0
invariant :n7_26 + -1'n7_27 + -1'Cstart_5 + Cstart_6 = 0
invariant :n7_21 + -1'n7_27 + -1'Cstart_0 + Cstart_6 = 0
invariant :n8_24 + -1'n8_27 + Cstart_3 + -1'Cstart_6 = 0
invariant :n8_43 + -1'n8_48 + Cstart_1 + -1'Cstart_6 = 0
invariant :n9_14 + -1'SstopOK_2 + CstopOK_0 = 0
invariant :n6_2 + -1'n6_6 + n5_2 + -1'n5_6 = 0
invariant :n9_33 + -1'SstopOK_4 + CstopOK_5 = 0
invariant :n7_16 + -1'n7_20 + -1'Cstart_2 + Cstart_6 = 0
invariant :n9_22 + -1'SstopOK_3 + CstopOK_1 = 0
invariant :n8_8 + -1'n8_13 + Cstart_1 + -1'Cstart_6 = 0
invariant :n7_39 + -1'n7_41 + -1'Cstart_4 + Cstart_6 = 0
invariant :n8_42 + -1'n8_48 + Cstart_0 + -1'Cstart_6 = 0
invariant :malicious_reservoir_0 + -1'c1_0 + -1'c1_1 + -1'c1_2 + -1'c1_3 + -1'c1_4 + -1'c1_5 + -1'c1_6 + -1'Cstart_0 + -1'Cstart_1 + -1'Cstart_2 + -1'Cstart_3 + -1'Cstart_4 + -1'Cstart_5 + -1'Cstart_6 + -1'Sstart_0 + -1'Sstart_1 + -1'Sstart_2 + -1'Sstart_3 + -1'Sstart_4 + -1'Sstart_5 + -1'Sstart_6 + -1's2_0 + -1's2_1 + -1's2_2 + -1's2_3 + -1's2_4 + -1's2_5 + -1's2_6 + -1's3_0 + -1's3_1 + -1's3_2 + -1's3_3 + -1's3_4 + -1's3_5 + -1's3_6 + -1's4_0 + -1's4_1 + -1's4_2 + -1's4_3 + -1's4_4 + -1's4_5 + -1's4_6 + -1's5_0 + -1's5_1 + -1's5_2 + -1's5_3 + -1's5_4 + -1's5_5 + -1's5_6 + -1's6_0 + -1's6_1 + -1's6_2 + -1's6_3 + -1's6_4 + -1's6_5 + -1's6_6 + -1'SstopOK_0 + -1'SstopOK_1 + -1'SstopOK_2 + -1'SstopOK_3 + -1'SstopOK_4 + -1'SstopOK_5 + -1'SstopOK_6 + -1'CstopOK_0 + -1'CstopOK_1 + -1'CstopOK_2 + -1'CstopOK_3 + -1'CstopOK_4 + -1'CstopOK_5 + -1'CstopOK_6 = -11
invariant :n9_7 + -1'SstopOK_1 + CstopOK_0 = 0
invariant :n7_28 + -1'n7_34 + -1'Cstart_0 + Cstart_6 = 0
invariant :n7_0 + -1'n7_6 + -1'Cstart_0 + Cstart_6 = 0
invariant :n9_43 + -1'SstopOK_6 + CstopOK_1 = 0
invariant :n9_44 + -1'SstopOK_6 + CstopOK_2 = 0
invariant :n6_3 + -1'n6_6 + n5_3 + -1'n5_6 = 0
invariant :n7_5 + -1'n7_6 + -1'Cstart_5 + Cstart_6 = 0
invariant :n8_33 + -1'n8_34 + Cstart_5 + -1'Cstart_6 = 0
invariant :n4_2 + -1'n4_6 + n3_2 + -1'n3_6 = 0
invariant :n8_7 + -1'n8_13 + Cstart_0 + -1'Cstart_6 = 0
invariant :n7_15 + -1'n7_20 + -1'Cstart_1 + Cstart_6 = 0
invariant :n9_27 + -1'SstopOK_3 + CstopOK_6 = 0
invariant :n9_46 + -1'SstopOK_6 + CstopOK_4 = 0
invariant :n9_12 + -1'SstopOK_1 + CstopOK_5 = 0
invariant :n8_0 + -1'n8_6 + Cstart_0 + -1'Cstart_6 = 0
invariant :n4_5 + -1'n4_6 + n3_5 + -1'n3_6 = 0
invariant :n7_22 + -1'n7_27 + -1'Cstart_1 + Cstart_6 = 0
invariant :n7_2 + -1'n7_6 + -1'Cstart_2 + Cstart_6 = 0
invariant :n9_1 + -1'SstopOK_0 + CstopOK_1 = 0
invariant :n8_1 + -1'n8_6 + Cstart_1 + -1'Cstart_6 = 0
invariant :n8_2 + -1'n8_6 + Cstart_2 + -1'Cstart_6 = 0
invariant :n7_23 + -1'n7_27 + -1'Cstart_2 + Cstart_6 = 0
invariant :n9_5 + -1'SstopOK_0 + CstopOK_5 = 0
invariant :n8_47 + -1'n8_48 + Cstart_5 + -1'Cstart_6 = 0
invariant :n9_37 + -1'SstopOK_5 + CstopOK_2 = 0
invariant :n8_45 + -1'n8_48 + Cstart_3 + -1'Cstart_6 = 0
invariant :n9_10 + -1'SstopOK_1 + CstopOK_3 = 0
invariant :n7_40 + -1'n7_41 + -1'Cstart_5 + Cstart_6 = 0
invariant :n8_5 + -1'n8_6 + Cstart_5 + -1'Cstart_6 = 0
invariant :n7_44 + -1'n7_48 + -1'Cstart_2 + Cstart_6 = 0
invariant :n9_6 + -1'SstopOK_0 + CstopOK_6 = 0
invariant :n8_40 + -1'n8_41 + Cstart_5 + -1'Cstart_6 = 0
invariant :n2_1 + -1'n2_6 + n1_1 + -1'n1_6 = 0
invariant :n9_3 + -1'SstopOK_0 + CstopOK_3 = 0
invariant :n8_35 + -1'n8_41 + Cstart_0 + -1'Cstart_6 = 0
invariant :n7_35 + -1'n7_41 + -1'Cstart_0 + Cstart_6 = 0
invariant :n9_15 + -1'SstopOK_2 + CstopOK_1 = 0
invariant :n2_2 + -1'n2_6 + n1_2 + -1'n1_6 = 0
invariant :n9_42 + -1'SstopOK_6 + CstopOK_0 = 0
invariant :n8_16 + -1'n8_20 + Cstart_2 + -1'Cstart_6 = 0
invariant :n7_3 + -1'n7_6 + -1'Cstart_3 + Cstart_6 = 0
invariant :n4_0 + -1'n4_6 + n3_0 + -1'n3_6 = 0
invariant :CstopAbort_0 + c1_0 + c1_1 + c1_2 + c1_3 + c1_4 + c1_5 + c1_6 + Cstart_0 + Cstart_1 + Cstart_2 + Cstart_3 + Cstart_4 + Cstart_5 + Cstart_6 + CstopOK_0 + CstopOK_1 + CstopOK_2 + CstopOK_3 + CstopOK_4 + CstopOK_5 + CstopOK_6 = 7
invariant :n9_18 + -1'SstopOK_2 + CstopOK_4 = 0
invariant :n7_32 + -1'n7_34 + -1'Cstart_4 + Cstart_6 = 0
invariant :n9_2 + -1'SstopOK_0 + CstopOK_2 = 0
invariant :n9_40 + -1'SstopOK_5 + CstopOK_5 = 0
invariant :n8_29 + -1'n8_34 + Cstart_1 + -1'Cstart_6 = 0
invariant :n7_45 + -1'n7_48 + -1'Cstart_3 + Cstart_6 = 0
invariant :n8_9 + -1'n8_13 + Cstart_2 + -1'Cstart_6 = 0
invariant :n9_48 + -1'SstopOK_6 + CstopOK_6 = 0
invariant :n9_45 + -1'SstopOK_6 + CstopOK_3 = 0
invariant :n4_4 + -1'n4_6 + n3_4 + -1'n3_6 = 0
invariant :n9_8 + -1'SstopOK_1 + CstopOK_1 = 0
invariant :n8_46 + -1'n8_48 + Cstart_4 + -1'Cstart_6 = 0
invariant :n8_30 + -1'n8_34 + Cstart_2 + -1'Cstart_6 = 0
invariant :n9_23 + -1'SstopOK_3 + CstopOK_2 = 0
invariant :n7_8 + -1'n7_13 + -1'Cstart_1 + Cstart_6 = 0
invariant :n9_41 + -1'SstopOK_5 + CstopOK_6 = 0
invariant :n7_30 + -1'n7_34 + -1'Cstart_2 + Cstart_6 = 0
invariant :n4_3 + -1'n4_6 + n3_3 + -1'n3_6 = 0
invariant :n8_10 + -1'n8_13 + Cstart_3 + -1'Cstart_6 = 0
invariant :n9_29 + -1'SstopOK_4 + CstopOK_1 = 0
invariant :n7_43 + -1'n7_48 + -1'Cstart_1 + Cstart_6 = 0
invariant :n7_18 + -1'n7_20 + -1'Cstart_4 + Cstart_6 = 0
invariant :n9_0 + -1'SstopOK_0 + CstopOK_0 = 0
invariant :n8_15 + -1'n8_20 + Cstart_1 + -1'Cstart_6 = 0
invariant :n7_1 + -1'n7_6 + -1'Cstart_1 + Cstart_6 = 0
invariant :SstopAbort_0 + Sstart_0 + Sstart_1 + Sstart_2 + Sstart_3 + Sstart_4 + Sstart_5 + Sstart_6 + s2_0 + s2_1 + s2_2 + s2_3 + s2_4 + s2_5 + s2_6 + s3_0 + s3_1 + s3_2 + s3_3 + s3_4 + s3_5 + s3_6 + s4_0 + s4_1 + s4_2 + s4_3 + s4_4 + s4_5 + s4_6 + s5_0 + s5_1 + s5_2 + s5_3 + s5_4 + s5_5 + s5_6 + s6_0 + s6_1 + s6_2 + s6_3 + s6_4 + s6_5 + s6_6 + SstopOK_0 + SstopOK_1 + SstopOK_2 + SstopOK_3 + SstopOK_4 + SstopOK_5 + SstopOK_6 = 7
invariant :n7_17 + -1'n7_20 + -1'Cstart_3 + Cstart_6 = 0
invariant :n8_39 + -1'n8_41 + Cstart_4 + -1'Cstart_6 = 0
invariant :n6_5 + -1'n6_6 + n5_5 + -1'n5_6 = 0
invariant :n9_32 + -1'SstopOK_4 + CstopOK_4 = 0
invariant :n2_0 + -1'n2_6 + n1_0 + -1'n1_6 = 0
invariant :n7_36 + -1'n7_41 + -1'Cstart_1 + Cstart_6 = 0
invariant :n8_4 + -1'n8_6 + Cstart_4 + -1'Cstart_6 = 0
invariant :n7_42 + -1'n7_48 + -1'Cstart_0 + Cstart_6 = 0
invariant :n8_38 + -1'n8_41 + Cstart_3 + -1'Cstart_6 = 0
invariant :n7_12 + -1'n7_13 + -1'Cstart_5 + Cstart_6 = 0
invariant :n8_22 + -1'n8_27 + Cstart_1 + -1'Cstart_6 = 0
invariant :n6_1 + -1'n6_6 + n5_1 + -1'n5_6 = 0
invariant :n9_28 + -1'SstopOK_4 + CstopOK_0 = 0
invariant :n9_47 + -1'SstopOK_6 + CstopOK_5 = 0
invariant :n7_31 + -1'n7_34 + -1'Cstart_3 + Cstart_6 = 0
invariant :n9_19 + -1'SstopOK_2 + CstopOK_5 = 0
invariant :n7_10 + -1'n7_13 + -1'Cstart_3 + Cstart_6 = 0
invariant :n6_0 + -1'n6_6 + n5_0 + -1'n5_6 = 0
invariant :n9_17 + -1'SstopOK_2 + CstopOK_3 = 0
invariant :AstopAbort_0 + a5_0 + a4_0 + a3_0 + a2_0 + a1_0 + Astart_0 + AstopOK_0 = 1
invariant :n9_31 + -1'SstopOK_4 + CstopOK_3 = 0
invariant :n8_23 + -1'n8_27 + Cstart_2 + -1'Cstart_6 = 0
invariant :n9_36 + -1'SstopOK_5 + CstopOK_1 = 0
invariant :n4_1 + -1'n4_6 + n3_1 + -1'n3_6 = 0
invariant :n8_26 + -1'n8_27 + Cstart_5 + -1'Cstart_6 = 0
invariant :n9_30 + -1'SstopOK_4 + CstopOK_2 = 0
invariant :n7_19 + -1'n7_20 + -1'Cstart_5 + Cstart_6 = 0
invariant :n9_39 + -1'SstopOK_5 + CstopOK_4 = 0
invariant :n7_33 + -1'n7_34 + -1'Cstart_5 + Cstart_6 = 0
invariant :n9_21 + -1'SstopOK_3 + CstopOK_0 = 0
invariant :n7_25 + -1'n7_27 + -1'Cstart_4 + Cstart_6 = 0
invariant :n8_32 + -1'n8_34 + Cstart_4 + -1'Cstart_6 = 0
invariant :n8_37 + -1'n8_41 + Cstart_2 + -1'Cstart_6 = 0
invariant :n8_44 + -1'n8_48 + Cstart_2 + -1'Cstart_6 = 0
invariant :n9_26 + -1'SstopOK_3 + CstopOK_5 = 0
invariant :n9_13 + -1'SstopOK_1 + CstopOK_6 = 0
invariant :n9_25 + -1'SstopOK_3 + CstopOK_4 = 0
invariant :n9_4 + -1'SstopOK_0 + CstopOK_4 = 0
invariant :n7_14 + -1'n7_20 + -1'Cstart_0 + Cstart_6 = 0
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 6672 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 132 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, []((<>((LTLAP0==true)))U([]((LTLAP1==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 228 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLCardinality-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(((LTLAP2==true))U((LTLAP3==true))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 78 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLCardinality-01 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (<>(<>((LTLAP4==true))))U((LTLAP5==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 231 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLCardinality-02 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X(<>(X((LTLAP6==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 74 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLCardinality-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(<>([]((LTLAP7==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 207 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLCardinality-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (<>((LTLAP8==true)))U((LTLAP9==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 153 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLCardinality-05 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X((LTLAP10==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 95 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLCardinality-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, ([](X((LTLAP11==true))))U((LTLAP12==true)), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 100 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLCardinality-07 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP13==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 154 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLCardinality-08 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP6==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 231 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLCardinality-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP14==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 228 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLCardinality-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(((LTLAP15==true))U(<>((LTLAP16==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 136 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLCardinality-11 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP17==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 128 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLCardinality-12 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, (LTLAP18==true), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 145 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLCardinality-13 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, --when, --ltl, X([]([]((LTLAP19==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 1902 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLCardinality-14 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, --ltl, <>(<>(((LTLAP20==true))U((LTLAP21==true)))), --buchi-type=spotba], workingDir=/home/mcc/execution]
LTSmin run took 133 ms.
FORMULA QuasiCertifProtocol-COL-06-LTLCardinality-15 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1528280964603

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution LTLCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination LTLCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Jun 06, 2018 10:27:47 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
Jun 06, 2018 10:27:47 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 06, 2018 10:27:47 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
Jun 06, 2018 10:28:08 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Load time of PNML (colored model parsed with PNMLFW) : 21785 ms
Jun 06, 2018 10:28:08 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 30 places.
Jun 06, 2018 10:28:08 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Computed order using colors.
Jun 06, 2018 10:28:08 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: sort/places :tsidxtsid->n9,n8,n7,
Dot->malicious_reservoir,CstopAbort,SstopAbort,AstopAbort,a5,a4,a3,a2,a1,Astart,AstopOK,
tsid->n6,n5,n4,n3,n2,n1,c1,Cstart,Sstart,s2,s3,s4,s5,s6,SstopOK,CstopOK,

Jun 06, 2018 10:28:09 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 26 transitions.
Jun 06, 2018 10:28:09 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Computed order based on color domains.
Jun 06, 2018 10:28:09 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 19 ms
Jun 06, 2018 10:28:09 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 207 ms
Jun 06, 2018 10:28:10 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/LTLCardinality.pnml.gal : 13 ms
Jun 06, 2018 10:28:10 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSLTLTools
INFO: Time to serialize properties into /home/mcc/execution/LTLCardinality.ltl : 3 ms
Jun 06, 2018 10:28:11 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 74 transitions. Expanding to a total of 123 deterministic transitions.
Jun 06, 2018 10:28:11 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 7 ms.
Jun 06, 2018 10:28:12 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 155 place invariants in 171 ms
Jun 06, 2018 10:28:13 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 270 variables to be positive in 931 ms
Jun 06, 2018 10:28:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 116 transitions.
Jun 06, 2018 10:28:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/116 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 06, 2018 10:28:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 14 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 06, 2018 10:28:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 116 transitions.
Jun 06, 2018 10:28:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 10 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 06, 2018 10:28:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 116 transitions.
Jun 06, 2018 10:28:19 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/116) took 328 ms. Total solver calls (SAT/UNSAT): 104(104/0)
Jun 06, 2018 10:28:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(5/116) took 3613 ms. Total solver calls (SAT/UNSAT): 609(609/0)
Jun 06, 2018 10:28:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(11/116) took 7550 ms. Total solver calls (SAT/UNSAT): 1182(1182/0)
Jun 06, 2018 10:28:29 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(16/116) took 11053 ms. Total solver calls (SAT/UNSAT): 1632(1632/0)
Jun 06, 2018 10:28:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(23/116) took 14125 ms. Total solver calls (SAT/UNSAT): 2220(2220/0)
Jun 06, 2018 10:28:36 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(29/116) took 17413 ms. Total solver calls (SAT/UNSAT): 2685(2685/0)
Jun 06, 2018 10:28:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(36/116) took 20864 ms. Total solver calls (SAT/UNSAT): 3182(3182/0)
Jun 06, 2018 10:28:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(41/116) took 23898 ms. Total solver calls (SAT/UNSAT): 3507(3507/0)
Jun 06, 2018 10:28:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(50/116) took 27063 ms. Total solver calls (SAT/UNSAT): 3939(3922/17)
Jun 06, 2018 10:28:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(59/116) took 30178 ms. Total solver calls (SAT/UNSAT): 4275(4240/35)
Jun 06, 2018 10:28:52 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(70/116) took 33330 ms. Total solver calls (SAT/UNSAT): 4762(4727/35)
Jun 06, 2018 10:28:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(79/116) took 36784 ms. Total solver calls (SAT/UNSAT): 5077(5042/35)
Jun 06, 2018 10:28:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(88/116) took 39870 ms. Total solver calls (SAT/UNSAT): 5311(5276/35)
Jun 06, 2018 10:29:01 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(102/116) took 42964 ms. Total solver calls (SAT/UNSAT): 5500(5465/35)
Jun 06, 2018 10:29:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 44595 ms. Total solver calls (SAT/UNSAT): 5536(5486/50)
Jun 06, 2018 10:29:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 116 transitions.
Jun 06, 2018 10:29:10 AM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Jun 06, 2018 10:29:11 AM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Jun 06, 2018 10:29:11 AM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Skipping mayMatrices nes/nds SMT solver raised an error :unknown
java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.computeDoNotAccord(NecessaryEnablingsolver.java:628)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:538)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
Jun 06, 2018 10:29:11 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 60932ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="QuasiCertifProtocol-COL-06"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/QuasiCertifProtocol-COL-06.tgz
mv QuasiCertifProtocol-COL-06 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is QuasiCertifProtocol-COL-06, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r188-qhx2-152732140200043"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;