Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.....................................
/home/mcc/execution
total 208K
-rw-r--r-- 1 mcc users 3.3K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 14K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.5K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 9.4K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.4K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 113 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 351 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 3.3K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 20K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_pt
-rw-r--r-- 1 mcc users 2 May 15 18:50 instance
-rw-r--r-- 1 mcc users 5 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 41K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is LamportFastMutEx-COL-5, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r117-csrt-152666476500082
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-00
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-01
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-02
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-03
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-04
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-05
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-06
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-07
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-08
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-09
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-10
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-11
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-12
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-13
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-14
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1527239848343

09:17:30.896 [main] ERROR PNML validation - The rng grammar file can't be accessed : www.pnml.org
09:17:30.899 [main] ERROR import - Grammar file errors have been raised, the validation can't be done, process will continue without Grammar validation
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-00 with value :((!(((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5)>=3)||((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)<=(((((P_start_1_0+P_start_1_1)+P_start_1_2)+P_start_1_3)+P_start_1_4)+P_start_1_5))))||(!(((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5)>=1)||((((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)>=1))))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-01 with value :((!((((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)+P_setx_3_5)>=2))||((((((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)+P_awaity_5)<=(((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5))||((((((((((((((((((((((((((((((((((((wait_0+wait_1)+wait_2)+wait_3)+wait_4)+wait_5)+wait_6)+wait_7)+wait_8)+wait_9)+wait_10)+wait_11)+wait_12)+wait_13)+wait_14)+wait_15)+wait_16)+wait_17)+wait_18)+wait_19)+wait_20)+wait_21)+wait_22)+wait_23)+wait_24)+wait_25)+wait_26)+wait_27)+wait_28)+wait_29)+wait_30)+wait_31)+wait_32)+wait_33)+wait_34)+wait_35)>=1))||((((((((((((((((((((((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)+done_16)+done_17)+done_18)+done_19)+done_20)+done_21)+done_22)+done_23)+done_24)+done_25)+done_26)+done_27)+done_28)+done_29)+done_30)+done_31)+done_32)+done_33)+done_34)+done_35)>=3)))
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-02 with value :((((((P_CS_21_0+P_CS_21_1)+P_CS_21_2)+P_CS_21_3)+P_CS_21_4)+P_CS_21_5)>=2)
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-03 with value :(((((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)+P_awaity_5)>=1)&&(!((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)<=(((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5))))
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-04 with value :(((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)>=1)&&((((((((((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7)+b_8)+b_9)+b_10)+b_11)>=1)&&((((((((((((((((((((((((((((((((((((wait_0+wait_1)+wait_2)+wait_3)+wait_4)+wait_5)+wait_6)+wait_7)+wait_8)+wait_9)+wait_10)+wait_11)+wait_12)+wait_13)+wait_14)+wait_15)+wait_16)+wait_17)+wait_18)+wait_19)+wait_20)+wait_21)+wait_22)+wait_23)+wait_24)+wait_25)+wait_26)+wait_27)+wait_28)+wait_29)+wait_30)+wait_31)+wait_32)+wait_33)+wait_34)+wait_35)>=1))&&((((((P_sety_9_0+P_sety_9_1)+P_sety_9_2)+P_sety_9_3)+P_sety_9_4)+P_sety_9_5)<=(((((P_start_1_0+P_start_1_1)+P_start_1_2)+P_start_1_3)+P_start_1_4)+P_start_1_5))))
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-05 with value :((((((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)+P_ify0_4_5)<=(((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)+P_awaity_5))&&(((((((y_0+y_1)+y_2)+y_3)+y_4)+y_5)>=1)&&((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)<=(((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)+P_setbi_24_5))))&&((((((((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7)+b_8)+b_9)+b_10)+b_11)<=(((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-06 with value :(!((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)>=1))
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-07 with value :((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)>=2)
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-08 with value :(((((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)<=(((((y_0+y_1)+y_2)+y_3)+y_4)+y_5))||(((((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)+P_setx_3_5)>=3)||(((((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)+P_awaity_5)<=(((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5))||((((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)+P_ify0_4_5)<=(((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5)))))
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-09 with value :((((((P_await_13_0+P_await_13_1)+P_await_13_2)+P_await_13_3)+P_await_13_4)+P_await_13_5)>=1)
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-10 with value :((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5)>=2)
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-11 with value :(((((((P_CS_21_0+P_CS_21_1)+P_CS_21_2)+P_CS_21_3)+P_CS_21_4)+P_CS_21_5)<=(((((x_0+x_1)+x_2)+x_3)+x_4)+x_5))||((!((((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)+P_setbi_24_5)<=(((((P_sety_9_0+P_sety_9_1)+P_sety_9_2)+P_sety_9_3)+P_sety_9_4)+P_sety_9_5)))&&(!((((((y_0+y_1)+y_2)+y_3)+y_4)+y_5)<=(((((P_sety_9_0+P_sety_9_1)+P_sety_9_2)+P_sety_9_3)+P_sety_9_4)+P_sety_9_5)))))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-12 with value :(!((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5)>=3))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-13 with value :((!(((((((y_0+y_1)+y_2)+y_3)+y_4)+y_5)>=2)&&((((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)+P_setx_3_5)<=(((((P_start_1_0+P_start_1_1)+P_start_1_2)+P_start_1_3)+P_start_1_4)+P_start_1_5))))||(!(((((((P_ifxi_10_0+P_ifxi_10_1)+P_ifxi_10_2)+P_ifxi_10_3)+P_ifxi_10_4)+P_ifxi_10_5)<=(((((P_setbi_11_0+P_setbi_11_1)+P_setbi_11_2)+P_setbi_11_3)+P_setbi_11_4)+P_setbi_11_5))||((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5)>=3))))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-14 with value :((((((((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7)+b_8)+b_9)+b_10)+b_11)>=2)
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-15 with value :((((((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)+P_awaity_5)>=3)&&(((((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)<=(((((P_start_1_0+P_start_1_1)+P_start_1_2)+P_start_1_3)+P_start_1_4)+P_start_1_5))&&((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)<=(((((P_setbi_11_0+P_setbi_11_1)+P_setbi_11_2)+P_setbi_11_3)+P_setbi_11_4)+P_setbi_11_5))))||(!(((((((P_await_13_0+P_await_13_1)+P_await_13_2)+P_await_13_3)+P_await_13_4)+P_await_13_5)>=3)&&((((((P_setbi_11_0+P_setbi_11_1)+P_setbi_11_2)+P_setbi_11_3)+P_setbi_11_4)+P_setbi_11_5)>=3))))
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 246
// Phase 1: matrix 246 rows 174 cols
invariant :P_start_1_1 + P_setx_3_1 + P_setbi_5_1 + P_ify0_4_1 + P_sety_9_1 + P_ifxi_10_1 + P_setbi_11_1 + P_fordo_12_1 + P_await_13_1 + P_ifyi_15_1 + P_awaity_1 + P_CS_21_1 + P_setbi_24_1 = 1
invariant :wait_11 + -1'P_await_13_1 + done_11 = 0
invariant :wait_6 + done_6 = 0
invariant :wait_9 + -1'P_await_13_1 + done_9 = 0
invariant :wait_13 + -1'P_await_13_2 + done_13 = 0
invariant :wait_35 + -1'P_await_13_5 + done_35 = 0
invariant :wait_23 + -1'P_await_13_3 + done_23 = 0
invariant :wait_5 + -1'P_await_13_0 + done_5 = 0
invariant :wait_25 + -1'P_await_13_4 + done_25 = 0
invariant :wait_31 + -1'P_await_13_5 + done_31 = 0
invariant :wait_10 + -1'P_await_13_1 + done_10 = 0
invariant :y_0 + y_1 + y_2 + y_3 + y_4 + y_5 = 1
invariant :b_2 + b_3 = 1
invariant :wait_16 + -1'P_await_13_2 + done_16 = 0
invariant :wait_20 + -1'P_await_13_3 + done_20 = 0
invariant :wait_26 + -1'P_await_13_4 + done_26 = 0
invariant :wait_29 + -1'P_await_13_4 + done_29 = 0
invariant :P_start_1_5 + P_setx_3_5 + P_setbi_5_5 + P_ify0_4_5 + P_sety_9_5 + P_ifxi_10_5 + P_setbi_11_5 + P_fordo_12_5 + P_await_13_5 + P_ifyi_15_5 + P_awaity_5 + P_CS_21_5 + P_setbi_24_5 = 1
invariant :wait_30 + done_30 = 0
invariant :wait_22 + -1'P_await_13_3 + done_22 = 0
invariant :P_start_1_4 + P_setx_3_4 + P_setbi_5_4 + P_ify0_4_4 + P_sety_9_4 + P_ifxi_10_4 + P_setbi_11_4 + P_fordo_12_4 + P_await_13_4 + P_ifyi_15_4 + P_awaity_4 + P_CS_21_4 + P_setbi_24_4 = 1
invariant :wait_27 + -1'P_await_13_4 + done_27 = 0
invariant :wait_21 + -1'P_await_13_3 + done_21 = 0
invariant :wait_33 + -1'P_await_13_5 + done_33 = 0
invariant :x_0 + x_1 + x_2 + x_3 + x_4 + x_5 = 1
invariant :wait_1 + -1'P_await_13_0 + done_1 = 0
invariant :P_start_1_2 + P_setx_3_2 + P_setbi_5_2 + P_ify0_4_2 + P_sety_9_2 + P_ifxi_10_2 + P_setbi_11_2 + P_fordo_12_2 + P_await_13_2 + P_ifyi_15_2 + P_awaity_2 + P_CS_21_2 + P_setbi_24_2 = 1
invariant :wait_17 + -1'P_await_13_2 + done_17 = 0
invariant :wait_18 + done_18 = 0
invariant :P_start_1_3 + P_setx_3_3 + P_setbi_5_3 + P_ify0_4_3 + P_sety_9_3 + P_ifxi_10_3 + P_setbi_11_3 + P_fordo_12_3 + P_await_13_3 + P_ifyi_15_3 + P_awaity_3 + P_CS_21_3 + P_setbi_24_3 = 1
invariant :b_4 + b_5 = 1
invariant :wait_0 + done_0 = 0
invariant :b_10 + b_11 = 1
invariant :wait_8 + -1'P_await_13_1 + done_8 = 0
invariant :wait_7 + -1'P_await_13_1 + done_7 = 0
invariant :P_start_1_0 + P_setx_3_0 + P_setbi_5_0 + P_ify0_4_0 + P_sety_9_0 + P_ifxi_10_0 + P_setbi_11_0 + P_fordo_12_0 + P_await_13_0 + P_ifyi_15_0 + P_awaity_0 + P_CS_21_0 + P_setbi_24_0 = 0
invariant :wait_3 + -1'P_await_13_0 + done_3 = 0
invariant :wait_28 + -1'P_await_13_4 + done_28 = 0
invariant :wait_34 + -1'P_await_13_5 + done_34 = 0
invariant :b_8 + b_9 = 1
invariant :wait_19 + -1'P_await_13_3 + done_19 = 0
invariant :wait_14 + -1'P_await_13_2 + done_14 = 0
invariant :wait_24 + done_24 = 0
invariant :wait_4 + -1'P_await_13_0 + done_4 = 0
invariant :wait_32 + -1'P_await_13_5 + done_32 = 0
invariant :wait_12 + done_12 = 0
invariant :b_6 + b_7 = 1
invariant :b_0 + b_1 = 0
invariant :wait_2 + -1'P_await_13_0 + done_2 = 0
invariant :wait_15 + -1'P_await_13_2 + done_15 = 0
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 246
// Phase 1: matrix 246 rows 174 cols
invariant :P_start_1_1 + P_setx_3_1 + P_setbi_5_1 + P_ify0_4_1 + P_sety_9_1 + P_ifxi_10_1 + P_setbi_11_1 + P_fordo_12_1 + P_await_13_1 + P_ifyi_15_1 + P_awaity_1 + P_CS_21_1 + P_setbi_24_1 = 1
invariant :wait_11 + -1'P_await_13_1 + done_11 = 0
invariant :wait_6 + done_6 = 0
invariant :wait_9 + -1'P_await_13_1 + done_9 = 0
invariant :wait_13 + -1'P_await_13_2 + done_13 = 0
invariant :wait_35 + -1'P_await_13_5 + done_35 = 0
invariant :wait_23 + -1'P_await_13_3 + done_23 = 0
invariant :wait_5 + -1'P_await_13_0 + done_5 = 0
invariant :wait_25 + -1'P_await_13_4 + done_25 = 0
invariant :wait_31 + -1'P_await_13_5 + done_31 = 0
invariant :wait_10 + -1'P_await_13_1 + done_10 = 0
invariant :y_0 + y_1 + y_2 + y_3 + y_4 + y_5 = 1
invariant :b_2 + b_3 = 1
invariant :wait_16 + -1'P_await_13_2 + done_16 = 0
invariant :wait_20 + -1'P_await_13_3 + done_20 = 0
invariant :wait_26 + -1'P_await_13_4 + done_26 = 0
invariant :wait_29 + -1'P_await_13_4 + done_29 = 0
invariant :P_start_1_5 + P_setx_3_5 + P_setbi_5_5 + P_ify0_4_5 + P_sety_9_5 + P_ifxi_10_5 + P_setbi_11_5 + P_fordo_12_5 + P_await_13_5 + P_ifyi_15_5 + P_awaity_5 + P_CS_21_5 + P_setbi_24_5 = 1
invariant :wait_30 + done_30 = 0
invariant :wait_22 + -1'P_await_13_3 + done_22 = 0
invariant :P_start_1_4 + P_setx_3_4 + P_setbi_5_4 + P_ify0_4_4 + P_sety_9_4 + P_ifxi_10_4 + P_setbi_11_4 + P_fordo_12_4 + P_await_13_4 + P_ifyi_15_4 + P_awaity_4 + P_CS_21_4 + P_setbi_24_4 = 1
invariant :wait_27 + -1'P_await_13_4 + done_27 = 0
invariant :wait_21 + -1'P_await_13_3 + done_21 = 0
invariant :wait_33 + -1'P_await_13_5 + done_33 = 0
invariant :x_0 + x_1 + x_2 + x_3 + x_4 + x_5 = 1
invariant :wait_1 + -1'P_await_13_0 + done_1 = 0
invariant :P_start_1_2 + P_setx_3_2 + P_setbi_5_2 + P_ify0_4_2 + P_sety_9_2 + P_ifxi_10_2 + P_setbi_11_2 + P_fordo_12_2 + P_await_13_2 + P_ifyi_15_2 + P_awaity_2 + P_CS_21_2 + P_setbi_24_2 = 1
invariant :wait_17 + -1'P_await_13_2 + done_17 = 0
invariant :wait_18 + done_18 = 0
invariant :P_start_1_3 + P_setx_3_3 + P_setbi_5_3 + P_ify0_4_3 + P_sety_9_3 + P_ifxi_10_3 + P_setbi_11_3 + P_fordo_12_3 + P_await_13_3 + P_ifyi_15_3 + P_awaity_3 + P_CS_21_3 + P_setbi_24_3 = 1
invariant :b_4 + b_5 = 1
invariant :wait_0 + done_0 = 0
invariant :b_10 + b_11 = 1
invariant :wait_8 + -1'P_await_13_1 + done_8 = 0
invariant :wait_7 + -1'P_await_13_1 + done_7 = 0
invariant :P_start_1_0 + P_setx_3_0 + P_setbi_5_0 + P_ify0_4_0 + P_sety_9_0 + P_ifxi_10_0 + P_setbi_11_0 + P_fordo_12_0 + P_await_13_0 + P_ifyi_15_0 + P_awaity_0 + P_CS_21_0 + P_setbi_24_0 = 0
invariant :wait_3 + -1'P_await_13_0 + done_3 = 0
invariant :wait_28 + -1'P_await_13_4 + done_28 = 0
invariant :wait_34 + -1'P_await_13_5 + done_34 = 0
invariant :b_8 + b_9 = 1
invariant :wait_19 + -1'P_await_13_3 + done_19 = 0
invariant :wait_14 + -1'P_await_13_2 + done_14 = 0
invariant :wait_24 + done_24 = 0
invariant :wait_4 + -1'P_await_13_0 + done_4 = 0
invariant :wait_32 + -1'P_await_13_5 + done_32 = 0
invariant :wait_12 + done_12 = 0
invariant :b_6 + b_7 = 1
invariant :b_0 + b_1 = 0
invariant :wait_2 + -1'P_await_13_0 + done_2 = 0
invariant :wait_15 + -1'P_await_13_2 + done_15 = 0
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-05 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-08 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-13 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-14 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-15 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 12691 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 429 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality00==true], workingDir=/home/mcc/execution]
LTSmin run took 898 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-00 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality01==true], workingDir=/home/mcc/execution]
LTSmin run took 1216 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality02==true], workingDir=/home/mcc/execution]
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx\_COL\_5\_flat\_flat,5.30682e+08,430.611,3526620,2,677728,5,1.15637e+07,6,0,1020,1.6814e+07,0
Total reachable state count : 530682432

Verifying 16 reachability properties.
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-00 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-00,1,430.989,3526652,2,175,6,1.15637e+07,7,0,1071,1.6814e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-01 does not hold.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-01,22505,432.979,3526684,2,28159,7,1.15637e+07,8,0,6538,1.6814e+07,0
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-02 does not hold.
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-02 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : LamportFastMutEx-COL-5-ReachabilityCardinality-02

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-02,0,434.214,3526748,1,0,7,1.15637e+07,9,0,6549,1.6814e+07,0
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-03 is true.
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-03 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-03,1,434.221,3526748,2,175,8,1.15637e+07,10,0,6570,1.6814e+07,0
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-04 is true.
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-04 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-04,3.9978e+07,450.604,3526748,2,374535,9,1.15637e+07,11,0,24727,1.6814e+07,0
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-05 does not hold.
No reachable states exhibit your property : LamportFastMutEx-COL-5-ReachabilityCardinality-05

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-05,0,453.645,3526748,1,0,9,1.15637e+07,12,0,24783,1.6814e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-06 does not hold.
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-06 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-06,3,453.752,3526748,2,179,10,1.15637e+07,13,0,24784,1.6814e+07,0
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-07 is true.
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-07 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-07,1,453.786,3526748,2,175,11,1.15637e+07,14,0,24793,1.6814e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-08 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-08,0,454.772,3526748,1,0,11,1.15637e+07,15,0,24866,1.6814e+07,0
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-09 is true.
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-09 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-09,48,454.774,3526748,2,423,12,1.15637e+07,16,0,24872,1.6814e+07,0
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-10 is true.
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-10 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-10,3,454.776,3526748,2,179,13,1.15637e+07,17,0,24883,1.6814e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-11 is true.
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-11 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-11,0,455.907,3526748,1,0,13,1.15637e+07,18,0,24919,1.6814e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-12 does not hold.
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-12 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-12,1,455.912,3526748,2,175,14,1.15637e+07,19,0,24931,1.6814e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-13 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-13,0,457.538,3526748,1,0,14,1.15637e+07,20,0,24960,1.6814e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-14 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-14,0,458.187,3526748,1,0,14,1.15637e+07,21,0,24983,1.6814e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-15 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-15,0,459.339,3526748,1,0,14,1.15637e+07,22,0,25121,1.6814e+07,0
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527240323019

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 25, 2018 9:17:30 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 25, 2018 9:17:30 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 25, 2018 9:17:30 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
May 25, 2018 9:17:31 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Load time of PNML (colored model parsed with PNMLFW) : 979 ms
May 25, 2018 9:17:31 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 18 places.
May 25, 2018 9:17:31 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Computed order using colors.
May 25, 2018 9:17:31 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: sort/places :pid * pid->wait,done,
pid * bool->b,
pid->P-start_1,x,y,P-setx_3,P-setbi_5,P-ify0_4,P-sety_9,P-ifxi_10,P-setbi_11,P-fordo_12,P-await_13,P-ifyi_15,P-awaity,P-CS_21,P-setbi_24,

May 25, 2018 9:17:31 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 17 transitions.
May 25, 2018 9:17:31 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Computed order based on color domains.
May 25, 2018 9:17:31 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 8 ms
May 25, 2018 9:17:31 AM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $i and $y of transition T_yeqi_15
May 25, 2018 9:17:31 AM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $i and $x of transition T_xeqi_10
May 25, 2018 9:17:31 AM fr.lip6.move.gal.instantiate.Instantiator instantiateParameters
INFO: On-the-fly reduction of False transitions avoided exploring 13.0 instantiations of transitions. Total transitions/syncs built is 333
May 25, 2018 9:17:31 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 92 ms
May 25, 2018 9:17:32 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 36 ms
May 25, 2018 9:17:32 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 11 ms
May 25, 2018 9:17:32 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 2 ms
May 25, 2018 9:17:32 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 31 ms
May 25, 2018 9:17:32 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 82 transitions. Expanding to a total of 399 deterministic transitions.
May 25, 2018 9:17:32 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 82 transitions. Expanding to a total of 399 deterministic transitions.
May 25, 2018 9:17:32 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 17 ms.
May 25, 2018 9:17:32 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 8 ms.
May 25, 2018 9:17:32 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 50 place invariants in 72 ms
May 25, 2018 9:17:32 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 16 in 673 ms.
May 25, 2018 9:17:32 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(UNSAT) depth K=0 took 11 ms
May 25, 2018 9:17:32 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-01(UNSAT) depth K=0 took 7 ms
May 25, 2018 9:17:32 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(UNSAT) depth K=0 took 7 ms
May 25, 2018 9:17:32 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(UNSAT) depth K=0 took 6 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(UNSAT) depth K=0 took 8 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(UNSAT) depth K=0 took 12 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(UNSAT) depth K=0 took 6 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(UNSAT) depth K=0 took 7 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(UNSAT) depth K=0 took 14 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(UNSAT) depth K=0 took 6 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 82 transitions. Expanding to a total of 399 deterministic transitions.
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(UNSAT) depth K=0 took 20 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 4 ms.
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(UNSAT) depth K=0 took 6 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(UNSAT) depth K=0 took 6 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(UNSAT) depth K=0 took 10 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-14(UNSAT) depth K=0 took 19 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-15(UNSAT) depth K=0 took 8 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(UNSAT) depth K=1 took 8 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-01(UNSAT) depth K=1 took 39 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(UNSAT) depth K=1 took 11 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(UNSAT) depth K=1 took 11 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(UNSAT) depth K=1 took 21 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 50 place invariants in 26 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(UNSAT) depth K=1 took 14 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(UNSAT) depth K=1 took 11 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(UNSAT) depth K=1 took 4 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(UNSAT) depth K=1 took 17 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(UNSAT) depth K=1 took 12 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(UNSAT) depth K=1 took 16 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(UNSAT) depth K=1 took 15 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(UNSAT) depth K=1 took 24 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(UNSAT) depth K=1 took 5 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-14(UNSAT) depth K=1 took 12 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-15(UNSAT) depth K=1 took 15 ms
May 25, 2018 9:17:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(UNSAT) depth K=2 took 460 ms
May 25, 2018 9:17:34 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-01(UNSAT) depth K=2 took 314 ms
May 25, 2018 9:17:34 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(UNSAT) depth K=2 took 98 ms
May 25, 2018 9:17:34 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(UNSAT) depth K=2 took 181 ms
May 25, 2018 9:17:34 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(UNSAT) depth K=2 took 304 ms
May 25, 2018 9:17:34 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 174 variables to be positive in 2043 ms
May 25, 2018 9:17:34 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 318 transitions.
May 25, 2018 9:17:34 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/318 took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 25, 2018 9:17:34 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 36 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 25, 2018 9:17:34 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 318 transitions.
May 25, 2018 9:17:34 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(UNSAT) depth K=2 took 133 ms
May 25, 2018 9:17:34 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 30 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 25, 2018 9:17:34 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(UNSAT) depth K=2 took 53 ms
May 25, 2018 9:17:35 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(UNSAT) depth K=2 took 84 ms
May 25, 2018 9:17:35 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 174 variables to be positive in 1930 ms
May 25, 2018 9:17:35 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(UNSAT) depth K=2 took 299 ms
May 25, 2018 9:17:35 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(UNSAT) depth K=2 took 72 ms
May 25, 2018 9:17:35 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(UNSAT) depth K=2 took 237 ms
May 25, 2018 9:17:35 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(UNSAT) depth K=2 took 194 ms
May 25, 2018 9:17:35 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(UNSAT) depth K=2 took 93 ms
May 25, 2018 9:17:35 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(UNSAT) depth K=2 took 37 ms
May 25, 2018 9:17:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-14(UNSAT) depth K=2 took 58 ms
May 25, 2018 9:17:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-15(UNSAT) depth K=2 took 95 ms
May 25, 2018 9:17:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-00
May 25, 2018 9:17:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(SAT) depth K=0 took 965 ms
May 25, 2018 9:17:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-01
May 25, 2018 9:17:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-01(SAT) depth K=0 took 295 ms
May 25, 2018 9:17:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-02
May 25, 2018 9:17:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(SAT) depth K=0 took 230 ms
May 25, 2018 9:17:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-03
May 25, 2018 9:17:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(SAT) depth K=0 took 250 ms
May 25, 2018 9:17:37 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-04
May 25, 2018 9:17:37 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(SAT) depth K=0 took 577 ms
May 25, 2018 9:17:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(UNSAT) depth K=3 took 2172 ms
May 25, 2018 9:17:39 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate LamportFastMutEx-COL-5-ReachabilityCardinality-05
May 25, 2018 9:17:39 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-COL-5-ReachabilityCardinality-05
May 25, 2018 9:17:39 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(FALSE) depth K=0 took 2367 ms
May 25, 2018 9:17:40 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-06
May 25, 2018 9:17:40 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(SAT) depth K=0 took 225 ms
May 25, 2018 9:17:40 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-07
May 25, 2018 9:17:40 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(SAT) depth K=0 took 402 ms
May 25, 2018 9:17:41 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant LamportFastMutEx-COL-5-ReachabilityCardinality-08
May 25, 2018 9:17:41 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-COL-5-ReachabilityCardinality-08
May 25, 2018 9:17:41 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(TRUE) depth K=0 took 1286 ms
May 25, 2018 9:17:41 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-09
May 25, 2018 9:17:41 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(SAT) depth K=0 took 200 ms
May 25, 2018 9:17:42 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-10
May 25, 2018 9:17:42 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(SAT) depth K=0 took 664 ms
May 25, 2018 9:17:42 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-01(UNSAT) depth K=3 took 4470 ms
May 25, 2018 9:17:42 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-11
May 25, 2018 9:17:42 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(SAT) depth K=0 took 208 ms
May 25, 2018 9:17:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-12
May 25, 2018 9:17:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(SAT) depth K=0 took 583 ms
May 25, 2018 9:17:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant LamportFastMutEx-COL-5-ReachabilityCardinality-13
May 25, 2018 9:17:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-COL-5-ReachabilityCardinality-13
May 25, 2018 9:17:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(TRUE) depth K=0 took 580 ms
May 25, 2018 9:17:44 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant LamportFastMutEx-COL-5-ReachabilityCardinality-14
May 25, 2018 9:17:44 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-COL-5-ReachabilityCardinality-14
May 25, 2018 9:17:44 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-14(TRUE) depth K=0 took 205 ms
May 25, 2018 9:17:44 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant LamportFastMutEx-COL-5-ReachabilityCardinality-15
May 25, 2018 9:17:44 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-COL-5-ReachabilityCardinality-15
May 25, 2018 9:17:44 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-15(TRUE) depth K=0 took 400 ms
May 25, 2018 9:17:44 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(UNSAT) depth K=3 took 2105 ms
May 25, 2018 9:17:45 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(UNSAT) depth K=3 took 410 ms
May 25, 2018 9:17:46 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-00
May 25, 2018 9:17:46 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(SAT) depth K=1 took 2017 ms
May 25, 2018 9:17:46 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(UNSAT) depth K=3 took 1348 ms
May 25, 2018 9:17:47 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(UNSAT) depth K=3 took 1184 ms
May 25, 2018 9:17:48 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(UNSAT) depth K=3 took 706 ms
May 25, 2018 9:17:48 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(UNSAT) depth K=3 took 385 ms
May 25, 2018 9:17:50 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(UNSAT) depth K=3 took 1730 ms
May 25, 2018 9:17:51 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-01
May 25, 2018 9:17:51 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-01(SAT) depth K=1 took 4579 ms
May 25, 2018 9:17:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(UNSAT) depth K=3 took 1588 ms
May 25, 2018 9:17:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(UNSAT) depth K=3 took 509 ms
May 25, 2018 9:17:53 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(UNSAT) depth K=3 took 532 ms
May 25, 2018 9:17:53 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(UNSAT) depth K=3 took 498 ms
May 25, 2018 9:17:54 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(UNSAT) depth K=3 took 465 ms
May 25, 2018 9:17:54 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-02
May 25, 2018 9:17:54 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(SAT) depth K=1 took 3311 ms
May 25, 2018 9:17:56 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-14(UNSAT) depth K=3 took 1802 ms
May 25, 2018 9:17:57 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-03
May 25, 2018 9:17:57 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(SAT) depth K=1 took 2602 ms
May 25, 2018 9:17:57 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-15(UNSAT) depth K=3 took 1698 ms
May 25, 2018 9:18:07 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-04
May 25, 2018 9:18:07 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(SAT) depth K=1 took 10729 ms
May 25, 2018 9:18:07 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 318 transitions.
May 25, 2018 9:18:08 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/318) took 505 ms. Total solver calls (SAT/UNSAT): 57(0/57)
May 25, 2018 9:18:08 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-06
May 25, 2018 9:18:08 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(SAT) depth K=1 took 1059 ms
May 25, 2018 9:18:09 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-07
May 25, 2018 9:18:09 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(SAT) depth K=1 took 677 ms
May 25, 2018 9:18:10 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-09
May 25, 2018 9:18:10 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(SAT) depth K=1 took 555 ms
May 25, 2018 9:18:11 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(7/318) took 3873 ms. Total solver calls (SAT/UNSAT): 452(15/437)
May 25, 2018 9:18:14 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-10
May 25, 2018 9:18:14 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(SAT) depth K=1 took 4253 ms
May 25, 2018 9:18:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(13/318) took 7709 ms. Total solver calls (SAT/UNSAT): 897(25/872)
May 25, 2018 9:18:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(UNSAT) depth K=4 took 20444 ms
May 25, 2018 9:18:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(17/318) took 11107 ms. Total solver calls (SAT/UNSAT): 1323(25/1298)
May 25, 2018 9:18:19 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-11
May 25, 2018 9:18:19 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(SAT) depth K=1 took 4870 ms
May 25, 2018 9:18:20 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-12
May 25, 2018 9:18:20 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(SAT) depth K=1 took 769 ms
May 25, 2018 9:18:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(21/318) took 14593 ms. Total solver calls (SAT/UNSAT): 1733(61/1672)
May 25, 2018 9:18:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(25/318) took 17923 ms. Total solver calls (SAT/UNSAT): 2127(95/2032)
May 25, 2018 9:18:29 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(29/318) took 21139 ms. Total solver calls (SAT/UNSAT): 2505(127/2378)
May 25, 2018 9:18:31 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-01(UNSAT) depth K=4 took 13535 ms
May 25, 2018 9:18:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(33/318) took 24325 ms. Total solver calls (SAT/UNSAT): 2867(155/2712)
May 25, 2018 9:18:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(37/318) took 27355 ms. Total solver calls (SAT/UNSAT): 3213(181/3032)
May 25, 2018 9:18:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(42/318) took 30871 ms. Total solver calls (SAT/UNSAT): 3623(210/3413)
May 25, 2018 9:18:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(47/318) took 34261 ms. Total solver calls (SAT/UNSAT): 4008(235/3773)
May 25, 2018 9:18:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(49/318) took 37279 ms. Total solver calls (SAT/UNSAT): 4345(254/4091)
May 25, 2018 9:18:45 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-00
May 25, 2018 9:18:45 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(SAT) depth K=2 took 25588 ms
May 25, 2018 9:18:46 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(UNSAT) depth K=4 took 14521 ms
May 25, 2018 9:18:49 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(52/318) took 41459 ms. Total solver calls (SAT/UNSAT): 4843(305/4538)
May 25, 2018 9:18:53 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-01
May 25, 2018 9:18:53 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-01(SAT) depth K=2 took 7682 ms
May 25, 2018 9:18:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(55/318) took 45681 ms. Total solver calls (SAT/UNSAT): 5332(339/4993)
May 25, 2018 9:18:56 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(56/318) took 49004 ms. Total solver calls (SAT/UNSAT): 5493(357/5136)
May 25, 2018 9:18:58 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(UNSAT) depth K=4 took 12162 ms
May 25, 2018 9:19:07 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(58/318) took 59165 ms. Total solver calls (SAT/UNSAT): 5812(390/5422)
May 25, 2018 9:19:09 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(UNSAT) depth K=4 took 11002 ms
May 25, 2018 9:19:09 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-02
May 25, 2018 9:19:09 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(SAT) depth K=2 took 16202 ms
May 25, 2018 9:19:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(59/318) took 62201 ms. Total solver calls (SAT/UNSAT): 5970(405/5565)
May 25, 2018 9:19:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(62/318) took 66921 ms. Total solver calls (SAT/UNSAT): 6438(442/5996)
May 25, 2018 9:19:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(64/318) took 72271 ms. Total solver calls (SAT/UNSAT): 6745(475/6270)
May 25, 2018 9:19:21 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-03
May 25, 2018 9:19:21 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(SAT) depth K=2 took 11932 ms
May 25, 2018 9:19:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(66/318) took 76601 ms. Total solver calls (SAT/UNSAT): 7048(490/6558)
May 25, 2018 9:19:25 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(UNSAT) depth K=4 took 16238 ms
May 25, 2018 9:19:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(69/318) took 80380 ms. Total solver calls (SAT/UNSAT): 7495(544/6951)
May 25, 2018 9:19:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(72/318) took 84105 ms. Total solver calls (SAT/UNSAT): 7933(575/7358)
May 25, 2018 9:19:36 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(75/318) took 88420 ms. Total solver calls (SAT/UNSAT): 8362(629/7733)
May 25, 2018 9:19:41 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(UNSAT) depth K=4 took 16181 ms
May 25, 2018 9:19:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(77/318) took 94013 ms. Total solver calls (SAT/UNSAT): 8643(660/7983)
May 25, 2018 9:19:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(82/318) took 97033 ms. Total solver calls (SAT/UNSAT): 8861(670/8191)
May 25, 2018 9:19:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(88/318) took 100791 ms. Total solver calls (SAT/UNSAT): 9122(685/8437)
May 25, 2018 9:19:51 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-04
May 25, 2018 9:19:51 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(SAT) depth K=2 took 30191 ms
May 25, 2018 9:19:52 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(91/318) took 104463 ms. Total solver calls (SAT/UNSAT): 9438(709/8729)
May 25, 2018 9:19:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(93/318) took 107933 ms. Total solver calls (SAT/UNSAT): 9707(754/8953)
May 25, 2018 9:19:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(UNSAT) depth K=4 took 14026 ms
May 25, 2018 9:20:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(95/318) took 112825 ms. Total solver calls (SAT/UNSAT): 9972(795/9177)
May 25, 2018 9:20:05 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(98/318) took 117370 ms. Total solver calls (SAT/UNSAT): 10362(832/9530)
May 25, 2018 9:20:07 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(UNSAT) depth K=4 took 11998 ms
May 25, 2018 9:20:09 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-06
May 25, 2018 9:20:09 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(SAT) depth K=2 took 18187 ms
May 25, 2018 9:20:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(100/318) took 122135 ms. Total solver calls (SAT/UNSAT): 10617(865/9752)
May 25, 2018 9:20:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(101/318) took 125301 ms. Total solver calls (SAT/UNSAT): 10743(880/9863)
May 25, 2018 9:20:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(103/318) took 130760 ms. Total solver calls (SAT/UNSAT): 10992(894/10098)
May 25, 2018 9:20:23 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(105/318) took 135817 ms. Total solver calls (SAT/UNSAT): 11237(919/10318)
May 25, 2018 9:20:25 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-07
May 25, 2018 9:20:25 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(SAT) depth K=2 took 15355 ms
May 25, 2018 9:20:26 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(UNSAT) depth K=4 took 18257 ms
May 25, 2018 9:20:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(107/318) took 139005 ms. Total solver calls (SAT/UNSAT): 11478(940/10538)
May 25, 2018 9:20:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(109/318) took 143516 ms. Total solver calls (SAT/UNSAT): 11715(954/10761)
May 25, 2018 9:20:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(111/318) took 147490 ms. Total solver calls (SAT/UNSAT): 11948(979/10969)
May 25, 2018 9:20:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(113/318) took 150643 ms. Total solver calls (SAT/UNSAT): 12177(1000/11177)
May 25, 2018 9:20:40 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(UNSAT) depth K=4 took 14144 ms
May 25, 2018 9:20:40 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-09
May 25, 2018 9:20:40 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(SAT) depth K=2 took 15239 ms
May 25, 2018 9:20:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(115/318) took 154780 ms. Total solver calls (SAT/UNSAT): 12402(1014/11388)
May 25, 2018 9:20:46 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(117/318) took 158891 ms. Total solver calls (SAT/UNSAT): 12623(1039/11584)
May 25, 2018 9:20:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(119/318) took 163093 ms. Total solver calls (SAT/UNSAT): 12840(1060/11780)
May 25, 2018 9:20:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-10
May 25, 2018 9:20:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(SAT) depth K=2 took 12169 ms
May 25, 2018 9:20:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(121/318) took 166489 ms. Total solver calls (SAT/UNSAT): 13053(1074/11979)
May 25, 2018 9:20:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(124/318) took 170359 ms. Total solver calls (SAT/UNSAT): 13365(1110/12255)
May 25, 2018 9:21:01 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(126/318) took 174038 ms. Total solver calls (SAT/UNSAT): 13568(1120/12448)
May 25, 2018 9:21:05 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(128/318) took 177833 ms. Total solver calls (SAT/UNSAT): 13767(1147/12620)
May 25, 2018 9:21:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(131/318) took 182338 ms. Total solver calls (SAT/UNSAT): 14058(1180/12878)
May 25, 2018 9:21:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(133/318) took 185730 ms. Total solver calls (SAT/UNSAT): 14247(1194/13053)
May 25, 2018 9:21:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(135/318) took 189158 ms. Total solver calls (SAT/UNSAT): 14432(1219/13213)
May 25, 2018 9:21:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(137/318) took 192533 ms. Total solver calls (SAT/UNSAT): 14613(1240/13373)
May 25, 2018 9:21:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(141/318) took 196258 ms. Total solver calls (SAT/UNSAT): 14843(1240/13603)
May 25, 2018 9:21:25 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-11
May 25, 2018 9:21:25 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(SAT) depth K=2 took 33277 ms
May 25, 2018 9:21:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(144/318) took 200779 ms. Total solver calls (SAT/UNSAT): 15005(1249/13756)
May 25, 2018 9:21:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(147/318) took 203821 ms. Total solver calls (SAT/UNSAT): 15158(1261/13897)
May 25, 2018 9:21:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(154/318) took 207441 ms. Total solver calls (SAT/UNSAT): 15480(1284/14196)
May 25, 2018 9:21:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(157/318) took 210567 ms. Total solver calls (SAT/UNSAT): 15603(1291/14312)
May 25, 2018 9:21:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(162/318) took 214508 ms. Total solver calls (SAT/UNSAT): 15788(1300/14488)
May 25, 2018 9:21:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(168/318) took 217598 ms. Total solver calls (SAT/UNSAT): 15977(1305/14672)
May 25, 2018 9:21:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(176/318) took 220637 ms. Total solver calls (SAT/UNSAT): 16205(1325/14880)
May 25, 2018 9:21:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(187/318) took 223778 ms. Total solver calls (SAT/UNSAT): 16475(1330/15145)
May 25, 2018 9:21:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(202/318) took 226959 ms. Total solver calls (SAT/UNSAT): 16836(1389/15447)
May 25, 2018 9:21:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-12
May 25, 2018 9:21:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(SAT) depth K=2 took 29473 ms
May 25, 2018 9:21:57 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(218/318) took 230071 ms. Total solver calls (SAT/UNSAT): 17183(1445/15738)
May 25, 2018 9:22:01 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(228/318) took 234107 ms. Total solver calls (SAT/UNSAT): 17402(1460/15942)
May 25, 2018 9:22:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(231/318) took 238325 ms. Total solver calls (SAT/UNSAT): 17618(1484/16134)
May 25, 2018 9:22:09 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(233/318) took 241646 ms. Total solver calls (SAT/UNSAT): 17757(1490/16267)
May 25, 2018 9:22:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(236/318) took 245854 ms. Total solver calls (SAT/UNSAT): 17958(1514/16444)
May 25, 2018 9:22:16 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(238/318) took 249030 ms. Total solver calls (SAT/UNSAT): 18087(1520/16567)
May 25, 2018 9:22:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(241/318) took 253140 ms. Total solver calls (SAT/UNSAT): 18273(1544/16729)
May 25, 2018 9:22:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(245/318) took 256999 ms. Total solver calls (SAT/UNSAT): 18507(1567/16940)
May 25, 2018 9:22:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(250/318) took 260341 ms. Total solver calls (SAT/UNSAT): 18777(1597/17180)
May 25, 2018 9:22:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(254/318) took 264329 ms. Total solver calls (SAT/UNSAT): 18975(1619/17356)
May 25, 2018 9:22:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-00
May 25, 2018 9:22:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(SAT) depth K=3 took 37915 ms
May 25, 2018 9:22:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(258/318) took 267863 ms. Total solver calls (SAT/UNSAT): 19157(1640/17517)
May 25, 2018 9:22:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(262/318) took 271009 ms. Total solver calls (SAT/UNSAT): 19323(1660/17663)
May 25, 2018 9:22:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(277/318) took 274241 ms. Total solver calls (SAT/UNSAT): 19693(1679/18014)
May 25, 2018 9:22:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(290/318) took 277491 ms. Total solver calls (SAT/UNSAT): 19992(1702/18290)
May 25, 2018 9:22:47 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 279724 ms. Total solver calls (SAT/UNSAT): 20133(1725/18408)
May 25, 2018 9:22:47 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 318 transitions.
May 25, 2018 9:22:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 3518 ms. Total solver calls (SAT/UNSAT): 235(0/235)
May 25, 2018 9:22:51 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 318835ms conformant to PINS in folder :/home/mcc/execution
May 25, 2018 9:23:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(UNSAT) depth K=5 took 164756 ms
May 25, 2018 9:24:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-01
May 25, 2018 9:24:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-01(SAT) depth K=3 took 92277 ms
May 25, 2018 9:24:30 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-01(UNSAT) depth K=5 took 65586 ms
May 25, 2018 9:24:58 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-02
May 25, 2018 9:24:58 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(SAT) depth K=3 took 52908 ms
May 25, 2018 9:25:22 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
May 25, 2018 9:25:22 AM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
May 25, 2018 9:25:22 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
WARNING: Unexpected error occurred while running SMT. Was verifying LamportFastMutEx-COL-5-ReachabilityCardinality-02 SMT depth 5
java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:404)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
... 3 more
May 25, 2018 9:25:22 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: During BMC, SMT solver timed out at depth 5
May 25, 2018 9:25:22 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solving timed out (3600000 secs) at depth 5
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
May 25, 2018 9:25:22 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
WARNING: Unexpected error occurred while running SMT. Was verifying LamportFastMutEx-COL-5-ReachabilityCardinality-04 K-induction depth 3
Exception in thread "Thread-8" java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:336)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
... 3 more
May 25, 2018 9:25:22 AM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 5/ 16 properties. Interrupting other analysis methods.

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-COL-5"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-COL-5.tgz
mv LamportFastMutEx-COL-5 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is LamportFastMutEx-COL-5, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r117-csrt-152666476500082"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;